libsel4bench: Remove ARMv6 and arm1136jf-s support
Remove support for ARMv6 and the only CPU we support for that
architecture. This is because support is being removed from the kernel
after removal of the only ARMv6 platform, kzm/imx31.
Signed-off-by: Kent McLeod <kent@kry10.com>
diff --git a/libsel4bench/arch_include/arm/armv/armv6/sel4bench/armv/sel4bench.h b/libsel4bench/arch_include/arm/armv/armv6/sel4bench/armv/sel4bench.h
deleted file mode 100644
index 1c258c1..0000000
--- a/libsel4bench/arch_include/arm/armv/armv6/sel4bench/armv/sel4bench.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230)
- *
- * SPDX-License-Identifier: BSD-2-Clause
- */
-#pragma once
-
-#include <sel4bench/cpu/sel4bench.h>
-
-#define SEL4BENCH_READ_CCNT(var) do { \
- asm volatile("b 2f\n\
- 1:mrc p15, 0, %[counter], c15, c12," SEL4BENCH_ARM1136_COUNTER_CCNT "\n\
- bx lr\n\
- 2:sub r8, pc, #16\n\
- .word 0xe7f000f0" \
- : [counter] "=r"(var) \
- : \
- : "r8", "lr"); \
-} while(0)
diff --git a/libsel4bench/arch_include/arm/cpu/arm1136jf-s/sel4bench/cpu/events.h b/libsel4bench/arch_include/arm/cpu/arm1136jf-s/sel4bench/cpu/events.h
deleted file mode 100644
index 081521c..0000000
--- a/libsel4bench/arch_include/arm/cpu/arm1136jf-s/sel4bench/cpu/events.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230)
- *
- * SPDX-License-Identifier: BSD-2-Clause
- */
-#pragma once
-//event definitions
-
-/* generic events */
-#define SEL4BENCH_EVENT_CACHE_L1I_MISS 0x00
-#define SEL4BENCH_EVENT_CACHE_L1D_MISS 0x0B
-#define SEL4BENCH_EVENT_TLB_L1I_MISS 0x03
-#define SEL4BENCH_EVENT_TLB_L1D_MISS 0x04
-#define SEL4BENCH_EVENT_MEMORY_ACCESS 0x10
-#define SEL4BENCH_EVENT_EXECUTE_INSTRUCTION 0x07
-#define SEL4BENCH_EVENT_BRANCH_MISPREDICT 0x06
-
-/* specific events */
-#define SEL4BENCH_EVENT_STALL_INSTRUCTION 0x01
-#define SEL4BENCH_EVENT_STALL_DATA 0x02
-#define SEL4BENCH_EVENT_EXECUTE_BRANCH 0x05
-#define SEL4BENCH_EVENT_CACHE_L1D_HIT 0x09
-#define SEL4BENCH_EVENT_CACHE_L1D_ACCESS 0x0A
-#define SEL4BENCH_EVENT_CACHE_L1D_WRITEBACK_HL 0x0C
-#define SEL4BENCH_EVENT_SOFTWARE_PC_CHANGE 0x0D
-#define SEL4BENCH_EVENT_TLB_L2_MISS 0x0F
-#define SEL4BENCH_EVENT_STALL_LSU_BUSY 0x11
-#define SEL4BENCH_EVENT_WRITE_BUFFER_DRAIN 0x12
-#define SEL4BENCH_EVENT_ETMEXTOUT_0 0x20
-#define SEL4BENCH_EVENT_ETMEXTOUT_1 0x21
-#define SEL4BENCH_EVENT_ETMEXTOUT 0x22
-#define SEL4BENCH_EVENT_CCNT 0xFF
diff --git a/libsel4bench/arch_include/arm/cpu/arm1136jf-s/sel4bench/cpu/private.h b/libsel4bench/arch_include/arm/cpu/arm1136jf-s/sel4bench/cpu/private.h
deleted file mode 100644
index fbef7c1..0000000
--- a/libsel4bench/arch_include/arm/cpu/arm1136jf-s/sel4bench/cpu/private.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230)
- *
- * SPDX-License-Identifier: BSD-2-Clause
- */
-#pragma once
-
-#include <stdint.h>
-#include <sel4bench/cpu/events.h>
-
-//function attributes
-//functions that need to be forced inline
-#define FASTFN inline __attribute__((always_inline))
-
-//functions that must not cache miss
-#define CACHESENSFN __attribute__((noinline, aligned(32)))
-
-//functions that will be called through pointers, but need to be fast
-#define KERNELFN __attribute__((noinline, flatten))
-
-//counters and related constants
-#define SEL4BENCH_ARM1136_NUM_COUNTERS 2
-
-#define SEL4BENCH_ARM1136_COUNTER_CCNT "1"
-#define SEL4BENCH_ARM1136_COUNTER_PMN0 "2"
-#define SEL4BENCH_ARM1136_COUNTER_PMN1 "3"
-
-/*
- * PMNC: ARM1136 Performance Monitor Control Register
- *
- * bits 31:28 = SBZ
- * bits 27:20 = EvtCount1 = event monitored by counter 1
- * bits 19:12 = EvtCount2 = event monitored by counter 2
- * bit 11 = X = export events to ETM
- * bits 10: 8 = Flag = read: determines if C0 (bit 8)/
- * C1 (bit 9)/CCNT (bit 10)
- * overflowed
- * write: clears overflow flag
- * bit 7 = SBZ
- * bits 6: 4 = IntEn = Enable interrupt reporting for
- * C0 (bit 4)/C1 (bit 5)/CCNT (bit 6)
- * bit 3 = D = cycle counter divides by 64
- * bit 2 = C = write 1 to reset CCNT to zero
- * bit 1 = P = write 1 to reset C0 and C1 to zero
- * bit 0 = E = enable all three counters
- */
-typedef union {
- struct {
- uint32_t E : 1;
- uint32_t P : 1;
- uint32_t C : 1;
- uint32_t D : 1;
- uint32_t IntEn : 3;
- uint32_t SBZ1 : 1;
- uint32_t Flag : 3;
- uint32_t X : 1;
- uint32_t EvtCount2 : 8;
- uint32_t EvtCount1 : 8;
- uint32_t SBZ2 : 4;
- };
- uint32_t raw;
-} sel4bench_arm1136_pmnc_t;
-
-static CACHESENSFN void sel4bench_private_set_pmnc(sel4bench_arm1136_pmnc_t val)
-{
- /*
- * The ARM1136 has a 3-cycle delay between changing the PMNC and the
- * counters reacting. So we insert 3 nops to cover for that. Aligning on a
- * cache line boundary guarantees that the nops won't cause anything
- * interesting to happen.
- */
- asm volatile (
- "mcr p15, 0, %0, c15, c12, 0;"
- "nop;"
- "nop;"
- "nop;"
- :
- : "r"(val.raw)
- );
-}
-static FASTFN sel4bench_arm1136_pmnc_t sel4bench_private_get_pmnc(void)
-{
- sel4bench_arm1136_pmnc_t val;
- asm volatile (
- "mrc p15, 0, %0, c15, c12, 0"
- : "=r"(val.raw)
- :
- );
- return val;
-}
-
-/*
- * CCNT: cycle counter
- */
-static FASTFN uint32_t sel4bench_private_get_ccnt()
-{
- uint32_t val;
- asm volatile (
- "mrc p15, 0, %0, c15, c12," SEL4BENCH_ARM1136_COUNTER_CCNT
- : "=r"(val)
- );
- return val;
-}
-
-/*
- * PMN0: event count 0
- */
-static FASTFN uint32_t sel4bench_private_get_pmn0()
-{
- uint32_t val;
- asm volatile (
- "mrc p15, 0, %0, c15, c12,"SEL4BENCH_ARM1136_COUNTER_PMN0
- : "=r"(val)
- );
- return val;
-}
-static FASTFN void sel4bench_private_set_pmn0(uint32_t val)
-{
- asm volatile (
- "mcr p15, 0, %0, c15, c12,"SEL4BENCH_ARM1136_COUNTER_PMN0
- : "=r"(val)
- );
-}
-
-/*
- * PMN1: event count 1
- */
-static FASTFN uint32_t sel4bench_private_get_pmn1()
-{
- uint32_t val;
- asm volatile (
- "mrc p15, 0, %0, c15, c12,"SEL4BENCH_ARM1136_COUNTER_PMN1
- : "=r"(val)
- );
- return val;
-}
-static FASTFN void sel4bench_private_set_pmn1(uint32_t val)
-{
- asm volatile (
- "mcr p15, 0, %0, c15, c12,"SEL4BENCH_ARM1136_COUNTER_PMN1
- : "=r"(val)
- );
-}
diff --git a/libsel4bench/arch_include/arm/cpu/arm1136jf-s/sel4bench/cpu/sel4bench.h b/libsel4bench/arch_include/arm/cpu/arm1136jf-s/sel4bench/cpu/sel4bench.h
deleted file mode 100644
index 68d262c..0000000
--- a/libsel4bench/arch_include/arm/cpu/arm1136jf-s/sel4bench/cpu/sel4bench.h
+++ /dev/null
@@ -1,247 +0,0 @@
-/*
- * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230)
- *
- * SPDX-License-Identifier: BSD-2-Clause
- */
-#pragma once
-
-#include <sel4bench/types.h>
-#include <sel4bench/cpu/private.h>
-#include <assert.h>
-#include <sel4/sel4.h>
-
-//begin system-mode stubs for sel4bench_* api functions
-static KERNELFN void sel4bench_private_init(void* data)
-{
- sel4bench_arm1136_pmnc_t init_pmnc = {
- {
- .C = 1, //reset CCNT
- .P = 1, //reset performance counters
- .Flag = 0x7, //reset overflow flags
- .E = 1, //start all counters
- }
- };
-
- //reset and enable all counters
- sel4bench_private_set_pmnc(init_pmnc);
-}
-
-static KERNELFN void sel4bench_private_destroy(void* data)
-{
- sel4bench_arm1136_pmnc_t kill_pmnc = {
- {
- .C = 1, //reset CCNT
- .P = 1, //reset performance counters
- .Flag = 0x7, //reset overflow flags
- .E = 0, //stop all counters
- }
- };
-
- //disable and reset all counters
- sel4bench_private_set_pmnc(kill_pmnc);
-}
-
-static KERNELFN void sel4bench_private_reset_gp_counters(void* data)
-{
- sel4bench_arm1136_pmnc_t reset_pmnc = sel4bench_private_get_pmnc();
- reset_pmnc.P = 1; //reset performance counters
- reset_pmnc.Flag = 0x3; //clear overflow flags on C0 and C1
- reset_pmnc.C = 0; //don't touch CCNT
- reset_pmnc.SBZ1 = 0; //per spec
- reset_pmnc.SBZ2 = 0; //per spec
-
- //reset and enable all counters
- sel4bench_private_set_pmnc(reset_pmnc);
-}
-
-static KERNELFN void sel4bench_private_get_cycle_count(void* data)
-{
- //get contents of PMNC
- sel4bench_arm1136_pmnc_t pmnc_contents = sel4bench_private_get_pmnc();
- pmnc_contents.Flag = 0; //don't reset anything
- pmnc_contents.SBZ1 = 0; //per spec
- pmnc_contents.SBZ2 = 0; //per spec
-
- //store current state
- sel4bench_arm1136_pmnc_t pmnc_contents_restore = pmnc_contents;
-
- //disable counters
- pmnc_contents.E = 0;
- sel4bench_private_set_pmnc(pmnc_contents);
-
- //read value of specified counter
- *(uint32_t*)data = sel4bench_private_get_ccnt();
-
- //restore previous state
- sel4bench_private_set_pmnc(pmnc_contents_restore);
-}
-
-static KERNELFN void sel4bench_private_get_counter(void* data)
-{
- //get contents of PMNC
- sel4bench_arm1136_pmnc_t pmnc_contents = sel4bench_private_get_pmnc();
- pmnc_contents.Flag = 0; //don't reset anything
- pmnc_contents.SBZ1 = 0; //per spec
- pmnc_contents.SBZ2 = 0; //per spec
-
- //store current state
- sel4bench_arm1136_pmnc_t pmnc_contents_restore = pmnc_contents;
-
- //disable counters
- pmnc_contents.E = 0;
- sel4bench_private_set_pmnc(pmnc_contents);
-
- //read value of specified counter
- *(uint32_t*)data = *(uint32_t*)data ? sel4bench_private_get_pmn1() : sel4bench_private_get_pmn0();
-
- //restore previous state
- sel4bench_private_set_pmnc(pmnc_contents_restore);
-}
-
-static KERNELFN void sel4bench_private_get_counters(void* data)
-{
- //get contents of PMNC
- sel4bench_arm1136_pmnc_t pmnc_contents = sel4bench_private_get_pmnc();
- pmnc_contents.Flag = 0; //don't reset anything
- pmnc_contents.SBZ1 = 0; //per spec
- pmnc_contents.SBZ2 = 0; //per spec
-
- //store current state
- sel4bench_arm1136_pmnc_t pmnc_contents_restore = pmnc_contents;
-
- //disable counters
- pmnc_contents.E = 0;
- sel4bench_private_set_pmnc(pmnc_contents);
-
- uint32_t* args = (uint32_t*)data;
- uint32_t mask = args[0];
- ccnt_t* values = (ccnt_t*)args[1];
-
- //read value of specified counters
- if (mask & 1) {
- values[0] = sel4bench_private_get_pmn0();
- }
- if (mask & 2) {
- values[1] = sel4bench_private_get_pmn1();
- }
-
- //read CCNT
- args[0] = sel4bench_private_get_ccnt();
-
- //restore previous state
- sel4bench_private_set_pmnc(pmnc_contents_restore);
-}
-
-static KERNELFN void sel4bench_private_set_count_event(void* data)
-{
- //bring in arguments
- uint32_t counter = ((uint32_t)data) >> 31;
- uint32_t event = ((uint32_t)data) & ~(1U << 31);
-
- //get contents of PMNC
- sel4bench_arm1136_pmnc_t pmnc_contents = sel4bench_private_get_pmnc();
- pmnc_contents.Flag = 0; //don't reset anything
- pmnc_contents.SBZ1 = 0; //per spec
- pmnc_contents.SBZ2 = 0; //per spec
-
- //store current state
- sel4bench_arm1136_pmnc_t pmnc_contents_restore = pmnc_contents;
-
- //stop counters
- pmnc_contents.E = 0;
- sel4bench_private_set_pmnc(pmnc_contents);
-
- //setup specified counter
- if (counter) {
- //setting counter 1
- pmnc_contents_restore.EvtCount2 = event;
- sel4bench_private_set_pmn1(0);
- } else {
- //setting counter 0
- pmnc_contents_restore.EvtCount1 = event;
- sel4bench_private_set_pmn0(0);
-
- }
-
- //restore previous state
- sel4bench_private_set_pmnc(pmnc_contents_restore);
-}
-
-/* Silence warnings about including the following functions when seL4_DebugRun
- * is not enabled when we are not calling them. If we actually call these
- * functions without seL4_DebugRun enabled, we'll get a link failure, so this
- * should be OK.
- */
-void seL4_DebugRun(void (* userfn) (void *), void* userarg);
-
-//begin actual sel4bench_* api functions
-
-static FASTFN void sel4bench_init()
-{
- seL4_DebugRun(&sel4bench_private_init, NULL);
-}
-
-static FASTFN void sel4bench_destroy()
-{
- seL4_DebugRun(&sel4bench_private_destroy, NULL);
-}
-
-static FASTFN seL4_Word sel4bench_get_num_counters()
-{
- return SEL4BENCH_ARM1136_NUM_COUNTERS;
-}
-
-static FASTFN ccnt_t sel4bench_get_cycle_count()
-{
- uint32_t val = 0;
- seL4_DebugRun(&sel4bench_private_get_cycle_count, &val);
- return val;
-}
-
-static FASTFN ccnt_t sel4bench_get_counter(counter_t counter)
-{
- assert(counter < sel4bench_get_num_counters()); //range check
-
- uint32_t val = counter;
- seL4_DebugRun(&sel4bench_private_get_counter, &val);
- return val;
-}
-
-static FASTFN ccnt_t sel4bench_get_counters(counter_bitfield_t mask, ccnt_t* values)
-{
- assert(mask & (sel4bench_get_num_counters() - 1)); //there are only two counters, so there should be no other 1 bits
- assert(values); //NULL guard -- because otherwise we'll get a kernel fault
-
- uint32_t args[2] = {mask, (uint32_t)values};
- //entry 0: in = mask, out = ccnt
- //entry 1: in = values
- seL4_DebugRun(&sel4bench_private_get_counters, args);
- return args[0];
-}
-
-static FASTFN void sel4bench_set_count_event(counter_t counter, event_id_t event)
-{
- assert(counter < sel4bench_get_num_counters()); //range check
-
- seL4_DebugRun(&sel4bench_private_set_count_event, (void*)(event | ((counter & 1U) << 31)));
-}
-
-static FASTFN void sel4bench_stop_counters(counter_bitfield_t mask)
-{
- /* all three ARM1136 counters have to start at the same time...
- * so we just start them all at init time and make this a no-op
- */
-}
-
-static FASTFN void sel4bench_reset_counters(void)
-{
- seL4_DebugRun(&sel4bench_private_reset_gp_counters, NULL);
-}
-
-static FASTFN void sel4bench_start_counters(counter_bitfield_t mask)
-{
- /* all three ARM1136 counters have to start at the same time...
- * so we just start them all at init time and make this reset them
- */
- sel4bench_reset_counters();
-}
diff --git a/libsel4bench/include/sel4bench/sel4bench.h b/libsel4bench/include/sel4bench/sel4bench.h
index 81cb593..6cb0ef9 100644
--- a/libsel4bench/include/sel4bench/sel4bench.h
+++ b/libsel4bench/include/sel4bench/sel4bench.h
@@ -22,9 +22,7 @@
* can measure the performance of your software. It will also work out whether
* certain operations need to be done in kernel mode, and perform kernel code
* injection calls to make them happen. As a result, expect that any library
- * call could potentially result in a syscall. (This is of particular note on
- * the KZM/ARM1136, for which even reading the cycle counter must be done in
- * kernel mode.)
+ * call could potentially result in a syscall.
*
* It also goes out of its way to ensure that there's always a cycle counter
* available for use. `sel4bench_init()` will start this running, and
@@ -162,8 +160,7 @@
/**
* Stop counting events on a set of performance counters.
*
- * Note: Some processors (notably, the KZM/ARM1136) may not support this
- * operation.
+ * Note: Some processors may not support this operation.
*
* @param counters bitfield indicating which counter(s) to stop
*/
diff --git a/libsel4bench/src/arch/arm/cpu/arm1136jf-s/event_counters.c b/libsel4bench/src/arch/arm/cpu/arm1136jf-s/event_counters.c
deleted file mode 100644
index ee403ad..0000000
--- a/libsel4bench/src/arch/arm/cpu/arm1136jf-s/event_counters.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230)
- *
- * SPDX-License-Identifier: BSD-2-Clause
- */
-
-#include <utils/util.h>
-
-#include "../../event_counters.h"
-
-const char* const sel4bench_arch_event_counter_data[] = {
- NAME_EVENT(CACHE_L1I_MISS , "CACHE_L1I_MISS"),
- NAME_EVENT(STALL_INSTRUCTION , "STALL_INSTRUCTION"),
- NAME_EVENT(STALL_DATA , "STALL_DATA"),
- NAME_EVENT(TLB_L1I_MISS , "TLB_L1I_MISS"),
- NAME_EVENT(TLB_L1D_MISS , "TLB_L1D_MISS"),
- NAME_EVENT(EXECUTE_BRANCH , "EXECUTE_BRANCH"),
- NAME_EVENT(BRANCH_MISPREDICT , "BRANCH_MISPREDICT"),
- NAME_EVENT(EXECUTE_INSTRUCTION , "EXECUTE_INSTRUCTION"),
- NAME_EVENT(CACHE_L1D_HIT , "CACHE_L1D_HIT"),
- NAME_EVENT(CACHE_L1D_ACCESS , "CACHE_L1D_ACCESS"),
- NAME_EVENT(CACHE_L1D_MISS , "CACHE_L1D_MISS"),
- NAME_EVENT(CACHE_L1D_WRITEBACK_HL, "CACHE_L1D_WRITEBACK_HL"),
- NAME_EVENT(SOFTWARE_PC_CHANGE , "SOFTWARE_PC_CHANGE"),
- NAME_EVENT(TLB_L2_MISS , "TLB_L2_MISS"),
- NAME_EVENT(MEMORY_ACCESS , "MEMORY_ACCESS"),
- NAME_EVENT(STALL_LSU_BUSY , "STALL_LSU_BUSY"),
- NAME_EVENT(WRITE_BUFFER_DRAIN , "WRITE_BUFFER_DRAIN"),
- NAME_EVENT(ETMEXTOUT_0 , "ETMEXTOUT_0"),
- NAME_EVENT(ETMEXTOUT_1 , "ETMEXTOUT_1"),
- NAME_EVENT(ETMEXTOUT , "ETMEXTOUT"),
- NAME_EVENT(CCNT , "CCNT")
-};
-
-const char* const sel4bench_cpu_event_counter_data[] = {
-};
-
-int
-sel4bench_arch_get_num_counters(void)
-{
- return ARRAY_SIZE(sel4bench_arch_event_counter_data);
-}
-
-int
-sel4bench_cpu_get_num_counters(void)
-{
- return ARRAY_SIZE(sel4bench_cpu_event_counter_data);
-}
