Piotr Zierhoffer | 2843cb7 | 2019-01-10 16:19:08 +0100 | [diff] [blame] | 1 | debugArea: Memory.MappedMemory @ sysbus 0x0 |
| 2 | size: 0x1000 |
| 3 | |
| 4 | smallRom: Memory.MappedMemory @ sysbus 0x1000 |
| 5 | size: 0xF000 |
| 6 | |
Piotr Zierhoffer | bdd52b9 | 2017-11-15 11:42:28 +0100 | [diff] [blame] | 7 | flash: Memory.MappedMemory @ sysbus 0x60000000 |
| 8 | size: 0x40000 |
| 9 | |
| 10 | ddr: Memory.MappedMemory @ sysbus 0x80000000 |
| 11 | size: 0x4000000 |
| 12 | |
| 13 | uart: UART.MiV_CoreUART @ sysbus 0x70001000 |
| 14 | clockFrequency: 66000000 |
| 15 | |
Mateusz Hołenko | 22a433b | 2018-03-12 16:52:17 +0100 | [diff] [blame] | 16 | cpu: CPU.RiscV32 @ sysbus |
Michał Szprejda | dc9cd37 | 2023-10-13 15:08:10 +0200 | [diff] [blame] | 17 | cpuType: "rv32imaf_zicsr_zifencei" |
Mateusz Hołenko | 5a0ad57 | 2018-06-01 13:07:46 +0200 | [diff] [blame] | 18 | privilegeArchitecture: PrivilegeArchitecture.Priv1_09 |
Mateusz Holenko | efd14ba | 2019-05-13 15:24:12 +0200 | [diff] [blame] | 19 | timeProvider: clint |
Piotr Zierhoffer | bdd52b9 | 2017-11-15 11:42:28 +0100 | [diff] [blame] | 20 | |
| 21 | plic: IRQControllers.PlatformLevelInterruptController @ sysbus 0x40000000 |
Mateusz Holenko | 0d9f10b | 2021-03-24 17:06:02 +0100 | [diff] [blame] | 22 | 0 -> cpu@11 |
Piotr Zierhoffer | bdd52b9 | 2017-11-15 11:42:28 +0100 | [diff] [blame] | 23 | numberOfSources: 31 |
Mateusz Holenko | 0d9f10b | 2021-03-24 17:06:02 +0100 | [diff] [blame] | 24 | numberOfContexts: 1 |
Piotr Zierhoffer | bdd52b9 | 2017-11-15 11:42:28 +0100 | [diff] [blame] | 25 | prioritiesEnabled : false |
| 26 | |
| 27 | // Power/Reset/Clock/Interrupt |
Michał Szprejda | fff0081 | 2018-01-17 14:37:35 +0100 | [diff] [blame] | 28 | clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x44000000 |
Piotr Zierhoffer | d382a37 | 2018-05-04 15:30:31 +0200 | [diff] [blame] | 29 | frequency: 66000000 |
Mateusz Hołenko | 7472ae5 | 2018-05-23 14:01:48 +0200 | [diff] [blame] | 30 | [0, 1] -> cpu@[3, 7] |
Piotr Zierhoffer | bdd52b9 | 2017-11-15 11:42:28 +0100 | [diff] [blame] | 31 | |
| 32 | gpioInputs: GPIOPort.MiV_CoreGPIO @ sysbus 0x70002000 |
| 33 | -> plic@29 |
| 34 | |
| 35 | gpioOutputs: GPIOPort.MiV_CoreGPIO @ sysbus 0x70005000 |
| 36 | |
| 37 | timer0: Timers.MiV_CoreTimer @ sysbus 0x70003000 |
| 38 | -> plic@30 |
| 39 | clockFrequency: 66000000 |
| 40 | |
| 41 | timer1: Timers.MiV_CoreTimer @ sysbus 0x70004000 |
| 42 | -> plic@31 |
| 43 | clockFrequency: 66000000 |