[#59790] ARMv8: Add regression test for checking EL and SS
diff --git a/tests/platforms/ARMv8A.robot b/tests/platforms/ARMv8A.robot index d2dfc73..201afa1 100644 --- a/tests/platforms/ARMv8A.robot +++ b/tests/platforms/ARMv8A.robot
@@ -55,6 +55,17 @@ Wait For Log Entry Read from ${timer_register_name} *** Test Cases *** +Should Get Correct EL and SS on CPU Creation + # This platform uses `Cortex-A53` CPU - ARMv8A + # We only check if EL and SS are reflected correctly on C# side, for their usage in peripherals + Create Machine + + ${ss}= Execute Command sysbus.cpu SecurityState + ${el}= Execute Command sysbus.cpu ExceptionLevel + + Should Be Equal As Strings ${ss.split()[0].strip()} Secure + Should Be Equal As Strings ${el.split()[0].strip()} EL3_MonitorMode + Test Accessing ARM Generic Timer Registers Through AArch64 System Registers Create Machine Create Log Tester 0
diff --git a/tests/platforms/ARMv8R.robot b/tests/platforms/ARMv8R.robot index 5be458a..13fc1a2 100644 --- a/tests/platforms/ARMv8R.robot +++ b/tests/platforms/ARMv8R.robot
@@ -704,6 +704,17 @@ ### Prerequisites +Should Get Correct EL and SS on CPU Creation + # This platform uses `Cortex-R52` CPU - ARMv8R in AArch32 configuration + # We only check if EL and SS are reflected correctly on C# side, for their usage in peripherals + Initialize Emulation + + ${ss}= Execute Command sysbus.cpu SecurityState + ${el}= Execute Command sysbus.cpu ExceptionLevel + + Should Be Equal As Strings ${ss.split()[0].strip()} NonSecure + Should Be Equal As Strings ${el.split()[0].strip()} EL2_HypervisorMode + Check Changing Privilege Level From Monitor [Template] Check Changing Privilege Level From Monitor Template [Tags] Prerequisite