Integrate LLVM to llvm/llvm-project@bdd8381f5b7e (#25103) Adapt IREE code to API rename from this commit: 68aa3b9000f9 [mlir][vector][NFC] Rename getShapeForUnroll to getIterationShapeToUnroll (#232648) Add a bazel fixup commit to the LLVM fork: [Bazel] Fixes 092c876 which was needed due to this commit: 092c87674f0f [mlir][OpenACC] Decouple frontend support from GPU operations (#233103) Adapt ROCM test due to commits: b453ff8c276c [AMDGPU] Hardwire SRAMECC ON for gfx12.5 (#232985) 3d88acd425bf [AMDGPU] Omit hardwired-on SRAMECC ELF mode (#228268) Co-Authored-By: Claude Code Signed-off-by: Stefan Schuermans <schuermans@roofline.ai>
diff --git a/compiler/plugins/target/ROCM/test/default_subgroup_size.mlir b/compiler/plugins/target/ROCM/test/default_subgroup_size.mlir index c7a65a8..b073d0d 100644 --- a/compiler/plugins/target/ROCM/test/default_subgroup_size.mlir +++ b/compiler/plugins/target/ROCM/test/default_subgroup_size.mlir
@@ -18,10 +18,10 @@ // export does not specify one. CDNA5 only supports wave32; asking LLVM for // wave64 silently produces an executable with no kernels. -// CDNA5 has selectable XNACK, so the ELF target ID keeps the XNACK feature -// bits. Check the little-endian e_flags at byte offset 48: gfx1250 (0x49), -// SRAMECC any (0x400), and XNACK any (0x100). -// ELF: data = dense<"0x7F454C46{{([0-9A-F]{88})}}49050000 +// CDNA5 has selectable XNACK but SRAMECC has no on/off modes, so the ELF target +// ID keeps the XNACK feature bits but not SRAMECC. Check the little-endian +// e_flags at byte offset 48: gfx1250 (0x49) and XNACK any (0x100). +// ELF: data = dense<"0x7F454C46{{([0-9A-F]{88})}}49010000 // Likewise for gfx942: (0x4c), SRAMECC any (0x400), and XNACK any (0x100). // RUN: iree-opt --iree-hal-transformation-pipeline --iree-hal-target-device=hip \
diff --git a/compiler/plugins/target/ROCM/test/target_feature_serialization.mlir b/compiler/plugins/target/ROCM/test/target_feature_serialization.mlir index 09db9f1..171f6f8 100644 --- a/compiler/plugins/target/ROCM/test/target_feature_serialization.mlir +++ b/compiler/plugins/target/ROCM/test/target_feature_serialization.mlir
@@ -55,13 +55,14 @@ // IR-ECCOFF-DAG: !{i32 1, !"amdgpu.xnack", i32 1} // gfx1250 supports selectable XNACK on/off modes (LLVM 05e432a8597f), so these -// target IDs are valid and the modes reach LLVM as module flags. +// target IDs are valid and the modes reach LLVM as module flags. SRAMECC is +// hardwired on for gfx1250 and is omitted from the ELF target ID. // RUN: rm -rf %t && mkdir -p %t // RUN: iree-opt --iree-hal-transformation-pipeline --iree-hal-target-device=hip \ // RUN: --iree-rocm-target=mi455x --iree-rocm-target-features=-xnack \ // RUN: --iree-hal-dump-executable-intermediates-to=%t --iree-rocm-container-type=hsaco %s | FileCheck %s --check-prefix=ELF-CDNA5OFF // RUN: cat %t/*.linked.ll | FileCheck %s --check-prefix=IR-CDNA5OFF -// ELF-CDNA5OFF: data = dense<"0x7F454C46{{([0-9A-F]{88})}}49060000 +// ELF-CDNA5OFF: data = dense<"0x7F454C46{{([0-9A-F]{88})}}49020000 // IR-CDNA5OFF: target triple = "amdgpu12.50-amd-amdhsa" // IR-CDNA5OFF-DAG: !{i32 1, !"amdgpu.xnack", i32 0} @@ -70,7 +71,7 @@ // RUN: --iree-rocm-target=cdna5 --iree-rocm-target-features=+xnack \ // RUN: --iree-hal-dump-executable-intermediates-to=%t --iree-rocm-container-type=hsaco %s | FileCheck %s --check-prefix=ELF-CDNA5ON // RUN: cat %t/*.linked.ll | FileCheck %s --check-prefix=IR-CDNA5ON -// ELF-CDNA5ON: data = dense<"0x7F454C46{{([0-9A-F]{88})}}49070000 +// ELF-CDNA5ON: data = dense<"0x7F454C46{{([0-9A-F]{88})}}49030000 // IR-CDNA5ON: target triple = "amdgpu12.50-amd-amdhsa" // IR-CDNA5ON-DAG: !{i32 1, !"amdgpu.xnack", i32 1}
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/Codegen/IR/IREECodegenOps.cpp b/compiler/src/iree/compiler/Codegen/Dialect/Codegen/IR/IREECodegenOps.cpp index 1b76780..90af9fb 100644 --- a/compiler/src/iree/compiler/Codegen/Dialect/Codegen/IR/IREECodegenOps.cpp +++ b/compiler/src/iree/compiler/Codegen/Dialect/Codegen/IR/IREECodegenOps.cpp
@@ -441,7 +441,8 @@ iterationBounds.append(inverseMap.compose(combinedOuterShapes)); } -std::optional<SmallVector<int64_t, 4>> InnerTiledOp::getShapeForUnroll() { +std::optional<SmallVector<int64_t, 4>> +InnerTiledOp::getIterationShapeToUnroll() { SmallVector<int64_t, 4> shape; getIterationBounds(shape); return shape;
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/Codegen/IR/IREECodegenOps.td b/compiler/src/iree/compiler/Codegen/Dialect/Codegen/IR/IREECodegenOps.td index 47e454d..aaf0947 100644 --- a/compiler/src/iree/compiler/Codegen/Dialect/Codegen/IR/IREECodegenOps.td +++ b/compiler/src/iree/compiler/Codegen/Dialect/Codegen/IR/IREECodegenOps.td
@@ -260,7 +260,7 @@ DestinationStyleOpInterface, DeclareOpInterfaceMethods<ValueBoundsOpInterface, ["populateBoundsForShapedValueDim"]>, - DeclareOpInterfaceMethods<VectorUnrollOpInterface, ["getShapeForUnroll"]>, + DeclareOpInterfaceMethods<VectorUnrollOpInterface, ["getIterationShapeToUnroll"]>, DeclareOpInterfaceMethods<TilingInterface, ["getIterationDomain", "getLoopIteratorTypes",
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/Codegen/Transforms/UnrollInnerTiled.cpp b/compiler/src/iree/compiler/Codegen/Dialect/Codegen/Transforms/UnrollInnerTiled.cpp index 4a24d1e..8014def 100644 --- a/compiler/src/iree/compiler/Codegen/Dialect/Codegen/Transforms/UnrollInnerTiled.cpp +++ b/compiler/src/iree/compiler/Codegen/Dialect/Codegen/Transforms/UnrollInnerTiled.cpp
@@ -88,7 +88,7 @@ "vector unrolling expects the native shape or native shape call " "back function to be set"); std::optional<SmallVector<int64_t, 4>> maybeUnrollShape = - tiledOp.getShapeForUnroll(); + tiledOp.getIterationShapeToUnroll(); if (!maybeUnrollShape) { return rewriter.notifyMatchFailure( tiledOp, "unexpected failure to get unroll shape");
diff --git a/third_party/llvm-project b/third_party/llvm-project index 03ddfac..bdd8381 160000 --- a/third_party/llvm-project +++ b/third_party/llvm-project
@@ -1 +1 @@ -Subproject commit 03ddfac14e84ebaea0dc8a1a79ea28b09287fb5b +Subproject commit bdd8381f5b7e39e01b520ac2e99982bf5e926f59