[ROCM][Codegen] Add experimental amdgcn SPIR-V path (#24499)

Adds an experimental ROCm amdgcn SPIR-V path that emits HIP-loadable
SPIR-V instead of native HSACO, enabling the HIP runtime to JIT compile
device code for the target GPU. The main changes are:

- `--iree-rocm-use-spirv` flag to select `rocm-spirv-fb` for HIP
targets.
- ROCDL prepare for SPIR-V: Adjust address spaces, calling conventions,
remove AMDGPU-specific function attributes.
- ROCMTarget: Serialize LLVM SPIR-V output into a HIP-loadable offload
bundle.
- Focused lit coverage for lowering, serialization, command-line
handling.

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Signed-off-by: Austin Lu <aulu@amd.com>
Co-authored-by: Jakub Kuderski <jakub@nod-labs.com>