[NFC] Add StrategyTilingLevel enum class to clear tiling level meaning. (#8633)
The codegen used to use TilingLevel::L1Tiles and
TilingLevel::VectorTiles. This is confusing in strategy approach because
they are not targeting tiling sizes for L1 and vector. They are actually
the tiling sizes for parallel dims and reduction dims. Correct the
variable name to make confusion less.
diff --git a/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp b/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp
index 138d7cd..eb0ea6b 100644
--- a/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp
+++ b/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp
@@ -378,25 +378,25 @@
int vectorSize) {
// Hardcoded tiling sizes {1, 1, ..., 8, 32, 16}.
// The tiling for parallel dims and reduction dims should be separated.
- SmallVector<int64_t> l1TileSizes;
+ SmallVector<int64_t> parallelTileSizes;
int64_t nLoops = cast<linalg::LinalgOp>(op.getOperation()).getNumLoops();
- l1TileSizes.append(nLoops - 3, 1);
- l1TileSizes.push_back(
+ parallelTileSizes.append(nLoops - 3, 1);
+ parallelTileSizes.push_back(
getMaxTileSize(0, flowTileSizes[nLoops - 3], 8, vectorSize));
- l1TileSizes.push_back(
+ parallelTileSizes.push_back(
getMaxTileSize(0, flowTileSizes[nLoops - 2], 32, vectorSize));
- l1TileSizes.push_back(0);
+ parallelTileSizes.push_back(0);
auto lhsShapedType = op.lhs().getType().cast<ShapedType>();
int64_t K = lhsShapedType.getShape().back();
- SmallVector<int64_t> vectorTileSizes;
- vectorTileSizes.append(nLoops - 1, 0);
- vectorTileSizes.push_back(getMaxTileSize(0, K, 16, vectorSize));
+ SmallVector<int64_t> reductionTileSizes;
+ reductionTileSizes.append(nLoops - 1, 0);
+ reductionTileSizes.push_back(getMaxTileSize(0, K, 16, vectorSize));
TileSizesListType tileSizes;
tileSizes.emplace_back(flowTileSizes.begin(), flowTileSizes.end());
- tileSizes.push_back(l1TileSizes);
- tileSizes.push_back(vectorTileSizes);
+ tileSizes.push_back(parallelTileSizes);
+ tileSizes.push_back(reductionTileSizes);
return setOpConfigAndEntryPointFnTranslation(
entryPointFn, op, tileSizes,
@@ -602,30 +602,31 @@
maxTileSizes);
// Set the Next level tile sizes.
- SmallVector<int64_t> l1TileSizes(numLoops, 0);
+ SmallVector<int64_t> parallelTileSizes(numLoops, 0);
Optional<SmallVector<int64_t, 4>> staticLoopRanges =
linalgOp.getStaticLoopRanges();
for (auto loopNum : llvm::seq<unsigned>(0, numLoops)) {
if (flowTileSizes[loopNum]) {
- l1TileSizes[loopNum] =
+ parallelTileSizes[loopNum] =
getMaxTileSize(0, flowTileSizes[loopNum], minTileSizes[loopNum],
minTileSizes[loopNum]);
} else {
// If the flow level tile size is zero, and static loop range is 0 as
// well, set the tile sizes here to zero as well.
- l1TileSizes[loopNum] =
+ parallelTileSizes[loopNum] =
(staticLoopRanges && staticLoopRanges.getValue()[loopNum] == 1)
? 0
: minTileSizes[loopNum];
}
}
- SmallVector<int64_t> vectorTileSizes;
- splitParallelAndReductionTiles(linalgOp, l1TileSizes, vectorTileSizes);
+ SmallVector<int64_t> reductionTileSizes;
+ splitParallelAndReductionTiles(linalgOp, parallelTileSizes,
+ reductionTileSizes);
TileSizesListType tileSizes;
tileSizes.push_back(flowTileSizes);
- tileSizes.push_back(l1TileSizes);
- tileSizes.push_back(vectorTileSizes);
+ tileSizes.push_back(parallelTileSizes);
+ tileSizes.push_back(reductionTileSizes);
// For non-tensor based ops use the Buffer ops pipeline.
auto passPipeline =
@@ -641,7 +642,7 @@
static LogicalResult setConvRootConfig(
FuncOp entryPointFn, linalg::LinalgOp convOp,
ArrayRef<LoopTilingAndDistributionInfo> tiledLoops,
- ArrayRef<int64_t> targetL1TileSizes, int64_t vectorSize) {
+ ArrayRef<int64_t> targetTileSizes, int64_t vectorSize) {
if (!isa<linalg::Conv2DNhwcHwcfOp, linalg::DepthwiseConv2DNhwcHwcOp>(
convOp.getOperation())) {
return failure();
@@ -665,23 +666,24 @@
// Shapes of N, OH, OW, OC, KH, KW, (IC)
Optional<SmallVector<int64_t, 4>> shapes = convOp.getStaticLoopRanges();
- SmallVector<int64_t> l1TileSizes(targetL1TileSizes.begin(),
- targetL1TileSizes.end());
- for (auto i : llvm::seq<unsigned>(0, l1TileSizes.size())) {
+ SmallVector<int64_t> parallelTileSizes(targetTileSizes.begin(),
+ targetTileSizes.end());
+ for (auto i : llvm::seq<unsigned>(0, parallelTileSizes.size())) {
auto tileSize = flowTileSizes[i] ? flowTileSizes[i] : shapes.getValue()[i];
// If the tile size is intended to be 1, do not adjust it to `vectorSize`.
// The ops will be decomposed to lower-rank named ops.
- if (l1TileSizes[i] != 1) {
- l1TileSizes[i] = getMaxTileSize(0, tileSize, l1TileSizes[i], vectorSize);
+ if (parallelTileSizes[i] != 1) {
+ parallelTileSizes[i] =
+ getMaxTileSize(0, tileSize, parallelTileSizes[i], vectorSize);
}
}
- SmallVector<int64_t> vectorTileSizes;
- splitParallelAndReductionTiles(convOp, l1TileSizes, vectorTileSizes);
+ SmallVector<int64_t> reductionTileSizes;
+ splitParallelAndReductionTiles(convOp, parallelTileSizes, reductionTileSizes);
TileSizesListType tileSizes;
tileSizes.push_back(flowTileSizes);
- tileSizes.push_back(l1TileSizes);
- tileSizes.push_back(vectorTileSizes);
+ tileSizes.push_back(parallelTileSizes);
+ tileSizes.push_back(reductionTileSizes);
return setOpConfigAndEntryPointFnTranslation(
entryPointFn, convOp, tileSizes,
DispatchLoweringPassPipeline::CPUConvTileAndDecomposeExpert);
@@ -693,8 +695,8 @@
auto linalgOp = cast<linalg::LinalgOp>(convOp.getOperation());
int64_t vectorSize =
getVectorSize(entryPointFn, convOp.getResult(0).getType());
- SmallVector<int64_t> l1TileSizes = {1, 1, 8, vectorSize * 2, 1, 1, 8};
- return setConvRootConfig(entryPointFn, linalgOp, tiledLoops, l1TileSizes,
+ SmallVector<int64_t> targetTileSizes = {1, 1, 8, vectorSize * 2, 1, 1, 8};
+ return setConvRootConfig(entryPointFn, linalgOp, tiledLoops, targetTileSizes,
vectorSize);
}
@@ -706,8 +708,8 @@
auto linalgOp = cast<linalg::LinalgOp>(convOp.getOperation());
int64_t vectorSize =
getVectorSize(entryPointFn, convOp.getResult(0).getType());
- SmallVector<int64_t> l1TileSizes = {1, 1, 8, vectorSize * 2, 1, 3};
- return setConvRootConfig(entryPointFn, linalgOp, tiledLoops, l1TileSizes,
+ SmallVector<int64_t> targetTileSizes = {1, 1, 8, vectorSize * 2, 1, 3};
+ return setConvRootConfig(entryPointFn, linalgOp, tiledLoops, targetTileSizes,
vectorSize);
}
diff --git a/iree/compiler/Codegen/LLVMCPU/KernelDispatch.h b/iree/compiler/Codegen/LLVMCPU/KernelDispatch.h
index afb616e..f462682 100644
--- a/iree/compiler/Codegen/LLVMCPU/KernelDispatch.h
+++ b/iree/compiler/Codegen/LLVMCPU/KernelDispatch.h
@@ -23,6 +23,16 @@
NumTileLevels = 3
};
+enum class StrategyTilingLevel : unsigned {
+ // Tile linalg operations to threads.
+ WorkGroupTiles = 0,
+ // Tile linalg operation on workgroup thread for parallel dims.
+ ParallelTiles = 1,
+ // Tile linalg operations on workgroup thread for reduction dims.
+ ReductionTiles = 2,
+ NumStrategyTileLevels = 3
+};
+
LogicalResult initCPULaunchConfig(ModuleOp moduleOp);
} // namespace iree_compiler
diff --git a/iree/compiler/Codegen/LLVMCPU/Passes.cpp b/iree/compiler/Codegen/LLVMCPU/Passes.cpp
index b039615..d6c2e1e 100644
--- a/iree/compiler/Codegen/LLVMCPU/Passes.cpp
+++ b/iree/compiler/Codegen/LLVMCPU/Passes.cpp
@@ -120,7 +120,7 @@
}
SmallVector<int64_t> secondLevelTileSizes = loweringConfig.getTileSizeVals(
- static_cast<unsigned>(TilingLevel::L1Tiles));
+ static_cast<unsigned>(StrategyTilingLevel::ParallelTiles));
for (auto en : llvm::enumerate(secondLevelTileSizes)) {
if (en.value() != 0 && !pLoopsSet.contains(en.index())) {
return op->emitOpError(
@@ -131,7 +131,7 @@
}
SmallVector<int64_t> thirdLevelTileSizes = loweringConfig.getTileSizeVals(
- static_cast<unsigned>(TilingLevel::VectorTiles));
+ static_cast<unsigned>(StrategyTilingLevel::ReductionTiles));
for (auto en : llvm::enumerate(thirdLevelTileSizes)) {
if (en.value() != 0 && pLoopsSet.contains(en.index())) {
return op->emitOpError(
@@ -142,17 +142,11 @@
}
}
- // Verify that native vector size is either empty, or if set is same as the
- // last level of tiling
+ // Verify that native vector size is empty.
SmallVector<int64_t> nativeVectorSize =
loweringConfig.getNativeVectorSizeVals();
if (!nativeVectorSize.empty()) {
- if (nativeVectorSize !=
- loweringConfig.getTileSizeVals(
- static_cast<unsigned>(TilingLevel::VectorTiles))) {
- return op->emitOpError(
- "native_vector_size must be same as the last level of tiling");
- }
+ return op->emitOpError("native_vector_size must be empty");
}
return success();
}
@@ -229,7 +223,8 @@
// along reduction dim again, which needs them to be Linalg ops form.
{
LinalgFusePassOptions options;
- options.tilingLevel = static_cast<int64_t>(TilingLevel::L1Tiles);
+ options.tilingLevel =
+ static_cast<int64_t>(StrategyTilingLevel::ParallelTiles);
passManager.addNestedPass<FuncOp>(createLinalgFusePass(options));
passManager.addNestedPass<FuncOp>(createCanonicalizerPass());
passManager.addNestedPass<FuncOp>(createCSEPass());
@@ -248,7 +243,8 @@
// bufferization for some cases.
// options.pad = true;
// options.packPaddings = {1, 1, 0};
- options.tilingLevel = static_cast<int64_t>(TilingLevel::VectorTiles);
+ options.tilingLevel =
+ static_cast<int64_t>(StrategyTilingLevel::ReductionTiles);
passManager.addNestedPass<FuncOp>(
createLinalgSingleTilingExpertPass(options));
passManager.addNestedPass<FuncOp>(createCanonicalizerPass());
@@ -293,7 +289,8 @@
// along reduction dim again, which needs them to be Linalg ops form.
{
LinalgFusePassOptions options;
- options.tilingLevel = static_cast<int64_t>(TilingLevel::L1Tiles);
+ options.tilingLevel =
+ static_cast<int64_t>(StrategyTilingLevel::ParallelTiles);
passManager.addNestedPass<FuncOp>(createLinalgFusePass(options));
passManager.addNestedPass<FuncOp>(createCanonicalizerPass());
passManager.addNestedPass<FuncOp>(createCSEPass());
@@ -305,7 +302,8 @@
options.decomposeToLowerDimOp = true;
options.vectorize = true;
options.vectorizePadding = true;
- options.tilingLevel = static_cast<int64_t>(TilingLevel::VectorTiles);
+ options.tilingLevel =
+ static_cast<int64_t>(StrategyTilingLevel::ReductionTiles);
passManager.addNestedPass<FuncOp>(
createLinalgSingleTilingExpertPass(options));
passManager.addNestedPass<FuncOp>(createCanonicalizerPass());
diff --git a/iree/compiler/Codegen/LLVMCPU/test/illegal_configuration.mlir b/iree/compiler/Codegen/LLVMCPU/test/illegal_configuration.mlir
index a8ac4f8..0acba0e 100644
--- a/iree/compiler/Codegen/LLVMCPU/test/illegal_configuration.mlir
+++ b/iree/compiler/Codegen/LLVMCPU/test/illegal_configuration.mlir
@@ -51,7 +51,7 @@
%lhs = hal.interface.binding.subspan set(0) binding(0) type(storage_buffer) : memref<4x8xf32>
%rhs = hal.interface.binding.subspan set(0) binding(1) type(storage_buffer) : memref<8x16xf32>
%result = hal.interface.binding.subspan set(0) binding(2) type(storage_buffer) : memref<4x16xf32>
- // expected-error @+1 {{native_vector_size must be same as the last level of tiling}}
+ // expected-error @+1 {{native_vector_size must be empty}}
linalg.matmul {lowering_config = #config} ins(%lhs, %rhs : memref<4x8xf32>, memref<8x16xf32>)
outs(%result: memref<4x16xf32>)
return
