[Codegen][CPU] Add a type-polymorphic generic-scalar MMA fallback. (#24389)

Adds two new `MMAIntrinsic` values, `MMA_GENERIC_SCALAR_1x1x1_REG8` and
`_REG16`, that the data-tiling cost model picks when no element-type-
specific intrinsic on the target supports the matmul's (LHS, RHS, ACC)
types. This intentionally breaks the "an MMAIntrinsic enum value pins
down a specific element-type triple" invariant in exchange for not
having to add one enum value per supported triple. Element types live on
new `DataTiledMMAAttr.{lhs,rhs,acc}_type` parameters, populated by the
cost model only when the chosen intrinsic is one of the polymorphic
variants.

The cost model picks `_REG16` on 64-bit ISAs (x86_64, AArch64, RISC-V)
and `_REG8` on 32-bit ISAs. The number is a register-budget for the
unroll heuristic — one element of any width occupies one register, but
the architectural register file the lowering ends up in (GPR or SIMD-
scalar lane) is up to LLVM. The budget is encoded in the low byte of the
enum value, so `chooseUnrolling` can read it back.

Since the intrinsic is 1×1×1, the operand tiles after `intrinsics_m` /
`intrinsics_n` / `intrinsics_k` are simple row-major (M, K) / (N, K) /
(M, N) — `linalg.mmt4d`-shaped.
`DataTiledMMAAttr::buildUnderlyingOperations` therefore short-circuits
the swizzle/distribute pipeline for these intrinsics and emits a single
`vector.contract` directly, with `arith.extf` / `arith.extsi` widening
narrow LHS/RHS to ACC's element type. For sub-byte LHS/RHS types
`chooseUnrolling` also picks the smallest power-of-two `intrinsics_k`
such that K*lhsBits and K*rhsBits are byte-aligned (e.g. K=2 for i4/f4,
K=4 for f6, K=8 for i1).

Progress towards #24323