)]}'
{
  "commit": "c4da71ca6bf0ea7d45fe1453e76bd20a17ea26dd",
  "tree": "d7dc2e69c266d5f18a00a85811effbbc6f2660eb",
  "parents": [
    "fac9d3d9d9b1ea55757c3ae94e9b03ff50b6d4f0"
  ],
  "author": {
    "name": "Benoit Jacob",
    "email": "jacob.benoit.1@gmail.com",
    "time": "Thu May 07 16:28:45 2026 -0400"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu May 07 20:28:45 2026 +0000"
  },
  "message": "[Codegen][CPU] Add a type-polymorphic generic-scalar MMA fallback. (#24389)\n\nAdds two new `MMAIntrinsic` values, `MMA_GENERIC_SCALAR_1x1x1_REG8` and\n`_REG16`, that the data-tiling cost model picks when no element-type-\nspecific intrinsic on the target supports the matmul\u0027s (LHS, RHS, ACC)\ntypes. This intentionally breaks the \"an MMAIntrinsic enum value pins\ndown a specific element-type triple\" invariant in exchange for not\nhaving to add one enum value per supported triple. Element types live on\nnew `DataTiledMMAAttr.{lhs,rhs,acc}_type` parameters, populated by the\ncost model only when the chosen intrinsic is one of the polymorphic\nvariants.\n\nThe cost model picks `_REG16` on 64-bit ISAs (x86_64, AArch64, RISC-V)\nand `_REG8` on 32-bit ISAs. The number is a register-budget for the\nunroll heuristic — one element of any width occupies one register, but\nthe architectural register file the lowering ends up in (GPR or SIMD-\nscalar lane) is up to LLVM. The budget is encoded in the low byte of the\nenum value, so `chooseUnrolling` can read it back.\n\nSince the intrinsic is 1×1×1, the operand tiles after `intrinsics_m` /\n`intrinsics_n` / `intrinsics_k` are simple row-major (M, K) / (N, K) /\n(M, N) — `linalg.mmt4d`-shaped.\n`DataTiledMMAAttr::buildUnderlyingOperations` therefore short-circuits\nthe swizzle/distribute pipeline for these intrinsics and emits a single\n`vector.contract` directly, with `arith.extf` / `arith.extsi` widening\nnarrow LHS/RHS to ACC\u0027s element type. For sub-byte LHS/RHS types\n`chooseUnrolling` also picks the smallest power-of-two `intrinsics_k`\nsuch that K*lhsBits and K*rhsBits are byte-aligned (e.g. K\u003d2 for i4/f4,\nK\u003d4 for f6, K\u003d8 for i1).\n\nProgress towards #24323",
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