Integrate LLVM to llvm/llvm-project@d98828d394e4 (#24832)
Bumps the llvm-project submodule from llvm/llvm-project@d37fa5a838db to
llvm/llvm-project@d98828d394e4.
This is based on llvm/llvm-project@bd9990e127e1 with a temporary revert
of llvm/llvm-project@202ece62657c due to a regression in MLIR SPIR-V
conversion where i16 StorageBuffer accesses can fail legalization when
narrow-integer emulation is required. Follow-up investigation/upstream
fix required.
Adaptations needed:
- llvm/llvm-project@7e0416da49f4 removed `TargetOptions::FloatABIType`
in favor of the `float-abi` LLVM IR module flag. Store the float ABI on
IREE's `LLVMTarget` instead and set the module flag on generated
executables in the LLVMCPU target backend, preserving the previous
hard-float default.
- Updated lit tests for MLIR assembly-format changes that moved inherent
attributes out of the attr-dict into declarative syntax.
- Regenerated CAPI export files.
Assisted-by: Claude Code
Signed-off-by: Pooja Hemashekar <hemashekar@roofline.ai>
diff --git a/compiler/plugins/target/LLVMCPU/LLVMCPUTarget.cpp b/compiler/plugins/target/LLVMCPU/LLVMCPUTarget.cpp
index 9a8ec2e..b0b9f19 100644
--- a/compiler/plugins/target/LLVMCPU/LLVMCPUTarget.cpp
+++ b/compiler/plugins/target/LLVMCPU/LLVMCPUTarget.cpp
@@ -531,6 +531,15 @@
// Specialize the module to our target machine.
llvmModule->setDataLayout(targetMachine->createDataLayout());
llvmModule->setTargetTriple(targetMachine->getTargetTriple());
+ // An explicit "float-abi" module flag wins; only record the target's ABI
+ // when the module does not already carry one.
+ if (target.floatABI != llvm::FloatABI::Default &&
+ !llvmModule->getModuleFlag("float-abi")) {
+ llvmModule->addModuleFlag(
+ llvm::Module::Error, "float-abi",
+ llvm::MDString::get(llvmModule->getContext(),
+ llvm::FloatABI::getABITypeName(target.floatABI)));
+ }
// Dump just the codegen bitcode before linking and optimization.
if (!options.dumpIntermediatesPath.empty()) {
diff --git a/compiler/plugins/target/LLVMCPU/LLVMTargetOptions.cpp b/compiler/plugins/target/LLVMCPU/LLVMTargetOptions.cpp
index c58cb4e..289ae03 100644
--- a/compiler/plugins/target/LLVMCPU/LLVMTargetOptions.cpp
+++ b/compiler/plugins/target/LLVMCPU/LLVMTargetOptions.cpp
@@ -37,7 +37,7 @@
// TODO(benvanik): add an option for this.
optimizerOptLevel = llvm::OptimizationLevel::O2;
codeGenOptLevel = llvm::CodeGenOptLevel::Aggressive;
- llvmTargetOptions.FloatABIType = DEFAULT_FLOAT_ABI;
+ floatABI = DEFAULT_FLOAT_ABI;
// Force `-ffunction-sections` so we can strip unused code.
llvmTargetOptions.FunctionSections = true;
@@ -111,8 +111,7 @@
<< " SLPVectorization=" << pipelineTuningOptions.SLPVectorization
<< "\n"
<< " }, llvmTargetOptions={\n"
- << " FloatABIType=" << static_cast<int>(llvmTargetOptions.FloatABIType)
- << "\n"
+ << " FloatABI=" << static_cast<int>(floatABI) << "\n"
<< " }\n"
<< " ukernels=" << ukernels << "\n"
<< " linkUkernelBitcode=" << linkUkernelBitcode << "\n"
@@ -180,8 +179,8 @@
if (!llvmTargetOptions.MCOptions.ABIName.empty()) {
addString("target_abi", llvmTargetOptions.MCOptions.ABIName);
}
- if (llvmTargetOptions.FloatABIType != DEFAULT_FLOAT_ABI) {
- switch (llvmTargetOptions.FloatABIType) {
+ if (floatABI != DEFAULT_FLOAT_ABI) {
+ switch (floatABI) {
case llvm::FloatABI::Default:
addString("float_abi", "default");
break;
@@ -318,11 +317,11 @@
auto floatAbi = getOptionalString("float_abi");
if (floatAbi) {
if (floatAbi == "default") {
- target.llvmTargetOptions.FloatABIType = llvm::FloatABI::Default;
+ target.floatABI = llvm::FloatABI::Default;
} else if (floatAbi == "soft") {
- target.llvmTargetOptions.FloatABIType = llvm::FloatABI::Default;
+ target.floatABI = llvm::FloatABI::Default;
} else if (floatAbi == "hard") {
- target.llvmTargetOptions.FloatABIType = llvm::FloatABI::Default;
+ target.floatABI = llvm::FloatABI::Default;
} else {
emitError(loc) << "executable config unexpected value for 'float_abi'";
return {};
@@ -670,7 +669,7 @@
target.pipelineTuningOptions.SLPVectorization = llvmSLPVectorization;
target.sanitizerKind = sanitizerKind;
target.llvmTargetOptions.MCOptions.ABIName = targetABI;
- target.llvmTargetOptions.FloatABIType = targetFloatABI;
+ target.floatABI = targetFloatABI;
target.dataLayout = targetDataLayout;
target.vectorWidthInBytes = targetVectorWidthInBytes;
target.maxStackAllocSizeInBytes = targetMaxStackAllocSizeInBytes.value;
diff --git a/compiler/plugins/target/LLVMCPU/LLVMTargetOptions.h b/compiler/plugins/target/LLVMCPU/LLVMTargetOptions.h
index cb39c88..d40b82c 100644
--- a/compiler/plugins/target/LLVMCPU/LLVMTargetOptions.h
+++ b/compiler/plugins/target/LLVMCPU/LLVMTargetOptions.h
@@ -105,6 +105,9 @@
// Optimization level to be used by the LLVM code generator (back-end).
llvm::CodeGenOptLevel codeGenOptLevel;
llvm::TargetOptions llvmTargetOptions;
+ // Floating-point ABI to use, recorded on generated LLVM modules via the
+ // "float-abi" module flag (Default defers to the target triple).
+ llvm::FloatABI::ABIType floatABI = DEFAULT_FLOAT_ABI;
bool getLinkEmbedded() const { return linkEmbedded; }
diff --git a/compiler/plugins/target/ROCM/builtins/mlir_ukernel/iree_uk_amdgpu_dt_matmul_f8E4M3FNUZ.mlir b/compiler/plugins/target/ROCM/builtins/mlir_ukernel/iree_uk_amdgpu_dt_matmul_f8E4M3FNUZ.mlir
index 1225b8a..83aae08 100644
--- a/compiler/plugins/target/ROCM/builtins/mlir_ukernel/iree_uk_amdgpu_dt_matmul_f8E4M3FNUZ.mlir
+++ b/compiler/plugins/target/ROCM/builtins/mlir_ukernel/iree_uk_amdgpu_dt_matmul_f8E4M3FNUZ.mlir
@@ -380,8 +380,8 @@
%3 = scf.for %i = %c1 to %nDim step %c1 iter_args(%iter = %2) -> vector<8x2x1x4xf32> {
// Local loads of lhs.
%lhs_vec = vector.transfer_read %lhs_shared[%c0, %ids#0, %ids#2, %c0], %cst {in_bounds = [true, true, true, true]} : !m_lhs_shared_ty, vector<2x8x1x16xf8E4M3FNUZ>
- %lhs_vec_0 = vector.extract_strided_slice %lhs_vec {offsets = [0, 0, 0, 0], sizes = [1, 8, 1, 16], strides = [1, 1, 1, 1]} : vector<2x8x1x16xf8E4M3FNUZ> to vector<1x8x1x16xf8E4M3FNUZ>
- %lhs_vec_2 = vector.extract_strided_slice %lhs_vec {offsets = [1, 0, 0, 0], sizes = [1, 8, 1, 16], strides = [1, 1, 1, 1]} : vector<2x8x1x16xf8E4M3FNUZ> to vector<1x8x1x16xf8E4M3FNUZ>
+ %lhs_vec_0 = vector.extract_strided_slice %lhs_vec offsets = [0, 0, 0, 0], sizes = [1, 8, 1, 16], strides = [1, 1, 1, 1] : vector<2x8x1x16xf8E4M3FNUZ> to vector<1x8x1x16xf8E4M3FNUZ>
+ %lhs_vec_2 = vector.extract_strided_slice %lhs_vec offsets = [1, 0, 0, 0], sizes = [1, 8, 1, 16], strides = [1, 1, 1, 1] : vector<2x8x1x16xf8E4M3FNUZ> to vector<1x8x1x16xf8E4M3FNUZ>
%lhs_vec_0_t = vector.shape_cast %lhs_vec_0 : vector<1x8x1x16xf8E4M3FNUZ> to vector<8x2x1x8xf8E4M3FNUZ>
%lhs_vec_2_t = vector.shape_cast %lhs_vec_2 : vector<1x8x1x16xf8E4M3FNUZ> to vector<8x2x1x8xf8E4M3FNUZ>
@@ -397,8 +397,8 @@
// Local loads of rhs.
%rhs_vec = vector.transfer_read %rhs_shared[%c0, %glb0_rhs, %ids#2, %c0], %cst {in_bounds = [true, true, true, true]} : !m_rhs_shared_ty, vector<2x2x1x16xf8E4M3FNUZ>
- %rhs_vec_0 = vector.extract_strided_slice %rhs_vec {offsets = [0, 0, 0, 0], sizes = [1, 2, 1, 16], strides = [1, 1, 1, 1]} : vector<2x2x1x16xf8E4M3FNUZ> to vector<1x2x1x16xf8E4M3FNUZ>
- %rhs_vec_2 = vector.extract_strided_slice %rhs_vec {offsets = [1, 0, 0, 0], sizes = [1, 2, 1, 16], strides = [1, 1, 1, 1]} : vector<2x2x1x16xf8E4M3FNUZ> to vector<1x2x1x16xf8E4M3FNUZ>
+ %rhs_vec_0 = vector.extract_strided_slice %rhs_vec offsets = [0, 0, 0, 0], sizes = [1, 2, 1, 16], strides = [1, 1, 1, 1] : vector<2x2x1x16xf8E4M3FNUZ> to vector<1x2x1x16xf8E4M3FNUZ>
+ %rhs_vec_2 = vector.extract_strided_slice %rhs_vec offsets = [1, 0, 0, 0], sizes = [1, 2, 1, 16], strides = [1, 1, 1, 1] : vector<2x2x1x16xf8E4M3FNUZ> to vector<1x2x1x16xf8E4M3FNUZ>
%rhs_vec_0_t = vector.shape_cast %rhs_vec_0 : vector<1x2x1x16xf8E4M3FNUZ> to vector<2x2x1x8xf8E4M3FNUZ>
%rhs_vec_2_t = vector.shape_cast %rhs_vec_2 : vector<1x2x1x16xf8E4M3FNUZ> to vector<2x2x1x8xf8E4M3FNUZ>
@@ -461,14 +461,14 @@
// Epilogue
%lhs_vec = vector.transfer_read %lhs_shared[%c0, %ids#0, %ids#2, %c0], %cst {in_bounds = [true, true, true, true]} : !m_lhs_shared_ty, vector<2x8x1x16xf8E4M3FNUZ>
- %lhs_vec_0 = vector.extract_strided_slice %lhs_vec {offsets = [0, 0, 0, 0], sizes = [1, 8, 1, 16], strides = [1, 1, 1, 1]} : vector<2x8x1x16xf8E4M3FNUZ> to vector<1x8x1x16xf8E4M3FNUZ>
- %lhs_vec_2 = vector.extract_strided_slice %lhs_vec {offsets = [1, 0, 0, 0], sizes = [1, 8, 1, 16], strides = [1, 1, 1, 1]} : vector<2x8x1x16xf8E4M3FNUZ> to vector<1x8x1x16xf8E4M3FNUZ>
+ %lhs_vec_0 = vector.extract_strided_slice %lhs_vec offsets = [0, 0, 0, 0], sizes = [1, 8, 1, 16], strides = [1, 1, 1, 1] : vector<2x8x1x16xf8E4M3FNUZ> to vector<1x8x1x16xf8E4M3FNUZ>
+ %lhs_vec_2 = vector.extract_strided_slice %lhs_vec offsets = [1, 0, 0, 0], sizes = [1, 8, 1, 16], strides = [1, 1, 1, 1] : vector<2x8x1x16xf8E4M3FNUZ> to vector<1x8x1x16xf8E4M3FNUZ>
%lhs_vec_0_t = vector.shape_cast %lhs_vec_0 : vector<1x8x1x16xf8E4M3FNUZ> to vector<8x2x1x8xf8E4M3FNUZ>
%lhs_vec_2_t = vector.shape_cast %lhs_vec_2 : vector<1x8x1x16xf8E4M3FNUZ> to vector<8x2x1x8xf8E4M3FNUZ>
%rhs_vec = vector.transfer_read %rhs_shared[%c0, %glb0_rhs, %ids#2, %c0], %cst {in_bounds = [true, true, true, true]} : !m_rhs_shared_ty, vector<2x2x1x16xf8E4M3FNUZ>
- %rhs_vec_0 = vector.extract_strided_slice %rhs_vec {offsets = [0, 0, 0, 0], sizes = [1, 2, 1, 16], strides = [1, 1, 1, 1]} : vector<2x2x1x16xf8E4M3FNUZ> to vector<1x2x1x16xf8E4M3FNUZ>
- %rhs_vec_2 = vector.extract_strided_slice %rhs_vec {offsets = [1, 0, 0, 0], sizes = [1, 2, 1, 16], strides = [1, 1, 1, 1]} : vector<2x2x1x16xf8E4M3FNUZ> to vector<1x2x1x16xf8E4M3FNUZ>
+ %rhs_vec_0 = vector.extract_strided_slice %rhs_vec offsets = [0, 0, 0, 0], sizes = [1, 2, 1, 16], strides = [1, 1, 1, 1] : vector<2x2x1x16xf8E4M3FNUZ> to vector<1x2x1x16xf8E4M3FNUZ>
+ %rhs_vec_2 = vector.extract_strided_slice %rhs_vec offsets = [1, 0, 0, 0], sizes = [1, 2, 1, 16], strides = [1, 1, 1, 1] : vector<2x2x1x16xf8E4M3FNUZ> to vector<1x2x1x16xf8E4M3FNUZ>
%rhs_vec_0_t = vector.shape_cast %rhs_vec_0 : vector<1x2x1x16xf8E4M3FNUZ> to vector<2x2x1x8xf8E4M3FNUZ>
%rhs_vec_2_t = vector.shape_cast %rhs_vec_2 : vector<1x2x1x16xf8E4M3FNUZ> to vector<2x2x1x8xf8E4M3FNUZ>
diff --git a/compiler/plugins/target/ROCM/builtins/mlir_ukernel/iree_uk_amdgpu_dt_scaled_matmul_f4E2M1FN.mlir b/compiler/plugins/target/ROCM/builtins/mlir_ukernel/iree_uk_amdgpu_dt_scaled_matmul_f4E2M1FN.mlir
index da42889..c573678 100644
--- a/compiler/plugins/target/ROCM/builtins/mlir_ukernel/iree_uk_amdgpu_dt_scaled_matmul_f4E2M1FN.mlir
+++ b/compiler/plugins/target/ROCM/builtins/mlir_ukernel/iree_uk_amdgpu_dt_scaled_matmul_f4E2M1FN.mlir
@@ -137,11 +137,11 @@
%lhs_scale_byte = iree_tensor_ext.bitcast %lhs_scale_base : !lhs_scale_ty{%k} -> !lhs_scale_byte_ty{%k}
%rhs_scale_byte = iree_tensor_ext.bitcast %rhs_scale_base : !rhs_scale_ty{%k} -> !rhs_scale_byte_ty{%k}
- %lhs = bufferization.to_buffer %lhs_byte {read_only} : !lhs_byte_ty to !lhs_buffer_ty
- %rhs = bufferization.to_buffer %rhs_byte {read_only} : !rhs_byte_ty to !rhs_buffer_ty
+ %lhs = bufferization.to_buffer %lhs_byte read_only : !lhs_byte_ty to !lhs_buffer_ty
+ %rhs = bufferization.to_buffer %rhs_byte read_only : !rhs_byte_ty to !rhs_buffer_ty
- %lhs_scale = bufferization.to_buffer %lhs_scale_byte {read_only} : !lhs_scale_byte_ty to !lhs_scale_buffer_ty
- %rhs_scale = bufferization.to_buffer %rhs_scale_byte {read_only} : !rhs_scale_byte_ty to !rhs_scale_buffer_ty
+ %lhs_scale = bufferization.to_buffer %lhs_scale_byte read_only : !lhs_scale_byte_ty to !lhs_scale_buffer_ty
+ %rhs_scale = bufferization.to_buffer %rhs_scale_byte read_only : !rhs_scale_byte_ty to !rhs_scale_buffer_ty
// Collapse shapes to reduce memory indexing overhead.
%lhs_collapse = memref.collapse_shape %lhs [[0, 1], [2, 3, 4, 5, 6, 7, 8]] : !lhs_buffer_ty into !lhs_buffer_collapse_ty
diff --git a/compiler/plugins/target/ROCM/builtins/mlir_ukernel/ukernel_patterns_gfx942.mlir b/compiler/plugins/target/ROCM/builtins/mlir_ukernel/ukernel_patterns_gfx942.mlir
index d34db59..6097cae 100644
--- a/compiler/plugins/target/ROCM/builtins/mlir_ukernel/ukernel_patterns_gfx942.mlir
+++ b/compiler/plugins/target/ROCM/builtins/mlir_ukernel/ukernel_patterns_gfx942.mlir
@@ -34,7 +34,7 @@
: !pdl.operation, !pdl.attribute, !pdl.attribute)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
// M % 128 == 0, K % 128 == 0, N % 256 == 0
%empty = pdl.attribute = {}
@@ -119,7 +119,7 @@
: !pdl.operation, !pdl.attribute, !pdl.attribute)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
// M % 256 == 0, K % 128 == 0, N % 256 == 0
%empty = pdl.attribute = {}
@@ -211,7 +211,7 @@
: !pdl.operation, !pdl.attribute, !pdl.attribute)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
// M % 256 == 0, K % 64 == 0, N % 256 == 0
%empty = pdl.attribute = {}
@@ -293,7 +293,7 @@
: !pdl.operation, !pdl.attribute, !pdl.attribute)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
// M % 128 == 0, K % 64 == 0, N % 256 == 0
%empty = pdl.attribute = {}
@@ -382,7 +382,7 @@
: !pdl.operation, !pdl.attribute, !pdl.attribute)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
// M % 256 == 0, K % 64 == 0, N % 256 == 0
%empty = pdl.attribute = {}
@@ -471,7 +471,7 @@
: !pdl.operation, !pdl.attribute, !pdl.attribute)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
// M % 256 == 0, K % 64 == 0, N % 256 == 0
%empty = pdl.attribute = {}
@@ -553,7 +553,7 @@
: !pdl.operation, !pdl.attribute, !pdl.attribute)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
// M % 128 == 0, K % 64 == 0, N % 256 == 0
%empty = pdl.attribute = {}
@@ -646,7 +646,7 @@
: !pdl.operation, !pdl.attribute, !pdl.attribute)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
// M % 256 == 0, K % 64 == 0, N % 256 == 0
%empty = pdl.attribute = {}
@@ -708,7 +708,7 @@
%generic_op = pdl.operation "iree_codegen.inner_tiled" (%lhs, %rhs, %out_init : !pdl.value, !pdl.value, !pdl.value) -> (%out_type : !pdl.type)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
%lhs_cast_type = pdl.type : tensor<?x?x8x4x16x2x8xf8E4M3FNUZ>
pdl.apply_native_constraint "matchCastCompatibleType"(%lhs, %lhs_cast_type : !pdl.value, !pdl.type)
@@ -765,7 +765,7 @@
%generic_op = pdl.operation "iree_codegen.inner_tiled" (%lhs, %rhs, %out_init : !pdl.value, !pdl.value, !pdl.value) -> (%out_type : !pdl.type)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
%lhs_cast_type = pdl.type : tensor<?x?x2x8x4x16x8xf8E4M3FNUZ>
pdl.apply_native_constraint "matchCastCompatibleType"(%lhs, %lhs_cast_type : !pdl.value, !pdl.type)
@@ -822,7 +822,7 @@
%generic_op = pdl.operation "iree_codegen.inner_tiled" (%lhs, %rhs, %out_init : !pdl.value, !pdl.value, !pdl.value) -> (%out_type : !pdl.type)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
%lhs_cast_type = pdl.type : tensor<?x?x2x8x4x16x4xf16>
pdl.apply_native_constraint "matchCastCompatibleType"(%lhs, %lhs_cast_type : !pdl.value, !pdl.type)
diff --git a/compiler/plugins/target/ROCM/builtins/mlir_ukernel/ukernel_patterns_gfx950.mlir b/compiler/plugins/target/ROCM/builtins/mlir_ukernel/ukernel_patterns_gfx950.mlir
index d6717e9..a267995 100644
--- a/compiler/plugins/target/ROCM/builtins/mlir_ukernel/ukernel_patterns_gfx950.mlir
+++ b/compiler/plugins/target/ROCM/builtins/mlir_ukernel/ukernel_patterns_gfx950.mlir
@@ -34,7 +34,7 @@
: !pdl.operation, !pdl.attribute, !pdl.attribute)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
// M % 128 == 0, K % 128 == 0, N % 256 == 0
%empty = pdl.attribute = {}
@@ -119,7 +119,7 @@
: !pdl.operation, !pdl.attribute, !pdl.attribute)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
// M % 256 == 0, K % 128 == 0, N % 256 == 0
%empty = pdl.attribute = {}
@@ -211,7 +211,7 @@
: !pdl.operation, !pdl.attribute, !pdl.attribute)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
// M % 256 == 0, K % 64 == 0, N % 256 == 0
%empty = pdl.attribute = {}
@@ -293,7 +293,7 @@
: !pdl.operation, !pdl.attribute, !pdl.attribute)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
// M % 128 == 0, K % 64 == 0, N % 256 == 0
%empty = pdl.attribute = {}
@@ -384,7 +384,7 @@
: !pdl.operation, !pdl.attribute, !pdl.attribute)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
// M % 256 == 0, K % 64 == 0, N % 256 == 0
%empty = pdl.attribute = {}
@@ -473,7 +473,7 @@
: !pdl.operation, !pdl.attribute, !pdl.attribute)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
// M % 256 == 0, K % 64 == 0, N % 256 == 0
%empty = pdl.attribute = {}
@@ -555,7 +555,7 @@
: !pdl.operation, !pdl.attribute, !pdl.attribute)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
// M % 128 == 0, K % 64 == 0, N % 256 == 0
%empty = pdl.attribute = {}
@@ -648,7 +648,7 @@
: !pdl.operation, !pdl.attribute, !pdl.attribute)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
// M % 256 == 0, K % 64 == 0, N % 256 == 0
%empty = pdl.attribute = {}
@@ -714,7 +714,7 @@
%inner_tiled_op = pdl.operation "iree_codegen.inner_tiled" (%lhs, %rhs, %lhs_scale, %rhs_scale, %out_init : !pdl.value, !pdl.value, !pdl.value, !pdl.value, !pdl.value) -> (%out_type : !pdl.type)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%inner_tiled_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%inner_tiled_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
%lhs_cast_type = pdl.type : tensor<?x?x1x2x4x2x4x16x32xf4E2M1FN>
pdl.apply_native_constraint "matchCastCompatibleType"(%lhs, %lhs_cast_type : !pdl.value, !pdl.type)
@@ -779,7 +779,7 @@
%generic_op = pdl.operation "iree_codegen.inner_tiled" (%lhs, %rhs, %out_init : !pdl.value, !pdl.value, !pdl.value) -> (%out_type : !pdl.type)
%attr_name = pdl.attribute = "iree_codegen.ukernel"
- pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) {isNegated = true}
+ pdl.apply_native_constraint "hasAttr"(%generic_op, %attr_name : !pdl.operation, !pdl.attribute) is_negated = true
%lhs_cast_type = pdl.type : tensor<?x?x2x8x4x16x8xf8E4M3FN>
pdl.apply_native_constraint "matchCastCompatibleType"(%lhs, %lhs_cast_type : !pdl.value, !pdl.type)
diff --git a/compiler/plugins/target/ROCM/builtins/specialization/specialization_patterns_gfx942.mlir b/compiler/plugins/target/ROCM/builtins/specialization/specialization_patterns_gfx942.mlir
index 893c73b..978ea0b 100644
--- a/compiler/plugins/target/ROCM/builtins/specialization/specialization_patterns_gfx942.mlir
+++ b/compiler/plugins/target/ROCM/builtins/specialization/specialization_patterns_gfx942.mlir
@@ -20,7 +20,7 @@
%attr_name = pdl.attribute = "iree_codegen.specialization_ranges"
pdl.apply_native_constraint "hasAttr"(
%matmul, %attr_name
- : !pdl.operation, !pdl.attribute) {isNegated = true}
+ : !pdl.operation, !pdl.attribute) is_negated = true
pdl.rewrite %matmul {
%ranges = pdl.attribute = #util<int.assumption.multi_array[
@@ -51,7 +51,7 @@
%attr_name = pdl.attribute = "iree_codegen.specialization_ranges"
pdl.apply_native_constraint "hasAttr"(
%matmul, %attr_name
- : !pdl.operation, !pdl.attribute) {isNegated = true}
+ : !pdl.operation, !pdl.attribute) is_negated = true
pdl.rewrite %matmul {
%ranges = pdl.attribute = #util<int.assumption.multi_array[
@@ -82,7 +82,7 @@
%attr_name = pdl.attribute = "iree_codegen.specialization_ranges"
pdl.apply_native_constraint "hasAttr"(
%matmul, %attr_name
- : !pdl.operation, !pdl.attribute) {isNegated = true}
+ : !pdl.operation, !pdl.attribute) is_negated = true
pdl.rewrite %matmul {
%ranges = pdl.attribute = #util<int.assumption.multi_array[
diff --git a/compiler/plugins/target/ROCM/builtins/specialization/specialization_patterns_gfx950.mlir b/compiler/plugins/target/ROCM/builtins/specialization/specialization_patterns_gfx950.mlir
index a57285f..9644e06 100644
--- a/compiler/plugins/target/ROCM/builtins/specialization/specialization_patterns_gfx950.mlir
+++ b/compiler/plugins/target/ROCM/builtins/specialization/specialization_patterns_gfx950.mlir
@@ -20,7 +20,7 @@
%attr_name = pdl.attribute = "iree_codegen.specialization_ranges"
pdl.apply_native_constraint "hasAttr"(
%matmul, %attr_name
- : !pdl.operation, !pdl.attribute) {isNegated = true}
+ : !pdl.operation, !pdl.attribute) is_negated = true
pdl.rewrite %matmul {
%ranges = pdl.attribute = #util<int.assumption.multi_array[
@@ -51,7 +51,7 @@
%attr_name = pdl.attribute = "iree_codegen.specialization_ranges"
pdl.apply_native_constraint "hasAttr"(
%matmul, %attr_name
- : !pdl.operation, !pdl.attribute) {isNegated = true}
+ : !pdl.operation, !pdl.attribute) is_negated = true
pdl.rewrite %matmul {
%ranges = pdl.attribute = #util<int.assumption.multi_array[
@@ -82,7 +82,7 @@
%attr_name = pdl.attribute = "iree_codegen.specialization_ranges"
pdl.apply_native_constraint "hasAttr"(
%matmul, %attr_name
- : !pdl.operation, !pdl.attribute) {isNegated = true}
+ : !pdl.operation, !pdl.attribute) is_negated = true
pdl.rewrite %matmul {
%ranges = pdl.attribute = #util<int.assumption.multi_array[
@@ -115,7 +115,7 @@
%attr_name = pdl.attribute = "iree_codegen.specialization_ranges"
pdl.apply_native_constraint "hasAttr"(
%scaled_matmul, %attr_name
- : !pdl.operation, !pdl.attribute) {isNegated = true}
+ : !pdl.operation, !pdl.attribute) is_negated = true
pdl.rewrite %scaled_matmul {
%ranges = pdl.attribute = #util<int.assumption.multi_array[
diff --git a/compiler/src/iree/compiler/API/api_exports.c b/compiler/src/iree/compiler/API/api_exports.c
index c92d46e..e0e31c3 100644
--- a/compiler/src/iree/compiler/API/api_exports.c
+++ b/compiler/src/iree/compiler/API/api_exports.c
@@ -314,12 +314,14 @@
extern void mlirConditionallySpeculatableOpInterfaceTypeID();
extern void mlirContextAppendDialectRegistry();
extern void mlirContextAttachDiagnosticHandler();
+extern void mlirContextBeginTransientScope();
extern void mlirContextCreate();
extern void mlirContextCreateWithRegistry();
extern void mlirContextCreateWithThreading();
extern void mlirContextDestroy();
extern void mlirContextDetachDiagnosticHandler();
extern void mlirContextEnableMultithreading();
+extern void mlirContextEndTransientScope();
extern void mlirContextEqual();
extern void mlirContextGetAllowUnregisteredDialects();
extern void mlirContextGetLoadedDialect();
@@ -328,6 +330,7 @@
extern void mlirContextGetNumThreads();
extern void mlirContextGetOrLoadDialect();
extern void mlirContextGetThreadPool();
+extern void mlirContextIsInTransientScope();
extern void mlirContextIsRegisteredOperation();
extern void mlirContextLoadAllAvailableDialects();
extern void mlirContextSetAllowUnregisteredDialects();
@@ -651,6 +654,7 @@
extern void mlirLLVMDICompileUnitAttrGetName();
extern void mlirLLVMDICompileUnitAttrGetRecSelf();
extern void mlirLLVMDICompileUnitAttrGetWithSourceLanguageDialect();
+extern void mlirLLVMDICompileUnitAttrGetWithSourceLanguageName();
extern void mlirLLVMDICompositeTypeAttrGet();
extern void mlirLLVMDICompositeTypeAttrGetName();
extern void mlirLLVMDICompositeTypeAttrGetRecSelf();
@@ -1552,12 +1556,14 @@
x += (uintptr_t)&mlirConditionallySpeculatableOpInterfaceTypeID;
x += (uintptr_t)&mlirContextAppendDialectRegistry;
x += (uintptr_t)&mlirContextAttachDiagnosticHandler;
+ x += (uintptr_t)&mlirContextBeginTransientScope;
x += (uintptr_t)&mlirContextCreate;
x += (uintptr_t)&mlirContextCreateWithRegistry;
x += (uintptr_t)&mlirContextCreateWithThreading;
x += (uintptr_t)&mlirContextDestroy;
x += (uintptr_t)&mlirContextDetachDiagnosticHandler;
x += (uintptr_t)&mlirContextEnableMultithreading;
+ x += (uintptr_t)&mlirContextEndTransientScope;
x += (uintptr_t)&mlirContextEqual;
x += (uintptr_t)&mlirContextGetAllowUnregisteredDialects;
x += (uintptr_t)&mlirContextGetLoadedDialect;
@@ -1566,6 +1572,7 @@
x += (uintptr_t)&mlirContextGetNumThreads;
x += (uintptr_t)&mlirContextGetOrLoadDialect;
x += (uintptr_t)&mlirContextGetThreadPool;
+ x += (uintptr_t)&mlirContextIsInTransientScope;
x += (uintptr_t)&mlirContextIsRegisteredOperation;
x += (uintptr_t)&mlirContextLoadAllAvailableDialects;
x += (uintptr_t)&mlirContextSetAllowUnregisteredDialects;
@@ -1889,6 +1896,7 @@
x += (uintptr_t)&mlirLLVMDICompileUnitAttrGetName;
x += (uintptr_t)&mlirLLVMDICompileUnitAttrGetRecSelf;
x += (uintptr_t)&mlirLLVMDICompileUnitAttrGetWithSourceLanguageDialect;
+ x += (uintptr_t)&mlirLLVMDICompileUnitAttrGetWithSourceLanguageName;
x += (uintptr_t)&mlirLLVMDICompositeTypeAttrGet;
x += (uintptr_t)&mlirLLVMDICompositeTypeAttrGetName;
x += (uintptr_t)&mlirLLVMDICompositeTypeAttrGetRecSelf;
diff --git a/compiler/src/iree/compiler/API/api_exports.def b/compiler/src/iree/compiler/API/api_exports.def
index 417cfcc..a4b5fe7 100644
--- a/compiler/src/iree/compiler/API/api_exports.def
+++ b/compiler/src/iree/compiler/API/api_exports.def
@@ -304,12 +304,14 @@
mlirConditionallySpeculatableOpInterfaceTypeID
mlirContextAppendDialectRegistry
mlirContextAttachDiagnosticHandler
+ mlirContextBeginTransientScope
mlirContextCreate
mlirContextCreateWithRegistry
mlirContextCreateWithThreading
mlirContextDestroy
mlirContextDetachDiagnosticHandler
mlirContextEnableMultithreading
+ mlirContextEndTransientScope
mlirContextEqual
mlirContextGetAllowUnregisteredDialects
mlirContextGetLoadedDialect
@@ -318,6 +320,7 @@
mlirContextGetNumThreads
mlirContextGetOrLoadDialect
mlirContextGetThreadPool
+ mlirContextIsInTransientScope
mlirContextIsRegisteredOperation
mlirContextLoadAllAvailableDialects
mlirContextSetAllowUnregisteredDialects
@@ -641,6 +644,7 @@
mlirLLVMDICompileUnitAttrGetName
mlirLLVMDICompileUnitAttrGetRecSelf
mlirLLVMDICompileUnitAttrGetWithSourceLanguageDialect
+ mlirLLVMDICompileUnitAttrGetWithSourceLanguageName
mlirLLVMDICompositeTypeAttrGet
mlirLLVMDICompositeTypeAttrGetName
mlirLLVMDICompositeTypeAttrGetRecSelf
diff --git a/compiler/src/iree/compiler/API/api_exports.ld b/compiler/src/iree/compiler/API/api_exports.ld
index 86643c8..bf447bd 100644
--- a/compiler/src/iree/compiler/API/api_exports.ld
+++ b/compiler/src/iree/compiler/API/api_exports.ld
@@ -305,12 +305,14 @@
mlirConditionallySpeculatableOpInterfaceTypeID;
mlirContextAppendDialectRegistry;
mlirContextAttachDiagnosticHandler;
+ mlirContextBeginTransientScope;
mlirContextCreate;
mlirContextCreateWithRegistry;
mlirContextCreateWithThreading;
mlirContextDestroy;
mlirContextDetachDiagnosticHandler;
mlirContextEnableMultithreading;
+ mlirContextEndTransientScope;
mlirContextEqual;
mlirContextGetAllowUnregisteredDialects;
mlirContextGetLoadedDialect;
@@ -319,6 +321,7 @@
mlirContextGetNumThreads;
mlirContextGetOrLoadDialect;
mlirContextGetThreadPool;
+ mlirContextIsInTransientScope;
mlirContextIsRegisteredOperation;
mlirContextLoadAllAvailableDialects;
mlirContextSetAllowUnregisteredDialects;
@@ -642,6 +645,7 @@
mlirLLVMDICompileUnitAttrGetName;
mlirLLVMDICompileUnitAttrGetRecSelf;
mlirLLVMDICompileUnitAttrGetWithSourceLanguageDialect;
+ mlirLLVMDICompileUnitAttrGetWithSourceLanguageName;
mlirLLVMDICompositeTypeAttrGet;
mlirLLVMDICompositeTypeAttrGetName;
mlirLLVMDICompositeTypeAttrGetRecSelf;
diff --git a/compiler/src/iree/compiler/API/api_exports.macos.lst b/compiler/src/iree/compiler/API/api_exports.macos.lst
index fc3d9f7..1db3db7 100644
--- a/compiler/src/iree/compiler/API/api_exports.macos.lst
+++ b/compiler/src/iree/compiler/API/api_exports.macos.lst
@@ -303,12 +303,14 @@
_mlirConditionallySpeculatableOpInterfaceTypeID
_mlirContextAppendDialectRegistry
_mlirContextAttachDiagnosticHandler
+_mlirContextBeginTransientScope
_mlirContextCreate
_mlirContextCreateWithRegistry
_mlirContextCreateWithThreading
_mlirContextDestroy
_mlirContextDetachDiagnosticHandler
_mlirContextEnableMultithreading
+_mlirContextEndTransientScope
_mlirContextEqual
_mlirContextGetAllowUnregisteredDialects
_mlirContextGetLoadedDialect
@@ -317,6 +319,7 @@
_mlirContextGetNumThreads
_mlirContextGetOrLoadDialect
_mlirContextGetThreadPool
+_mlirContextIsInTransientScope
_mlirContextIsRegisteredOperation
_mlirContextLoadAllAvailableDialects
_mlirContextSetAllowUnregisteredDialects
@@ -640,6 +643,7 @@
_mlirLLVMDICompileUnitAttrGetName
_mlirLLVMDICompileUnitAttrGetRecSelf
_mlirLLVMDICompileUnitAttrGetWithSourceLanguageDialect
+_mlirLLVMDICompileUnitAttrGetWithSourceLanguageName
_mlirLLVMDICompositeTypeAttrGet
_mlirLLVMDICompositeTypeAttrGetName
_mlirLLVMDICompositeTypeAttrGetRecSelf
diff --git a/compiler/src/iree/compiler/Codegen/Common/GPU/test/gpu_nested_layout_vector_distribution.mlir b/compiler/src/iree/compiler/Codegen/Common/GPU/test/gpu_nested_layout_vector_distribution.mlir
index d304b0a..31bc004 100644
--- a/compiler/src/iree/compiler/Codegen/Common/GPU/test/gpu_nested_layout_vector_distribution.mlir
+++ b/compiler/src/iree/compiler/Codegen/Common/GPU/test/gpu_nested_layout_vector_distribution.mlir
@@ -33,10 +33,10 @@
// CHECK: %[[YX:.+]]:3 = affine.delinearize_index %[[IDX]] into (4, 8)
// CHECK: %[[Y_SCALED:.+]] = affine.linearize_index disjoint [%[[YX]]#1, %c0] by (4, 4)
// CHECK: %[[RD00:.+]] = vector.transfer_read %arg0[%[[Y_SCALED]], %[[YX]]#2], {{.*}} : memref<32x32xf16>, vector<4x1xf16>
-// CHECK: vector.insert_strided_slice %[[RD00]], %{{.*}} {offsets = [0, 0, 0, 0, 0, 0], strides = [1, 1]} : vector<4x1xf16> into vector<1x2x1x1x4x1xf16>
+// CHECK: vector.insert_strided_slice %[[RD00]], %{{.*}} offsets = [0, 0, 0, 0, 0, 0], strides = [1, 1] : vector<4x1xf16> into vector<1x2x1x1x4x1xf16>
// CHECK: %[[X_PLUS_BATCH:.+]] = affine.linearize_index disjoint [%c1, %[[YX]]#2] by (2, 8)
// CHECK: vector.transfer_read %arg0[%[[Y_SCALED]], %[[X_PLUS_BATCH]]], %{{.*}} {in_bounds = [true, true]} : memref<32x32xf16>, vector<4x1xf16>
-// CHECK: vector.insert_strided_slice {{.*}} {offsets = [0, 1, 0, 0, 0, 0]
+// CHECK: vector.insert_strided_slice {{.*}} offsets = [0, 1, 0, 0, 0, 0]
// CHECK: iree_vector_ext.to_simd %{{.*}} : vector<1x2x1x1x4x1xf16> -> vector<16x16xf16>
// -----
@@ -121,8 +121,8 @@
// CHECK-SAME: %[[I0:.+]]: index, %[[I1:.+]]: index
// CHECK: %[[BROADCAST_READ:.+]] = vector.transfer_read %{{.*}}[%c0, %c0, %[[I0]], %[[I1]]], %{{.*}} permutation_map = #[[$MAP]]
-// CHECK: vector.insert_strided_slice %[[BROADCAST_READ]], %{{.*}} {offsets = [0, 0, 0, 0, 0, 0]
-// CHECK: vector.insert_strided_slice %[[BROADCAST_READ]], %{{.*}} {offsets = [0, 1, 0, 0, 0, 0]
+// CHECK: vector.insert_strided_slice %[[BROADCAST_READ]], %{{.*}} offsets = [0, 0, 0, 0, 0, 0]
+// CHECK: vector.insert_strided_slice %[[BROADCAST_READ]], %{{.*}} offsets = [0, 1, 0, 0, 0, 0]
// -----
diff --git a/compiler/src/iree/compiler/Codegen/Common/GPU/test/gpu_nested_layout_vector_distribution_scan.mlir b/compiler/src/iree/compiler/Codegen/Common/GPU/test/gpu_nested_layout_vector_distribution_scan.mlir
index e0227a5..6eefab0 100644
--- a/compiler/src/iree/compiler/Codegen/Common/GPU/test/gpu_nested_layout_vector_distribution_scan.mlir
+++ b/compiler/src/iree/compiler/Codegen/Common/GPU/test/gpu_nested_layout_vector_distribution_scan.mlir
@@ -18,7 +18,7 @@
// CHECK-LABEL: @scan_single_bo_inclusive
func.func @scan_single_bo_inclusive(%src: vector<16xf32>, %init: vector<f32>) -> (vector<16xf32>, vector<f32>) {
%src_l = iree_vector_ext.to_layout %src to layout(#layout_scan_1d) : vector<16xf32>
- %out:2 = vector.scan <add>, %src_l, %init {inclusive = true, reduction_dim = 0 : i64}
+ %out:2 = vector.scan <add>, %src_l, %init reduction_dim = 0, inclusive = true
: vector<16xf32>, vector<f32>
return %out#0, %out#1 : vector<16xf32>, vector<f32>
}
@@ -34,7 +34,7 @@
// CHECK-DAG: %[[ID_VEC:.*]] = arith.constant dense<0.000000e+00> : vector<1x1xf32>
// CHECK-DAG: %[[SRC_DIST:.*]] = iree_vector_ext.to_simt %{{.*}} : vector<16xf32> -> vector<1x1x4xf32>
// Local inclusive scan with identity init.
-// CHECK: %[[LOCAL_SCAN:.*]], %[[LOCAL_TOTAL:.*]] = vector.scan <add>, %[[SRC_DIST]], %[[ID_VEC]] {inclusive = true, reduction_dim = 2 : i64} : vector<1x1x4xf32>, vector<1x1xf32>
+// CHECK: %[[LOCAL_SCAN:.*]], %[[LOCAL_TOTAL:.*]] = vector.scan <add>, %[[SRC_DIST]], %[[ID_VEC]] reduction_dim = 2, inclusive = true : vector<1x1x4xf32>, vector<1x1xf32>
// Subgroup scan of localTotal.
// CHECK: %[[SCALAR_TOTAL:.*]] = vector.extract %[[LOCAL_TOTAL]][0, 0] : f32 from vector<1x1xf32>
// CHECK: %[[SUBGROUP_SCAN:.*]], %[[SUBGROUP_TOTAL:.*]] = iree_gpu.subgroup_scan(%[[SCALAR_TOTAL]], {{.*}}) cluster(size = 4)
@@ -69,7 +69,7 @@
// CHECK-LABEL: @scan_single_bo_exclusive
func.func @scan_single_bo_exclusive(%src: vector<16xf32>, %init: vector<f32>) -> (vector<16xf32>, vector<f32>) {
%src_l = iree_vector_ext.to_layout %src to layout(#layout_scan_1d_excl) : vector<16xf32>
- %out:2 = vector.scan <add>, %src_l, %init {inclusive = false, reduction_dim = 0 : i64}
+ %out:2 = vector.scan <add>, %src_l, %init reduction_dim = 0, inclusive = false
: vector<16xf32>, vector<f32>
return %out#0, %out#1 : vector<16xf32>, vector<f32>
}
@@ -85,9 +85,9 @@
// CHECK-DAG: %[[ID_VEC:.*]] = arith.constant dense<0.000000e+00> : vector<1x1xf32>
// CHECK-DAG: %[[SRC_DIST:.*]] = iree_vector_ext.to_simt %{{.*}} : vector<16xf32> -> vector<1x1x4xf32>
// Local exclusive scan with identity init.
-// CHECK: %[[LOCAL_SCAN:.*]], %[[ACC_VAL:.*]] = vector.scan <add>, %[[SRC_DIST]], %[[ID_VEC]] {inclusive = false, reduction_dim = 2 : i64}
+// CHECK: %[[LOCAL_SCAN:.*]], %[[ACC_VAL:.*]] = vector.scan <add>, %[[SRC_DIST]], %[[ID_VEC]] reduction_dim = 2, inclusive = false
// Fix up localTotal: combine accumulated_value with last source element.
-// CHECK: %[[LAST_ELEM:.*]] = vector.extract_strided_slice %[[SRC_DIST]] {offsets = [0, 0, 3], sizes = [1, 1, 1], strides = [1, 1, 1]}
+// CHECK: %[[LAST_ELEM:.*]] = vector.extract_strided_slice %[[SRC_DIST]] offsets = [0, 0, 3], sizes = [1, 1, 1], strides = [1, 1, 1]
// CHECK: %[[LAST_FLAT:.*]] = vector.shape_cast %[[LAST_ELEM]] : vector<1x1x1xf32> to vector<1x1xf32>
// CHECK: %[[LOCAL_TOTAL:.*]] = arith.addf %[[ACC_VAL]], %[[LAST_FLAT]] : vector<1x1xf32>
// Subgroup scan of fixed-up localTotal.
@@ -127,7 +127,7 @@
// CHECK-LABEL: @scan_cross_subgroup_inclusive
func.func @scan_cross_subgroup_inclusive(%src: vector<32xf32>, %init: vector<f32>) -> (vector<32xf32>, vector<f32>) {
%src_l = iree_vector_ext.to_layout %src to layout(#layout_scan_cross) : vector<32xf32>
- %out:2 = vector.scan <add>, %src_l, %init {inclusive = true, reduction_dim = 0 : i64}
+ %out:2 = vector.scan <add>, %src_l, %init reduction_dim = 0, inclusive = true
: vector<32xf32>, vector<f32>
return %out#0, %out#1 : vector<32xf32>, vector<f32>
}
@@ -143,7 +143,7 @@
// CHECK-DAG: %[[CST:.*]] = arith.constant dense<0.000000e+00> : vector<1x1xf32>
// CHECK-DAG: %[[SRC_DIST:.*]] = iree_vector_ext.to_simt %{{.*}} : vector<32xf32> -> vector<1x1x4xf32>
// Local inclusive scan with identity init.
-// CHECK: %[[LOCAL_SCAN:.*]], %[[LOCAL_TOTAL:.*]] = vector.scan <add>, %[[SRC_DIST]], %{{.*}} {inclusive = true, reduction_dim = 2 : i64}
+// CHECK: %[[LOCAL_SCAN:.*]], %[[LOCAL_TOTAL:.*]] = vector.scan <add>, %[[SRC_DIST]], %{{.*}} reduction_dim = 2, inclusive = true
// Subgroup scan of localTotal.
// CHECK: %[[SUBGROUP_SCAN:.*]], %[[SUBGROUP_TOTAL:.*]] = iree_gpu.subgroup_scan
// Apply subgroup scan carry to local result.
@@ -187,7 +187,7 @@
// CHECK-LABEL: @scan_cross_subgroup_exclusive
func.func @scan_cross_subgroup_exclusive(%src: vector<32xf32>, %init: vector<f32>) -> (vector<32xf32>, vector<f32>) {
%src_l = iree_vector_ext.to_layout %src to layout(#layout_scan_cross_excl) : vector<32xf32>
- %out:2 = vector.scan <add>, %src_l, %init {inclusive = false, reduction_dim = 0 : i64}
+ %out:2 = vector.scan <add>, %src_l, %init reduction_dim = 0, inclusive = false
: vector<32xf32>, vector<f32>
return %out#0, %out#1 : vector<32xf32>, vector<f32>
}
@@ -203,9 +203,9 @@
// CHECK-DAG: %[[CST:.*]] = arith.constant dense<0.000000e+00> : vector<1x1xf32>
// CHECK-DAG: %[[SRC_DIST:.*]] = iree_vector_ext.to_simt %{{.*}} : vector<32xf32> -> vector<1x1x4xf32>
// Local exclusive scan with identity init.
-// CHECK: %[[LOCAL_SCAN:.*]], %[[ACC_VAL:.*]] = vector.scan <add>, %[[SRC_DIST]], %[[CST]] {inclusive = false, reduction_dim = 2 : i64}
+// CHECK: %[[LOCAL_SCAN:.*]], %[[ACC_VAL:.*]] = vector.scan <add>, %[[SRC_DIST]], %[[CST]] reduction_dim = 2, inclusive = false
// Fix up localTotal: combine accumulated_value with last source element.
-// CHECK: %[[LAST_ELEM:.*]] = vector.extract_strided_slice %[[SRC_DIST]] {offsets = [0, 0, 3], sizes = [1, 1, 1], strides = [1, 1, 1]}
+// CHECK: %[[LAST_ELEM:.*]] = vector.extract_strided_slice %[[SRC_DIST]] offsets = [0, 0, 3], sizes = [1, 1, 1], strides = [1, 1, 1]
// CHECK: %[[LAST_FLAT:.*]] = vector.shape_cast %[[LAST_ELEM]] : vector<1x1x1xf32> to vector<1x1xf32>
// CHECK: %[[LOCAL_TOTAL:.*]] = arith.addf %[[ACC_VAL]], %[[LAST_FLAT]] : vector<1x1xf32>
// Subgroup scan of fixed-up localTotal.
@@ -264,7 +264,7 @@
// CHECK-LABEL: @scan_multi_bo_inclusive
func.func @scan_multi_bo_inclusive(%src: vector<32xf32>, %init: vector<f32>) -> (vector<32xf32>, vector<f32>) {
%src_l = iree_vector_ext.to_layout %src to layout(#layout_scan_multi) : vector<32xf32>
- %out:2 = vector.scan <add>, %src_l, %init {inclusive = true, reduction_dim = 0 : i64}
+ %out:2 = vector.scan <add>, %src_l, %init reduction_dim = 0, inclusive = true
: vector<32xf32>, vector<f32>
return %out#0, %out#1 : vector<32xf32>, vector<f32>
}
@@ -282,7 +282,7 @@
// First (b=0): extract srcChunk, local scan, subgroup scan.
// CHECK: %[[CHUNK0:.*]] = vector.extract %[[SRC_DIST]][0, 0] : vector<4xf32> from vector<2x1x4xf32>
// CHECK: %[[CHUNK0_RS:.*]] = vector.shape_cast %[[CHUNK0]] : vector<4xf32> to vector<1x1x4xf32>
-// CHECK: %[[SCAN0:.*]], %[[TOTAL0:.*]] = vector.scan <add>, %[[CHUNK0_RS]], %[[ID_VEC]] {inclusive = true, reduction_dim = 2 : i64} : vector<1x1x4xf32>, vector<1x1xf32>
+// CHECK: %[[SCAN0:.*]], %[[TOTAL0:.*]] = vector.scan <add>, %[[CHUNK0_RS]], %[[ID_VEC]] reduction_dim = 2, inclusive = true : vector<1x1x4xf32>, vector<1x1xf32>
// CHECK: %[[SCALAR0:.*]] = vector.extract %[[TOTAL0]][0, 0] : f32 from vector<1x1xf32>
// CHECK: %[[SG_SCAN0:.*]], %[[SG_TOTAL0:.*]] = iree_gpu.subgroup_scan(%[[SCALAR0]], {{.*}}) cluster(size = 4)
// Broadcast both subgroup scan results.
@@ -292,13 +292,13 @@
// CHECK: %[[BLOCK_INCR0:.*]] = arith.addf %[[SG_SCAN0_VEC]], %[[ID_VEC]] : vector<1x1xf32>
// CHECK: %[[BLOCK_INCR0_BCAST:.*]] = vector.broadcast %[[BLOCK_INCR0]] : vector<1x1xf32> to vector<1x1x4xf32>
// CHECK: %[[LOCAL_RESULT0:.*]] = arith.addf %[[BLOCK_INCR0_BCAST]], %[[SCAN0]] : vector<1x1x4xf32>
-// CHECK: %[[RES0:.*]] = vector.insert_strided_slice %[[LOCAL_RESULT0]], %{{.*}} {offsets = [0, 0, 0], strides = [1, 1, 1]}
+// CHECK: %[[RES0:.*]] = vector.insert_strided_slice %[[LOCAL_RESULT0]], %{{.*}} offsets = [0, 0, 0], strides = [1, 1, 1]
// Advance batchOuterRunning.
// CHECK: %[[BO_RUNNING1:.*]] = arith.addf %[[SG_TOTAL0_VEC]], %[[ID_VEC]] : vector<1x1xf32>
// Second (b=1): extract srcChunk, local scan, subgroup scan.
// CHECK: %[[CHUNK1:.*]] = vector.extract %[[SRC_DIST]][1, 0] : vector<4xf32> from vector<2x1x4xf32>
// CHECK: %[[CHUNK1_RS:.*]] = vector.shape_cast %[[CHUNK1]] : vector<4xf32> to vector<1x1x4xf32>
-// CHECK: %[[SCAN1:.*]], %[[TOTAL1:.*]] = vector.scan <add>, %[[CHUNK1_RS]], %[[ID_VEC]] {inclusive = true, reduction_dim = 2 : i64} : vector<1x1x4xf32>, vector<1x1xf32>
+// CHECK: %[[SCAN1:.*]], %[[TOTAL1:.*]] = vector.scan <add>, %[[CHUNK1_RS]], %[[ID_VEC]] reduction_dim = 2, inclusive = true : vector<1x1x4xf32>, vector<1x1xf32>
// CHECK: %[[SCALAR1:.*]] = vector.extract %[[TOTAL1]][0, 0] : f32 from vector<1x1xf32>
// CHECK: %[[SG_SCAN1:.*]], %[[SG_TOTAL1:.*]] = iree_gpu.subgroup_scan(%[[SCALAR1]], {{.*}}) cluster(size = 4)
// Broadcast both subgroup scan results.
@@ -308,7 +308,7 @@
// CHECK: %[[BLOCK_INCR1:.*]] = arith.addf %[[BO_RUNNING1]], %[[SG_SCAN1_VEC]] : vector<1x1xf32>
// CHECK: %[[BLOCK_INCR1_BCAST:.*]] = vector.broadcast %[[BLOCK_INCR1]] : vector<1x1xf32> to vector<1x1x4xf32>
// CHECK: %[[LOCAL_RESULT1:.*]] = arith.addf %[[BLOCK_INCR1_BCAST]], %[[SCAN1]] : vector<1x1x4xf32>
-// CHECK: %[[RESULT:.*]] = vector.insert_strided_slice %[[LOCAL_RESULT1]], %[[RES0]] {offsets = [1, 0, 0], strides = [1, 1, 1]}
+// CHECK: %[[RESULT:.*]] = vector.insert_strided_slice %[[LOCAL_RESULT1]], %[[RES0]] offsets = [1, 0, 0], strides = [1, 1, 1]
// Accumulated value = final batchOuterRunning.
// CHECK: %[[FINAL_BO_RUNNING:.*]] = arith.addf %[[BO_RUNNING1]], %[[SG_TOTAL1_VEC]] : vector<1x1xf32>
// CHECK: %[[ACC:.*]] = vector.shape_cast %[[FINAL_BO_RUNNING]] : vector<1x1xf32> to vector<f32>
@@ -333,7 +333,7 @@
// CHECK-LABEL: @scan_multi_bo_exclusive
func.func @scan_multi_bo_exclusive(%src: vector<32xf32>, %init: vector<f32>) -> (vector<32xf32>, vector<f32>) {
%src_l = iree_vector_ext.to_layout %src to layout(#layout_scan_multi_excl) : vector<32xf32>
- %out:2 = vector.scan <add>, %src_l, %init {inclusive = false, reduction_dim = 0 : i64}
+ %out:2 = vector.scan <add>, %src_l, %init reduction_dim = 0, inclusive = false
: vector<32xf32>, vector<f32>
return %out#0, %out#1 : vector<32xf32>, vector<f32>
}
@@ -351,9 +351,9 @@
// First (b=0): extract srcChunk, local exclusive scan.
// CHECK: %[[CHUNK0:.*]] = vector.extract %[[SRC_DIST]][0, 0] : vector<4xf32> from vector<2x1x4xf32>
// CHECK: %[[CHUNK0_RS:.*]] = vector.shape_cast %[[CHUNK0]] : vector<4xf32> to vector<1x1x4xf32>
-// CHECK: %[[SCAN0:.*]], %[[ACC0:.*]] = vector.scan <add>, %[[CHUNK0_RS]], %[[ID_VEC]] {inclusive = false, reduction_dim = 2 : i64}
+// CHECK: %[[SCAN0:.*]], %[[ACC0:.*]] = vector.scan <add>, %[[CHUNK0_RS]], %[[ID_VEC]] reduction_dim = 2, inclusive = false
// Fix up localTotal: combine accumulated_value with last source element.
-// CHECK: %[[LAST0:.*]] = vector.extract_strided_slice %[[CHUNK0_RS]] {offsets = [0, 0, 3], sizes = [1, 1, 1], strides = [1, 1, 1]}
+// CHECK: %[[LAST0:.*]] = vector.extract_strided_slice %[[CHUNK0_RS]] offsets = [0, 0, 3], sizes = [1, 1, 1], strides = [1, 1, 1]
// CHECK: %[[LAST0_FLAT:.*]] = vector.shape_cast %[[LAST0]] : vector<1x1x1xf32> to vector<1x1xf32>
// CHECK: %[[LOCAL_TOTAL0:.*]] = arith.addf %[[ACC0]], %[[LAST0_FLAT]] : vector<1x1xf32>
// Subgroup scan.
@@ -366,15 +366,15 @@
// CHECK: %[[BLOCK_INCR0:.*]] = arith.addf %[[SG_SCAN0_VEC]], %[[ID_VEC]] : vector<1x1xf32>
// CHECK: %[[BLOCK_INCR0_BCAST:.*]] = vector.broadcast %[[BLOCK_INCR0]] : vector<1x1xf32> to vector<1x1x4xf32>
// CHECK: %[[LOCAL_RESULT0:.*]] = arith.addf %[[BLOCK_INCR0_BCAST]], %[[SCAN0]] : vector<1x1x4xf32>
-// CHECK: %[[RES0:.*]] = vector.insert_strided_slice %[[LOCAL_RESULT0]], %{{.*}} {offsets = [0, 0, 0], strides = [1, 1, 1]}
+// CHECK: %[[RES0:.*]] = vector.insert_strided_slice %[[LOCAL_RESULT0]], %{{.*}} offsets = [0, 0, 0], strides = [1, 1, 1]
// Advance batchOuterRunning.
// CHECK: %[[BO_RUNNING1:.*]] = arith.addf %[[SG_TOTAL0_VEC]], %[[ID_VEC]] : vector<1x1xf32>
// Second (b=1): extract srcChunk, local exclusive scan.
// CHECK: %[[CHUNK1:.*]] = vector.extract %[[SRC_DIST]][1, 0] : vector<4xf32> from vector<2x1x4xf32>
// CHECK: %[[CHUNK1_RS:.*]] = vector.shape_cast %[[CHUNK1]] : vector<4xf32> to vector<1x1x4xf32>
-// CHECK: %[[SCAN1:.*]], %[[ACC1:.*]] = vector.scan <add>, %[[CHUNK1_RS]], %[[ID_VEC]] {inclusive = false, reduction_dim = 2 : i64}
+// CHECK: %[[SCAN1:.*]], %[[ACC1:.*]] = vector.scan <add>, %[[CHUNK1_RS]], %[[ID_VEC]] reduction_dim = 2, inclusive = false
// Fix up localTotal for second chunk.
-// CHECK: %[[LAST1:.*]] = vector.extract_strided_slice %[[CHUNK1_RS]] {offsets = [0, 0, 3], sizes = [1, 1, 1], strides = [1, 1, 1]}
+// CHECK: %[[LAST1:.*]] = vector.extract_strided_slice %[[CHUNK1_RS]] offsets = [0, 0, 3], sizes = [1, 1, 1], strides = [1, 1, 1]
// CHECK: %[[LAST1_FLAT:.*]] = vector.shape_cast %[[LAST1]] : vector<1x1x1xf32> to vector<1x1xf32>
// CHECK: %[[LOCAL_TOTAL1:.*]] = arith.addf %[[ACC1]], %[[LAST1_FLAT]] : vector<1x1xf32>
// Subgroup scan.
@@ -385,7 +385,7 @@
// CHECK: %[[BLOCK_INCR1:.*]] = arith.addf %[[BO_RUNNING1]], %[[SG_SCAN1_VEC]] : vector<1x1xf32>
// CHECK: %[[BLOCK_INCR1_BCAST:.*]] = vector.broadcast %[[BLOCK_INCR1]] : vector<1x1xf32> to vector<1x1x4xf32>
// CHECK: %[[LOCAL_RESULT1:.*]] = arith.addf %[[BLOCK_INCR1_BCAST]], %[[SCAN1]] : vector<1x1x4xf32>
-// CHECK: %[[PRE_INIT:.*]] = vector.insert_strided_slice %[[LOCAL_RESULT1]], %[[RES0]] {offsets = [1, 0, 0], strides = [1, 1, 1]}
+// CHECK: %[[PRE_INIT:.*]] = vector.insert_strided_slice %[[LOCAL_RESULT1]], %[[RES0]] offsets = [1, 0, 0], strides = [1, 1, 1]
// Application of user init.
// CHECK: %[[INIT_DIST:.*]] = iree_vector_ext.to_simt %{{.*}} : vector<f32> -> vector<f32>
// CHECK: %[[INIT_BCAST:.*]] = vector.broadcast %[[INIT_DIST]] : vector<f32> to vector<2x1x4xf32>
@@ -415,7 +415,7 @@
// CHECK-LABEL: @scan_2d_dim1_inclusive
func.func @scan_2d_dim1_inclusive(%src: vector<2x16xf32>, %init: vector<2xf32>) -> (vector<2x16xf32>, vector<2xf32>) {
%src_l = iree_vector_ext.to_layout %src to layout(#layout_scan_2d_dim1) : vector<2x16xf32>
- %out:2 = vector.scan <add>, %src_l, %init {inclusive = true, reduction_dim = 1 : i64}
+ %out:2 = vector.scan <add>, %src_l, %init reduction_dim = 1, inclusive = true
: vector<2x16xf32>, vector<2xf32>
return %out#0, %out#1 : vector<2x16xf32>, vector<2xf32>
}
@@ -430,7 +430,7 @@
// CHECK-DAG: %[[ID_VEC:.*]] = arith.constant dense<0.000000e+00> : vector<2x1x1x1x1xf32>
// CHECK-DAG: %[[SRC_DIST:.*]] = iree_vector_ext.to_simt %{{.*}} : vector<2x16xf32> -> vector<2x1x1x1x1x4xf32>
-// CHECK: %[[LOCAL_SCAN:.*]], %[[LOCAL_TOTAL:.*]] = vector.scan <add>, %[[SRC_DIST]], %[[ID_VEC]] {inclusive = true, reduction_dim = 5 : i64} : vector<2x1x1x1x1x4xf32>, vector<2x1x1x1x1xf32>
+// CHECK: %[[LOCAL_SCAN:.*]], %[[LOCAL_TOTAL:.*]] = vector.scan <add>, %[[SRC_DIST]], %[[ID_VEC]] reduction_dim = 5, inclusive = true : vector<2x1x1x1x1x4xf32>, vector<2x1x1x1x1xf32>
// CHECK: %[[SCALAR0:.*]] = vector.extract %[[LOCAL_TOTAL]][0, 0, 0, 0, 0] : f32 from vector<2x1x1x1x1xf32>
// CHECK: iree_gpu.subgroup_scan(%[[SCALAR0]], {{.*}}) cluster(size = 4)
// CHECK: %[[SCALAR1:.*]] = vector.extract %[[LOCAL_TOTAL]][1, 0, 0, 0, 0] : f32 from vector<2x1x1x1x1xf32>
@@ -456,7 +456,7 @@
// CHECK-LABEL: @scan_single_bo_exclusive_f16
func.func @scan_single_bo_exclusive_f16(%src: vector<16xf16>, %init: vector<f16>) -> (vector<16xf16>, vector<f16>) {
%src_l = iree_vector_ext.to_layout %src to layout(#layout_scan_1d_f16_excl) : vector<16xf16>
- %out:2 = vector.scan <add>, %src_l, %init {inclusive = false, reduction_dim = 0 : i64}
+ %out:2 = vector.scan <add>, %src_l, %init reduction_dim = 0, inclusive = false
: vector<16xf16>, vector<f16>
return %out#0, %out#1 : vector<16xf16>, vector<f16>
}
@@ -471,7 +471,7 @@
// CHECK-DAG: %[[ID_VEC_F16:.*]] = arith.constant dense<0.000000e+00> : vector<1x1xf16>
// CHECK-DAG: %[[SRC_DIST_F16:.*]] = iree_vector_ext.to_simt %{{.*}} : vector<16xf16> -> vector<1x1x4xf16>
-// CHECK: %[[LOCAL_SCAN_F16:.*]], %[[ACC_VAL_F16:.*]] = vector.scan <add>, %[[SRC_DIST_F16]], %[[ID_VEC_F16]] {inclusive = false, reduction_dim = 2 : i64}
+// CHECK: %[[LOCAL_SCAN_F16:.*]], %[[ACC_VAL_F16:.*]] = vector.scan <add>, %[[SRC_DIST_F16]], %[[ID_VEC_F16]] reduction_dim = 2, inclusive = false
// CHECK: arith.addf %{{.*}}, %{{.*}} : vector<1x1x4xf16>
// CHECK: %[[LAST_ACC_F16:.*]] = vector.extract %{{.*}}[0, 0, 3] : f16 from vector<1x1x4xf16>
// CHECK: %[[PACKED:.*]] = arith.bitcast %[[LAST_ACC_F16]] : f16 to i16
@@ -500,7 +500,7 @@
// CHECK-LABEL: @scan_thread_tile_1_inclusive
func.func @scan_thread_tile_1_inclusive(%src: vector<4xf32>, %init: vector<f32>) -> (vector<4xf32>, vector<f32>) {
%src_l = iree_vector_ext.to_layout %src to layout(#layout_scan_1d_thread_tile_1) : vector<4xf32>
- %out:2 = vector.scan <add>, %src_l, %init {inclusive = true, reduction_dim = 0 : i64}
+ %out:2 = vector.scan <add>, %src_l, %init reduction_dim = 0, inclusive = true
: vector<4xf32>, vector<f32>
return %out#0, %out#1 : vector<4xf32>, vector<f32>
}
@@ -515,7 +515,7 @@
// CHECK-DAG: %[[ID_VEC_T1:.*]] = arith.constant dense<0.000000e+00> : vector<1x1xf32>
// CHECK-DAG: %[[SRC_DIST_T1:.*]] = iree_vector_ext.to_simt %{{.*}} : vector<4xf32> -> vector<1x1x4xf32>
-// CHECK: %[[LOCAL_SCAN_T1:.*]], %[[LOCAL_TOTAL_T1:.*]] = vector.scan <add>, %[[SRC_DIST_T1]], %[[ID_VEC_T1]] {inclusive = true, reduction_dim = 2 : i64} : vector<1x1x4xf32>, vector<1x1xf32>
+// CHECK: %[[LOCAL_SCAN_T1:.*]], %[[LOCAL_TOTAL_T1:.*]] = vector.scan <add>, %[[SRC_DIST_T1]], %[[ID_VEC_T1]] reduction_dim = 2, inclusive = true : vector<1x1x4xf32>, vector<1x1xf32>
// CHECK-NOT: iree_gpu.subgroup_scan
// CHECK: arith.addf %[[LOCAL_SCAN_T1]], %{{.*}} : vector<1x1x4xf32>
// CHECK: %[[BO_RUNNING_T1:.*]] = arith.addf %[[LOCAL_TOTAL_T1]], %[[ID_VEC_T1]] : vector<1x1xf32>
diff --git a/compiler/src/iree/compiler/Codegen/Common/GPU/test/gpu_pipeline.mlir b/compiler/src/iree/compiler/Codegen/Common/GPU/test/gpu_pipeline.mlir
index a91a36e..b76f6b3 100644
--- a/compiler/src/iree/compiler/Codegen/Common/GPU/test/gpu_pipeline.mlir
+++ b/compiler/src/iree/compiler/Codegen/Common/GPU/test/gpu_pipeline.mlir
@@ -39,18 +39,18 @@
nvgpu.device_async_wait %21
gpu.barrier memfence [#gpu.address_space<workgroup>]
%22 = affine.apply affine_map<()[s0] -> (s0 * 16)>()[%2]
- %23 = gpu.subgroup_mma_load_matrix %4[%16, %22, %c0] {leadDimension = 40 : index} : memref<4x32x40xf16, 3> -> !gpu.mma_matrix<16x16xf16, "AOp">
- %24 = gpu.subgroup_mma_load_matrix %4[%16, %22, %c16] {leadDimension = 40 : index} : memref<4x32x40xf16, 3> -> !gpu.mma_matrix<16x16xf16, "AOp">
+ %23 = gpu.subgroup_mma_load_matrix %4[%16, %22, %c0] leadDimension 40 : memref<4x32x40xf16, 3> -> !gpu.mma_matrix<16x16xf16, "AOp">
+ %24 = gpu.subgroup_mma_load_matrix %4[%16, %22, %c16] leadDimension 40 : memref<4x32x40xf16, 3> -> !gpu.mma_matrix<16x16xf16, "AOp">
%25 = affine.apply affine_map<()[s0] -> ((s0 floordiv 32) * 16)>()[%1]
- %26 = gpu.subgroup_mma_load_matrix %5[%16, %c0, %25] {leadDimension = 40 : index} : memref<4x32x40xf16, 3> -> !gpu.mma_matrix<16x16xf16, "BOp">
- %27 = gpu.subgroup_mma_load_matrix %5[%16, %c16, %25] {leadDimension = 40 : index} : memref<4x32x40xf16, 3> -> !gpu.mma_matrix<16x16xf16, "BOp">
+ %26 = gpu.subgroup_mma_load_matrix %5[%16, %c0, %25] leadDimension 40 : memref<4x32x40xf16, 3> -> !gpu.mma_matrix<16x16xf16, "BOp">
+ %27 = gpu.subgroup_mma_load_matrix %5[%16, %c16, %25] leadDimension 40 : memref<4x32x40xf16, 3> -> !gpu.mma_matrix<16x16xf16, "BOp">
%28 = gpu.subgroup_mma_compute %23, %26, %arg1 : !gpu.mma_matrix<16x16xf16, "AOp">, !gpu.mma_matrix<16x16xf16, "BOp"> -> !gpu.mma_matrix<16x16xf16, "COp">
%29 = gpu.subgroup_mma_compute %24, %27, %28 : !gpu.mma_matrix<16x16xf16, "AOp">, !gpu.mma_matrix<16x16xf16, "BOp"> -> !gpu.mma_matrix<16x16xf16, "COp">
scf.yield %29 : !gpu.mma_matrix<16x16xf16, "COp">
}
%12 = affine.apply affine_map<()[s0, s1] -> (s0 * 16 + s1 * 32)>()[%2, %workgroup_id_y]
%13 = affine.apply affine_map<()[s0, s1] -> (s1 * 32 + (s0 floordiv 32) * 16)>()[%1, %workgroup_id_x]
- gpu.subgroup_mma_store_matrix %11, %8[%12, %13] {leadDimension = 1024 : index} : !gpu.mma_matrix<16x16xf16, "COp">, memref<3456x1024xf16>
+ gpu.subgroup_mma_store_matrix %11, %8[%12, %13] leadDimension 1024 : !gpu.mma_matrix<16x16xf16, "COp">, memref<3456x1024xf16>
return
}
// CHECK-LABEL: func.func @_matmul_f16_f16_dispatch_0_fill_3456x1024
@@ -94,13 +94,13 @@
%143 = arith.andi %140, %c6 : index
%144 = arith.shli %143, %c2 : index
%145 = arith.xori %141, %144 : index
- %146 = nvgpu.device_async_copy %3[%139, %138], %alloc_1[%142, %140, %145], 8 {bypassL1} : memref<512x1280xf16> to memref<3x128x32xf16, #gpu.address_space<workgroup>>
+ %146 = nvgpu.device_async_copy %3[%139, %138], %alloc_1[%142, %140, %145], 8 bypassL1 : memref<512x1280xf16> to memref<3x128x32xf16, #gpu.address_space<workgroup>>
%147 = affine.apply affine_map<()[s0, s1, s2, s3] -> (s1 * 32 + s2 * 64 + s3 * 128 + s0 floordiv 4 + 64)>()[%0, %1, %2, %workgroup_id_y]
%148 = affine.apply affine_map<()[s0, s1, s2] -> (s1 * 32 + s2 * 64 + s0 floordiv 4 + 64)>()[%0, %1, %2]
%149 = arith.andi %148, %c6 : index
%150 = arith.shli %149, %c2 : index
%151 = arith.xori %141, %150 : index
- %152 = nvgpu.device_async_copy %3[%147, %138], %alloc_1[%142, %148, %151], 8 {bypassL1} : memref<512x1280xf16> to memref<3x128x32xf16, #gpu.address_space<workgroup>>
+ %152 = nvgpu.device_async_copy %3[%147, %138], %alloc_1[%142, %148, %151], 8 bypassL1 : memref<512x1280xf16> to memref<3x128x32xf16, #gpu.address_space<workgroup>>
%153 = affine.apply affine_map<()[s0, s1, s2, s3] -> (s0 + s2 * 4 + s3 * 8 + s1 floordiv 32)>()[%arg0, %0, %1, %2]
%154 = affine.apply affine_map<()[s0, s1] -> (s0 * 8 + s1 * 256 - (s0 floordiv 32) * 256)>()[%0, %workgroup_id_x]
%155 = affine.apply affine_map<()[s0, s1, s2] -> (s1 * 4 + s2 * 8 + s0 floordiv 32)>()[%0, %1, %2]
@@ -108,25 +108,25 @@
%157 = arith.andi %155, %c31 : index
%158 = arith.shli %157, %c3 : index
%159 = arith.xori %156, %158 : index
- %160 = nvgpu.device_async_copy %4[%153, %154], %alloc_2[%142, %155, %159], 8 {bypassL1} : memref<1280x1280xf16> to memref<3x32x256xf16, #gpu.address_space<workgroup>>
+ %160 = nvgpu.device_async_copy %4[%153, %154], %alloc_2[%142, %155, %159], 8 bypassL1 : memref<1280x1280xf16> to memref<3x32x256xf16, #gpu.address_space<workgroup>>
%161 = affine.apply affine_map<()[s0, s1, s2, s3] -> (s0 + s2 * 4 + s3 * 8 + s1 floordiv 32 + 8)>()[%arg0, %0, %1, %2]
%162 = affine.apply affine_map<()[s0, s1, s2] -> (s1 * 4 + s2 * 8 + s0 floordiv 32 + 8)>()[%0, %1, %2]
%163 = arith.andi %162, %c31 : index
%164 = arith.shli %163, %c3 : index
%165 = arith.xori %156, %164 : index
- %166 = nvgpu.device_async_copy %4[%161, %154], %alloc_2[%142, %162, %165], 8 {bypassL1} : memref<1280x1280xf16> to memref<3x32x256xf16, #gpu.address_space<workgroup>>
+ %166 = nvgpu.device_async_copy %4[%161, %154], %alloc_2[%142, %162, %165], 8 bypassL1 : memref<1280x1280xf16> to memref<3x32x256xf16, #gpu.address_space<workgroup>>
%167 = affine.apply affine_map<()[s0, s1, s2, s3] -> (s0 + s2 * 4 + s3 * 8 + s1 floordiv 32 + 16)>()[%arg0, %0, %1, %2]
%168 = affine.apply affine_map<()[s0, s1, s2] -> (s1 * 4 + s2 * 8 + s0 floordiv 32 + 16)>()[%0, %1, %2]
%169 = arith.andi %168, %c31 : index
%170 = arith.shli %169, %c3 : index
%171 = arith.xori %156, %170 : index
- %172 = nvgpu.device_async_copy %4[%167, %154], %alloc_2[%142, %168, %171], 8 {bypassL1} : memref<1280x1280xf16> to memref<3x32x256xf16, #gpu.address_space<workgroup>>
+ %172 = nvgpu.device_async_copy %4[%167, %154], %alloc_2[%142, %168, %171], 8 bypassL1 : memref<1280x1280xf16> to memref<3x32x256xf16, #gpu.address_space<workgroup>>
%173 = affine.apply affine_map<()[s0, s1, s2, s3] -> (s0 + s2 * 4 + s3 * 8 + s1 floordiv 32 + 24)>()[%arg0, %0, %1, %2]
%174 = affine.apply affine_map<()[s0, s1, s2] -> (s1 * 4 + s2 * 8 + s0 floordiv 32 + 24)>()[%0, %1, %2]
%175 = arith.andi %174, %c31 : index
%176 = arith.shli %175, %c3 : index
%177 = arith.xori %156, %176 : index
- %178 = nvgpu.device_async_copy %4[%173, %154], %alloc_2[%142, %174, %177], 8 {bypassL1} : memref<1280x1280xf16> to memref<3x32x256xf16, #gpu.address_space<workgroup>>
+ %178 = nvgpu.device_async_copy %4[%173, %154], %alloc_2[%142, %174, %177], 8 bypassL1 : memref<1280x1280xf16> to memref<3x32x256xf16, #gpu.address_space<workgroup>>
%179 = nvgpu.device_async_create_group %146, %152, %160, %166, %172, %178
nvgpu.device_async_wait %179
gpu.barrier memfence [#gpu.address_space<workgroup>]
@@ -136,137 +136,137 @@
%183 = arith.andi %181, %c6 : index
%184 = arith.shli %183, %c2 : index
%185 = arith.xori %182, %184 : index
- %186 = nvgpu.ldmatrix %alloc_1[%142, %181, %185] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
+ %186 = nvgpu.ldmatrix %alloc_1[%142, %181, %185] numTiles = 4 transpose = false : memref<3x128x32xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
%187 = affine.apply affine_map<(d0) -> ((d0 floordiv 16) * 8 + 16)>(%180)
%188 = arith.xori %187, %184 : index
- %189 = nvgpu.ldmatrix %alloc_1[%142, %181, %188] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
+ %189 = nvgpu.ldmatrix %alloc_1[%142, %181, %188] numTiles = 4 transpose = false : memref<3x128x32xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
%190 = affine.apply affine_map<(d0)[s0] -> (d0 + s0 * 64 - (d0 floordiv 16) * 16 + 16)>(%180)[%1]
%191 = arith.andi %190, %c6 : index
%192 = arith.shli %191, %c2 : index
%193 = arith.xori %182, %192 : index
- %194 = nvgpu.ldmatrix %alloc_1[%142, %190, %193] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
+ %194 = nvgpu.ldmatrix %alloc_1[%142, %190, %193] numTiles = 4 transpose = false : memref<3x128x32xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
%195 = arith.xori %187, %192 : index
- %196 = nvgpu.ldmatrix %alloc_1[%142, %190, %195] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
+ %196 = nvgpu.ldmatrix %alloc_1[%142, %190, %195] numTiles = 4 transpose = false : memref<3x128x32xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
%197 = affine.apply affine_map<(d0)[s0] -> (d0 + s0 * 64 - (d0 floordiv 16) * 16 + 32)>(%180)[%1]
%198 = arith.andi %197, %c6 : index
%199 = arith.shli %198, %c2 : index
%200 = arith.xori %182, %199 : index
- %201 = nvgpu.ldmatrix %alloc_1[%142, %197, %200] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
+ %201 = nvgpu.ldmatrix %alloc_1[%142, %197, %200] numTiles = 4 transpose = false : memref<3x128x32xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
%202 = arith.xori %187, %199 : index
- %203 = nvgpu.ldmatrix %alloc_1[%142, %197, %202] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
+ %203 = nvgpu.ldmatrix %alloc_1[%142, %197, %202] numTiles = 4 transpose = false : memref<3x128x32xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
%204 = affine.apply affine_map<(d0)[s0] -> (d0 + s0 * 64 - (d0 floordiv 16) * 16 + 48)>(%180)[%1]
%205 = arith.andi %204, %c6 : index
%206 = arith.shli %205, %c2 : index
%207 = arith.xori %182, %206 : index
- %208 = nvgpu.ldmatrix %alloc_1[%142, %204, %207] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
+ %208 = nvgpu.ldmatrix %alloc_1[%142, %204, %207] numTiles = 4 transpose = false : memref<3x128x32xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
%209 = arith.xori %187, %206 : index
- %210 = nvgpu.ldmatrix %alloc_1[%142, %204, %209] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
+ %210 = nvgpu.ldmatrix %alloc_1[%142, %204, %209] numTiles = 4 transpose = false : memref<3x128x32xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
%211 = affine.apply affine_map<(d0)[s0] -> ((d0 floordiv 16) * 8 + (s0 floordiv 32) * 64)>(%180)[%0]
%212 = affine.apply affine_map<(d0) -> (d0 mod 16)>(%180)
%213 = arith.andi %212, %c31 : index
%214 = arith.shli %213, %c3 : index
%215 = arith.xori %211, %214 : index
- %216 = nvgpu.ldmatrix %alloc_2[%142, %212, %215] {numTiles = 4 : i32, transpose = true} : memref<3x32x256xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
+ %216 = nvgpu.ldmatrix %alloc_2[%142, %212, %215] numTiles = 4 transpose = true : memref<3x32x256xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
%217 = affine.apply affine_map<(d0) -> (d0 mod 16 + 16)>(%180)
%218 = arith.andi %217, %c31 : index
%219 = arith.shli %218, %c3 : index
%220 = arith.xori %211, %219 : index
- %221 = nvgpu.ldmatrix %alloc_2[%142, %217, %220] {numTiles = 4 : i32, transpose = true} : memref<3x32x256xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
+ %221 = nvgpu.ldmatrix %alloc_2[%142, %217, %220] numTiles = 4 transpose = true : memref<3x32x256xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
%222 = affine.apply affine_map<(d0)[s0] -> ((d0 floordiv 16) * 8 + (s0 floordiv 32) * 64 + 16)>(%180)[%0]
%223 = arith.xori %222, %214 : index
- %224 = nvgpu.ldmatrix %alloc_2[%142, %212, %223] {numTiles = 4 : i32, transpose = true} : memref<3x32x256xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
+ %224 = nvgpu.ldmatrix %alloc_2[%142, %212, %223] numTiles = 4 transpose = true : memref<3x32x256xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
%225 = arith.xori %222, %219 : index
- %226 = nvgpu.ldmatrix %alloc_2[%142, %217, %225] {numTiles = 4 : i32, transpose = true} : memref<3x32x256xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
+ %226 = nvgpu.ldmatrix %alloc_2[%142, %217, %225] numTiles = 4 transpose = true : memref<3x32x256xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
%227 = affine.apply affine_map<(d0)[s0] -> ((d0 floordiv 16) * 8 + (s0 floordiv 32) * 64 + 32)>(%180)[%0]
%228 = arith.xori %227, %214 : index
- %229 = nvgpu.ldmatrix %alloc_2[%142, %212, %228] {numTiles = 4 : i32, transpose = true} : memref<3x32x256xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
+ %229 = nvgpu.ldmatrix %alloc_2[%142, %212, %228] numTiles = 4 transpose = true : memref<3x32x256xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
%230 = arith.xori %227, %219 : index
- %231 = nvgpu.ldmatrix %alloc_2[%142, %217, %230] {numTiles = 4 : i32, transpose = true} : memref<3x32x256xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
+ %231 = nvgpu.ldmatrix %alloc_2[%142, %217, %230] numTiles = 4 transpose = true : memref<3x32x256xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
%232 = affine.apply affine_map<(d0)[s0] -> ((d0 floordiv 16) * 8 + (s0 floordiv 32) * 64 + 48)>(%180)[%0]
%233 = arith.xori %232, %214 : index
- %234 = nvgpu.ldmatrix %alloc_2[%142, %212, %233] {numTiles = 4 : i32, transpose = true} : memref<3x32x256xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
+ %234 = nvgpu.ldmatrix %alloc_2[%142, %212, %233] numTiles = 4 transpose = true : memref<3x32x256xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
%235 = arith.xori %232, %219 : index
- %236 = nvgpu.ldmatrix %alloc_2[%142, %217, %235] {numTiles = 4 : i32, transpose = true} : memref<3x32x256xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
- %237 = vector.extract_strided_slice %216 {offsets = [0, 0], sizes = [2, 2], strides = [1, 1]} : vector<4x2xf16> to vector<2x2xf16>
- %238 = nvgpu.mma.sync(%186, %237, %arg1) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %239 = vector.extract_strided_slice %216 {offsets = [2, 0], sizes = [2, 2], strides = [1, 1]} : vector<4x2xf16> to vector<2x2xf16>
- %240 = nvgpu.mma.sync(%186, %239, %arg2) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %241 = vector.extract_strided_slice %224 {offsets = [0, 0], sizes = [2, 2], strides = [1, 1]} : vector<4x2xf16> to vector<2x2xf16>
- %242 = nvgpu.mma.sync(%186, %241, %arg3) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %243 = vector.extract_strided_slice %224 {offsets = [2, 0], sizes = [2, 2], strides = [1, 1]} : vector<4x2xf16> to vector<2x2xf16>
- %244 = nvgpu.mma.sync(%186, %243, %arg4) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %245 = vector.extract_strided_slice %229 {offsets = [0, 0], sizes = [2, 2], strides = [1, 1]} : vector<4x2xf16> to vector<2x2xf16>
- %246 = nvgpu.mma.sync(%186, %245, %arg5) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %247 = vector.extract_strided_slice %229 {offsets = [2, 0], sizes = [2, 2], strides = [1, 1]} : vector<4x2xf16> to vector<2x2xf16>
- %248 = nvgpu.mma.sync(%186, %247, %arg6) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %249 = vector.extract_strided_slice %234 {offsets = [0, 0], sizes = [2, 2], strides = [1, 1]} : vector<4x2xf16> to vector<2x2xf16>
- %250 = nvgpu.mma.sync(%186, %249, %arg7) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %251 = vector.extract_strided_slice %234 {offsets = [2, 0], sizes = [2, 2], strides = [1, 1]} : vector<4x2xf16> to vector<2x2xf16>
- %252 = nvgpu.mma.sync(%186, %251, %arg8) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %253 = nvgpu.mma.sync(%194, %237, %arg9) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %254 = nvgpu.mma.sync(%194, %239, %arg10) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %255 = nvgpu.mma.sync(%194, %241, %arg11) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %256 = nvgpu.mma.sync(%194, %243, %arg12) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %257 = nvgpu.mma.sync(%194, %245, %arg13) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %258 = nvgpu.mma.sync(%194, %247, %arg14) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %259 = nvgpu.mma.sync(%194, %249, %arg15) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %260 = nvgpu.mma.sync(%194, %251, %arg16) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %261 = nvgpu.mma.sync(%201, %237, %arg17) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %262 = nvgpu.mma.sync(%201, %239, %arg18) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %263 = nvgpu.mma.sync(%201, %241, %arg19) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %264 = nvgpu.mma.sync(%201, %243, %arg20) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %265 = nvgpu.mma.sync(%201, %245, %arg21) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %266 = nvgpu.mma.sync(%201, %247, %arg22) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %267 = nvgpu.mma.sync(%201, %249, %arg23) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %268 = nvgpu.mma.sync(%201, %251, %arg24) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %269 = nvgpu.mma.sync(%208, %237, %arg25) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %270 = nvgpu.mma.sync(%208, %239, %arg26) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %271 = nvgpu.mma.sync(%208, %241, %arg27) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %272 = nvgpu.mma.sync(%208, %243, %arg28) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %273 = nvgpu.mma.sync(%208, %245, %arg29) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %274 = nvgpu.mma.sync(%208, %247, %arg30) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %275 = nvgpu.mma.sync(%208, %249, %arg31) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %276 = nvgpu.mma.sync(%208, %251, %arg32) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %277 = vector.extract_strided_slice %221 {offsets = [0, 0], sizes = [2, 2], strides = [1, 1]} : vector<4x2xf16> to vector<2x2xf16>
- %278 = nvgpu.mma.sync(%189, %277, %238) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %279 = vector.extract_strided_slice %221 {offsets = [2, 0], sizes = [2, 2], strides = [1, 1]} : vector<4x2xf16> to vector<2x2xf16>
- %280 = nvgpu.mma.sync(%189, %279, %240) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %281 = vector.extract_strided_slice %226 {offsets = [0, 0], sizes = [2, 2], strides = [1, 1]} : vector<4x2xf16> to vector<2x2xf16>
- %282 = nvgpu.mma.sync(%189, %281, %242) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %283 = vector.extract_strided_slice %226 {offsets = [2, 0], sizes = [2, 2], strides = [1, 1]} : vector<4x2xf16> to vector<2x2xf16>
- %284 = nvgpu.mma.sync(%189, %283, %244) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %285 = vector.extract_strided_slice %231 {offsets = [0, 0], sizes = [2, 2], strides = [1, 1]} : vector<4x2xf16> to vector<2x2xf16>
- %286 = nvgpu.mma.sync(%189, %285, %246) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %287 = vector.extract_strided_slice %231 {offsets = [2, 0], sizes = [2, 2], strides = [1, 1]} : vector<4x2xf16> to vector<2x2xf16>
- %288 = nvgpu.mma.sync(%189, %287, %248) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %289 = vector.extract_strided_slice %236 {offsets = [0, 0], sizes = [2, 2], strides = [1, 1]} : vector<4x2xf16> to vector<2x2xf16>
- %290 = nvgpu.mma.sync(%189, %289, %250) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %291 = vector.extract_strided_slice %236 {offsets = [2, 0], sizes = [2, 2], strides = [1, 1]} : vector<4x2xf16> to vector<2x2xf16>
- %292 = nvgpu.mma.sync(%189, %291, %252) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %293 = nvgpu.mma.sync(%196, %277, %253) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %294 = nvgpu.mma.sync(%196, %279, %254) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %295 = nvgpu.mma.sync(%196, %281, %255) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %296 = nvgpu.mma.sync(%196, %283, %256) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %297 = nvgpu.mma.sync(%196, %285, %257) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %298 = nvgpu.mma.sync(%196, %287, %258) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %299 = nvgpu.mma.sync(%196, %289, %259) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %300 = nvgpu.mma.sync(%196, %291, %260) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %301 = nvgpu.mma.sync(%203, %277, %261) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %302 = nvgpu.mma.sync(%203, %279, %262) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %303 = nvgpu.mma.sync(%203, %281, %263) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %304 = nvgpu.mma.sync(%203, %283, %264) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %305 = nvgpu.mma.sync(%203, %285, %265) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %306 = nvgpu.mma.sync(%203, %287, %266) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %307 = nvgpu.mma.sync(%203, %289, %267) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %308 = nvgpu.mma.sync(%203, %291, %268) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %309 = nvgpu.mma.sync(%210, %277, %269) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %310 = nvgpu.mma.sync(%210, %279, %270) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %311 = nvgpu.mma.sync(%210, %281, %271) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %312 = nvgpu.mma.sync(%210, %283, %272) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %313 = nvgpu.mma.sync(%210, %285, %273) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %314 = nvgpu.mma.sync(%210, %287, %274) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %315 = nvgpu.mma.sync(%210, %289, %275) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
- %316 = nvgpu.mma.sync(%210, %291, %276) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %236 = nvgpu.ldmatrix %alloc_2[%142, %217, %235] numTiles = 4 transpose = true : memref<3x32x256xf16, #gpu.address_space<workgroup>> -> vector<4x2xf16>
+ %237 = vector.extract_strided_slice %216 offsets = [0, 0], sizes = [2, 2], strides = [1, 1] : vector<4x2xf16> to vector<2x2xf16>
+ %238 = nvgpu.mma.sync(%186, %237, %arg1) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %239 = vector.extract_strided_slice %216 offsets = [2, 0], sizes = [2, 2], strides = [1, 1] : vector<4x2xf16> to vector<2x2xf16>
+ %240 = nvgpu.mma.sync(%186, %239, %arg2) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %241 = vector.extract_strided_slice %224 offsets = [0, 0], sizes = [2, 2], strides = [1, 1] : vector<4x2xf16> to vector<2x2xf16>
+ %242 = nvgpu.mma.sync(%186, %241, %arg3) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %243 = vector.extract_strided_slice %224 offsets = [2, 0], sizes = [2, 2], strides = [1, 1] : vector<4x2xf16> to vector<2x2xf16>
+ %244 = nvgpu.mma.sync(%186, %243, %arg4) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %245 = vector.extract_strided_slice %229 offsets = [0, 0], sizes = [2, 2], strides = [1, 1] : vector<4x2xf16> to vector<2x2xf16>
+ %246 = nvgpu.mma.sync(%186, %245, %arg5) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %247 = vector.extract_strided_slice %229 offsets = [2, 0], sizes = [2, 2], strides = [1, 1] : vector<4x2xf16> to vector<2x2xf16>
+ %248 = nvgpu.mma.sync(%186, %247, %arg6) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %249 = vector.extract_strided_slice %234 offsets = [0, 0], sizes = [2, 2], strides = [1, 1] : vector<4x2xf16> to vector<2x2xf16>
+ %250 = nvgpu.mma.sync(%186, %249, %arg7) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %251 = vector.extract_strided_slice %234 offsets = [2, 0], sizes = [2, 2], strides = [1, 1] : vector<4x2xf16> to vector<2x2xf16>
+ %252 = nvgpu.mma.sync(%186, %251, %arg8) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %253 = nvgpu.mma.sync(%194, %237, %arg9) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %254 = nvgpu.mma.sync(%194, %239, %arg10) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %255 = nvgpu.mma.sync(%194, %241, %arg11) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %256 = nvgpu.mma.sync(%194, %243, %arg12) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %257 = nvgpu.mma.sync(%194, %245, %arg13) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %258 = nvgpu.mma.sync(%194, %247, %arg14) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %259 = nvgpu.mma.sync(%194, %249, %arg15) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %260 = nvgpu.mma.sync(%194, %251, %arg16) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %261 = nvgpu.mma.sync(%201, %237, %arg17) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %262 = nvgpu.mma.sync(%201, %239, %arg18) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %263 = nvgpu.mma.sync(%201, %241, %arg19) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %264 = nvgpu.mma.sync(%201, %243, %arg20) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %265 = nvgpu.mma.sync(%201, %245, %arg21) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %266 = nvgpu.mma.sync(%201, %247, %arg22) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %267 = nvgpu.mma.sync(%201, %249, %arg23) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %268 = nvgpu.mma.sync(%201, %251, %arg24) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %269 = nvgpu.mma.sync(%208, %237, %arg25) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %270 = nvgpu.mma.sync(%208, %239, %arg26) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %271 = nvgpu.mma.sync(%208, %241, %arg27) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %272 = nvgpu.mma.sync(%208, %243, %arg28) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %273 = nvgpu.mma.sync(%208, %245, %arg29) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %274 = nvgpu.mma.sync(%208, %247, %arg30) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %275 = nvgpu.mma.sync(%208, %249, %arg31) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %276 = nvgpu.mma.sync(%208, %251, %arg32) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %277 = vector.extract_strided_slice %221 offsets = [0, 0], sizes = [2, 2], strides = [1, 1] : vector<4x2xf16> to vector<2x2xf16>
+ %278 = nvgpu.mma.sync(%189, %277, %238) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %279 = vector.extract_strided_slice %221 offsets = [2, 0], sizes = [2, 2], strides = [1, 1] : vector<4x2xf16> to vector<2x2xf16>
+ %280 = nvgpu.mma.sync(%189, %279, %240) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %281 = vector.extract_strided_slice %226 offsets = [0, 0], sizes = [2, 2], strides = [1, 1] : vector<4x2xf16> to vector<2x2xf16>
+ %282 = nvgpu.mma.sync(%189, %281, %242) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %283 = vector.extract_strided_slice %226 offsets = [2, 0], sizes = [2, 2], strides = [1, 1] : vector<4x2xf16> to vector<2x2xf16>
+ %284 = nvgpu.mma.sync(%189, %283, %244) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %285 = vector.extract_strided_slice %231 offsets = [0, 0], sizes = [2, 2], strides = [1, 1] : vector<4x2xf16> to vector<2x2xf16>
+ %286 = nvgpu.mma.sync(%189, %285, %246) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %287 = vector.extract_strided_slice %231 offsets = [2, 0], sizes = [2, 2], strides = [1, 1] : vector<4x2xf16> to vector<2x2xf16>
+ %288 = nvgpu.mma.sync(%189, %287, %248) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %289 = vector.extract_strided_slice %236 offsets = [0, 0], sizes = [2, 2], strides = [1, 1] : vector<4x2xf16> to vector<2x2xf16>
+ %290 = nvgpu.mma.sync(%189, %289, %250) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %291 = vector.extract_strided_slice %236 offsets = [2, 0], sizes = [2, 2], strides = [1, 1] : vector<4x2xf16> to vector<2x2xf16>
+ %292 = nvgpu.mma.sync(%189, %291, %252) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %293 = nvgpu.mma.sync(%196, %277, %253) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %294 = nvgpu.mma.sync(%196, %279, %254) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %295 = nvgpu.mma.sync(%196, %281, %255) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %296 = nvgpu.mma.sync(%196, %283, %256) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %297 = nvgpu.mma.sync(%196, %285, %257) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %298 = nvgpu.mma.sync(%196, %287, %258) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %299 = nvgpu.mma.sync(%196, %289, %259) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %300 = nvgpu.mma.sync(%196, %291, %260) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %301 = nvgpu.mma.sync(%203, %277, %261) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %302 = nvgpu.mma.sync(%203, %279, %262) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %303 = nvgpu.mma.sync(%203, %281, %263) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %304 = nvgpu.mma.sync(%203, %283, %264) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %305 = nvgpu.mma.sync(%203, %285, %265) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %306 = nvgpu.mma.sync(%203, %287, %266) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %307 = nvgpu.mma.sync(%203, %289, %267) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %308 = nvgpu.mma.sync(%203, %291, %268) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %309 = nvgpu.mma.sync(%210, %277, %269) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %310 = nvgpu.mma.sync(%210, %279, %270) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %311 = nvgpu.mma.sync(%210, %281, %271) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %312 = nvgpu.mma.sync(%210, %283, %272) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %313 = nvgpu.mma.sync(%210, %285, %273) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %314 = nvgpu.mma.sync(%210, %287, %274) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %315 = nvgpu.mma.sync(%210, %289, %275) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+ %316 = nvgpu.mma.sync(%210, %291, %276) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
scf.yield %278, %280, %282, %284, %286, %288, %290, %292, %293, %294, %295, %296, %297, %298, %299, %300, %301, %302, %303, %304, %305, %306, %307, %308, %309, %310, %311, %312, %313, %314, %315, %316 : vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>, vector<2x2xf16>
}
%7 = gpu.lane_id
@@ -490,7 +490,7 @@
// CHECK-NV: nvgpu.device_async_create_group
// CHECK-NV-COUNT-6: nvgpu.device_async_copy
// CHECK-NV: nvgpu.device_async_create_group
-// CHECK-NV: nvgpu.device_async_wait %{{.*}} {numGroups = 1 : i32}
+// CHECK-NV: nvgpu.device_async_wait %{{.*}} numGroups = 1
// CHECK-NV: gpu.barrier memfence [#gpu.address_space<workgroup>]
// CHECK-NV-COUNT-8: nvgpu.ldmatrix
// CHECK-NV: scf.for
@@ -498,7 +498,7 @@
// CHECK-NV-COUNT-32: nvgpu.mma.sync
// CHECK-NV-COUNT-6: nvgpu.device_async_copy
// CHECK-NV: nvgpu.device_async_create_group
-// CHECK-NV: nvgpu.device_async_wait %{{.*}} {numGroups = 1 : i32}
+// CHECK-NV: nvgpu.device_async_wait %{{.*}} numGroups = 1
// CHECK-NV: gpu.barrier memfence [#gpu.address_space<workgroup>]
// CHECK-NV-COUNT-8: nvgpu.ldmatrix
// CHECK-NV-COUNT-32: nvgpu.mma.sync
@@ -741,49 +741,49 @@
gpu.barrier memfence [#gpu.address_space<workgroup>]
%390 = affine.apply affine_map<()[s0, s1] -> (s0 + s1 * 4 - (s1 floordiv 8) * 32)>()[%arg0, %0]
%391 = affine.apply affine_map<(d0) -> ((d0 floordiv 32) mod 3)>(%arg0)
- %392 = nvgpu.device_async_copy %3[%6, %390], %alloc_2[%391, %7, %11], 4 {bypassL1} : memref<256x256xf32> to memref<3x128x32xf32, #gpu.address_space<workgroup>>
- %393 = nvgpu.device_async_copy %3[%12, %390], %alloc_2[%391, %13, %16], 4 {bypassL1} : memref<256x256xf32> to memref<3x128x32xf32, #gpu.address_space<workgroup>>
- %394 = nvgpu.device_async_copy %3[%17, %390], %alloc_2[%391, %18, %21], 4 {bypassL1} : memref<256x256xf32> to memref<3x128x32xf32, #gpu.address_space<workgroup>>
- %395 = nvgpu.device_async_copy %3[%22, %390], %alloc_2[%391, %23, %26], 4 {bypassL1} : memref<256x256xf32> to memref<3x128x32xf32, #gpu.address_space<workgroup>>
- %396 = nvgpu.device_async_copy %3[%27, %390], %alloc_2[%391, %28, %31], 4 {bypassL1} : memref<256x256xf32> to memref<3x128x32xf32, #gpu.address_space<workgroup>>
- %397 = nvgpu.device_async_copy %3[%32, %390], %alloc_2[%391, %33, %36], 4 {bypassL1} : memref<256x256xf32> to memref<3x128x32xf32, #gpu.address_space<workgroup>>
- %398 = nvgpu.device_async_copy %3[%37, %390], %alloc_2[%391, %38, %41], 4 {bypassL1} : memref<256x256xf32> to memref<3x128x32xf32, #gpu.address_space<workgroup>>
- %399 = nvgpu.device_async_copy %3[%42, %390], %alloc_2[%391, %43, %46], 4 {bypassL1} : memref<256x256xf32> to memref<3x128x32xf32, #gpu.address_space<workgroup>>
+ %392 = nvgpu.device_async_copy %3[%6, %390], %alloc_2[%391, %7, %11], 4 bypassL1 : memref<256x256xf32> to memref<3x128x32xf32, #gpu.address_space<workgroup>>
+ %393 = nvgpu.device_async_copy %3[%12, %390], %alloc_2[%391, %13, %16], 4 bypassL1 : memref<256x256xf32> to memref<3x128x32xf32, #gpu.address_space<workgroup>>
+ %394 = nvgpu.device_async_copy %3[%17, %390], %alloc_2[%391, %18, %21], 4 bypassL1 : memref<256x256xf32> to memref<3x128x32xf32, #gpu.address_space<workgroup>>
+ %395 = nvgpu.device_async_copy %3[%22, %390], %alloc_2[%391, %23, %26], 4 bypassL1 : memref<256x256xf32> to memref<3x128x32xf32, #gpu.address_space<workgroup>>
+ %396 = nvgpu.device_async_copy %3[%27, %390], %alloc_2[%391, %28, %31], 4 bypassL1 : memref<256x256xf32> to memref<3x128x32xf32, #gpu.address_space<workgroup>>
+ %397 = nvgpu.device_async_copy %3[%32, %390], %alloc_2[%391, %33, %36], 4 bypassL1 : memref<256x256xf32> to memref<3x128x32xf32, #gpu.address_space<workgroup>>
+ %398 = nvgpu.device_async_copy %3[%37, %390], %alloc_2[%391, %38, %41], 4 bypassL1 : memref<256x256xf32> to memref<3x128x32xf32, #gpu.address_space<workgroup>>
+ %399 = nvgpu.device_async_copy %3[%42, %390], %alloc_2[%391, %43, %46], 4 bypassL1 : memref<256x256xf32> to memref<3x128x32xf32, #gpu.address_space<workgroup>>
%400 = affine.apply affine_map<()[s0, s1, s2, s3] -> (s0 + s2 * 2 + s3 * 4 + s1 floordiv 32)>()[%arg0, %0, %1, %2]
- %401 = nvgpu.device_async_copy %4[%400, %47], %alloc_3[%391, %48, %52], 4 {bypassL1} : memref<256x256xf32> to memref<3x32x128xf32, #gpu.address_space<workgroup>>
+ %401 = nvgpu.device_async_copy %4[%400, %47], %alloc_3[%391, %48, %52], 4 bypassL1 : memref<256x256xf32> to memref<3x32x128xf32, #gpu.address_space<workgroup>>
%402 = affine.apply affine_map<()[s0, s1, s2, s3] -> (s0 + s2 * 2 + s3 * 4 + s1 floordiv 32 + 4)>()[%arg0, %0, %1, %2]
- %403 = nvgpu.device_async_copy %4[%402, %47], %alloc_3[%391, %53, %56], 4 {bypassL1} : memref<256x256xf32> to memref<3x32x128xf32, #gpu.address_space<workgroup>>
+ %403 = nvgpu.device_async_copy %4[%402, %47], %alloc_3[%391, %53, %56], 4 bypassL1 : memref<256x256xf32> to memref<3x32x128xf32, #gpu.address_space<workgroup>>
%404 = affine.apply affine_map<()[s0, s1, s2, s3] -> (s0 + s2 * 2 + s3 * 4 + s1 floordiv 32 + 8)>()[%arg0, %0, %1, %2]
- %405 = nvgpu.device_async_copy %4[%404, %47], %alloc_3[%391, %57, %60], 4 {bypassL1} : memref<256x256xf32> to memref<3x32x128xf32, #gpu.address_space<workgroup>>
+ %405 = nvgpu.device_async_copy %4[%404, %47], %alloc_3[%391, %57, %60], 4 bypassL1 : memref<256x256xf32> to memref<3x32x128xf32, #gpu.address_space<workgroup>>
%406 = affine.apply affine_map<()[s0, s1, s2, s3] -> (s0 + s2 * 2 + s3 * 4 + s1 floordiv 32 + 12)>()[%arg0, %0, %1, %2]
- %407 = nvgpu.device_async_copy %4[%406, %47], %alloc_3[%391, %61, %64], 4 {bypassL1} : memref<256x256xf32> to memref<3x32x128xf32, #gpu.address_space<workgroup>>
+ %407 = nvgpu.device_async_copy %4[%406, %47], %alloc_3[%391, %61, %64], 4 bypassL1 : memref<256x256xf32> to memref<3x32x128xf32, #gpu.address_space<workgroup>>
%408 = affine.apply affine_map<()[s0, s1, s2, s3] -> (s0 + s2 * 2 + s3 * 4 + s1 floordiv 32 + 16)>()[%arg0, %0, %1, %2]
- %409 = nvgpu.device_async_copy %4[%408, %47], %alloc_3[%391, %65, %68], 4 {bypassL1} : memref<256x256xf32> to memref<3x32x128xf32, #gpu.address_space<workgroup>>
+ %409 = nvgpu.device_async_copy %4[%408, %47], %alloc_3[%391, %65, %68], 4 bypassL1 : memref<256x256xf32> to memref<3x32x128xf32, #gpu.address_space<workgroup>>
%410 = affine.apply affine_map<()[s0, s1, s2, s3] -> (s0 + s2 * 2 + s3 * 4 + s1 floordiv 32 + 20)>()[%arg0, %0, %1, %2]
- %411 = nvgpu.device_async_copy %4[%410, %47], %alloc_3[%391, %69, %72], 4 {bypassL1} : memref<256x256xf32> to memref<3x32x128xf32, #gpu.address_space<workgroup>>
+ %411 = nvgpu.device_async_copy %4[%410, %47], %alloc_3[%391, %69, %72], 4 bypassL1 : memref<256x256xf32> to memref<3x32x128xf32, #gpu.address_space<workgroup>>
%412 = affine.apply affine_map<()[s0, s1, s2, s3] -> (s0 + s2 * 2 + s3 * 4 + s1 floordiv 32 + 24)>()[%arg0, %0, %1, %2]
- %413 = nvgpu.device_async_copy %4[%412, %47], %alloc_3[%391, %73, %76], 4 {bypassL1} : memref<256x256xf32> to memref<3x32x128xf32, #gpu.address_space<workgroup>>
+ %413 = nvgpu.device_async_copy %4[%412, %47], %alloc_3[%391, %73, %76], 4 bypassL1 : memref<256x256xf32> to memref<3x32x128xf32, #gpu.address_space<workgroup>>
%414 = affine.apply affine_map<()[s0, s1, s2, s3] -> (s0 + s2 * 2 + s3 * 4 + s1 floordiv 32 + 28)>()[%arg0, %0, %1, %2]
- %415 = nvgpu.device_async_copy %4[%414, %47], %alloc_3[%391, %77, %80], 4 {bypassL1} : memref<256x256xf32> to memref<3x32x128xf32, #gpu.address_space<workgroup>>
+ %415 = nvgpu.device_async_copy %4[%414, %47], %alloc_3[%391, %77, %80], 4 bypassL1 : memref<256x256xf32> to memref<3x32x128xf32, #gpu.address_space<workgroup>>
%416 = nvgpu.device_async_create_group %392, %393, %394, %395, %396, %397, %398, %399, %401, %403, %405, %407, %409, %411, %413, %415
nvgpu.device_async_wait %416
gpu.barrier memfence [#gpu.address_space<workgroup>]
- %417 = nvgpu.ldmatrix %alloc_2[%391, %82, %86] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
- %418 = nvgpu.ldmatrix %alloc_2[%391, %82, %88] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
- %419 = nvgpu.ldmatrix %alloc_2[%391, %82, %90] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
- %420 = nvgpu.ldmatrix %alloc_2[%391, %82, %92] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
- %421 = nvgpu.ldmatrix %alloc_2[%391, %93, %96] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
- %422 = nvgpu.ldmatrix %alloc_2[%391, %93, %97] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
- %423 = nvgpu.ldmatrix %alloc_2[%391, %93, %98] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
- %424 = nvgpu.ldmatrix %alloc_2[%391, %93, %99] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
- %425 = nvgpu.ldmatrix %alloc_2[%391, %100, %103] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
- %426 = nvgpu.ldmatrix %alloc_2[%391, %100, %104] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
- %427 = nvgpu.ldmatrix %alloc_2[%391, %100, %105] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
- %428 = nvgpu.ldmatrix %alloc_2[%391, %100, %106] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
- %429 = nvgpu.ldmatrix %alloc_2[%391, %107, %110] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
- %430 = nvgpu.ldmatrix %alloc_2[%391, %107, %111] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
- %431 = nvgpu.ldmatrix %alloc_2[%391, %107, %112] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
- %432 = nvgpu.ldmatrix %alloc_2[%391, %107, %113] {numTiles = 4 : i32, transpose = false} : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
+ %417 = nvgpu.ldmatrix %alloc_2[%391, %82, %86] numTiles = 4 transpose = false : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
+ %418 = nvgpu.ldmatrix %alloc_2[%391, %82, %88] numTiles = 4 transpose = false : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
+ %419 = nvgpu.ldmatrix %alloc_2[%391, %82, %90] numTiles = 4 transpose = false : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
+ %420 = nvgpu.ldmatrix %alloc_2[%391, %82, %92] numTiles = 4 transpose = false : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
+ %421 = nvgpu.ldmatrix %alloc_2[%391, %93, %96] numTiles = 4 transpose = false : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
+ %422 = nvgpu.ldmatrix %alloc_2[%391, %93, %97] numTiles = 4 transpose = false : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
+ %423 = nvgpu.ldmatrix %alloc_2[%391, %93, %98] numTiles = 4 transpose = false : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
+ %424 = nvgpu.ldmatrix %alloc_2[%391, %93, %99] numTiles = 4 transpose = false : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
+ %425 = nvgpu.ldmatrix %alloc_2[%391, %100, %103] numTiles = 4 transpose = false : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
+ %426 = nvgpu.ldmatrix %alloc_2[%391, %100, %104] numTiles = 4 transpose = false : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
+ %427 = nvgpu.ldmatrix %alloc_2[%391, %100, %105] numTiles = 4 transpose = false : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
+ %428 = nvgpu.ldmatrix %alloc_2[%391, %100, %106] numTiles = 4 transpose = false : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
+ %429 = nvgpu.ldmatrix %alloc_2[%391, %107, %110] numTiles = 4 transpose = false : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
+ %430 = nvgpu.ldmatrix %alloc_2[%391, %107, %111] numTiles = 4 transpose = false : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
+ %431 = nvgpu.ldmatrix %alloc_2[%391, %107, %112] numTiles = 4 transpose = false : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
+ %432 = nvgpu.ldmatrix %alloc_2[%391, %107, %113] numTiles = 4 transpose = false : memref<3x128x32xf32, #gpu.address_space<workgroup>> -> vector<4x1xf32>
%433 = memref.load %alloc_3[%391, %115, %118] : memref<3x32x128xf32, #gpu.address_space<workgroup>>
%434 = vector.insert %433, %cst [0, 0] : f32 into vector<2x1xf32>
%435 = memref.load %alloc_3[%391, %119, %122] : memref<3x32x128xf32, #gpu.address_space<workgroup>>
@@ -912,134 +912,134 @@
%558 = vector.insert %557, %cst [0, 0] : f32 into vector<2x1xf32>
%559 = memref.load %alloc_3[%391, %143, %209] : memref<3x32x128xf32, #gpu.address_space<workgroup>>
%560 = vector.insert %559, %558 [1, 0] : f32 into vector<2x1xf32>
- %561 = nvgpu.mma.sync(%417, %436, %arg1) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %562 = nvgpu.mma.sync(%417, %452, %arg2) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %563 = nvgpu.mma.sync(%417, %468, %arg3) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %564 = nvgpu.mma.sync(%417, %484, %arg4) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %565 = nvgpu.mma.sync(%417, %500, %arg5) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %566 = nvgpu.mma.sync(%417, %516, %arg6) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %567 = nvgpu.mma.sync(%417, %532, %arg7) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %568 = nvgpu.mma.sync(%417, %548, %arg8) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %569 = nvgpu.mma.sync(%421, %436, %arg9) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %570 = nvgpu.mma.sync(%421, %452, %arg10) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %571 = nvgpu.mma.sync(%421, %468, %arg11) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %572 = nvgpu.mma.sync(%421, %484, %arg12) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %573 = nvgpu.mma.sync(%421, %500, %arg13) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %574 = nvgpu.mma.sync(%421, %516, %arg14) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %575 = nvgpu.mma.sync(%421, %532, %arg15) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %576 = nvgpu.mma.sync(%421, %548, %arg16) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %577 = nvgpu.mma.sync(%425, %436, %arg17) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %578 = nvgpu.mma.sync(%425, %452, %arg18) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %579 = nvgpu.mma.sync(%425, %468, %arg19) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %580 = nvgpu.mma.sync(%425, %484, %arg20) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %581 = nvgpu.mma.sync(%425, %500, %arg21) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %582 = nvgpu.mma.sync(%425, %516, %arg22) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %583 = nvgpu.mma.sync(%425, %532, %arg23) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %584 = nvgpu.mma.sync(%425, %548, %arg24) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %585 = nvgpu.mma.sync(%429, %436, %arg25) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %586 = nvgpu.mma.sync(%429, %452, %arg26) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %587 = nvgpu.mma.sync(%429, %468, %arg27) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %588 = nvgpu.mma.sync(%429, %484, %arg28) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %589 = nvgpu.mma.sync(%429, %500, %arg29) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %590 = nvgpu.mma.sync(%429, %516, %arg30) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %591 = nvgpu.mma.sync(%429, %532, %arg31) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %592 = nvgpu.mma.sync(%429, %548, %arg32) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %593 = nvgpu.mma.sync(%418, %440, %561) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %594 = nvgpu.mma.sync(%418, %456, %562) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %595 = nvgpu.mma.sync(%418, %472, %563) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %596 = nvgpu.mma.sync(%418, %488, %564) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %597 = nvgpu.mma.sync(%418, %504, %565) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %598 = nvgpu.mma.sync(%418, %520, %566) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %599 = nvgpu.mma.sync(%418, %536, %567) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %600 = nvgpu.mma.sync(%418, %552, %568) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %601 = nvgpu.mma.sync(%422, %440, %569) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %602 = nvgpu.mma.sync(%422, %456, %570) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %603 = nvgpu.mma.sync(%422, %472, %571) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %604 = nvgpu.mma.sync(%422, %488, %572) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %605 = nvgpu.mma.sync(%422, %504, %573) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %606 = nvgpu.mma.sync(%422, %520, %574) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %607 = nvgpu.mma.sync(%422, %536, %575) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %608 = nvgpu.mma.sync(%422, %552, %576) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %609 = nvgpu.mma.sync(%426, %440, %577) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %610 = nvgpu.mma.sync(%426, %456, %578) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %611 = nvgpu.mma.sync(%426, %472, %579) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %612 = nvgpu.mma.sync(%426, %488, %580) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %613 = nvgpu.mma.sync(%426, %504, %581) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %614 = nvgpu.mma.sync(%426, %520, %582) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %615 = nvgpu.mma.sync(%426, %536, %583) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %616 = nvgpu.mma.sync(%426, %552, %584) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %617 = nvgpu.mma.sync(%430, %440, %585) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %618 = nvgpu.mma.sync(%430, %456, %586) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %619 = nvgpu.mma.sync(%430, %472, %587) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %620 = nvgpu.mma.sync(%430, %488, %588) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %621 = nvgpu.mma.sync(%430, %504, %589) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %622 = nvgpu.mma.sync(%430, %520, %590) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %623 = nvgpu.mma.sync(%430, %536, %591) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %624 = nvgpu.mma.sync(%430, %552, %592) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %625 = nvgpu.mma.sync(%419, %444, %593) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %626 = nvgpu.mma.sync(%419, %460, %594) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %627 = nvgpu.mma.sync(%419, %476, %595) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %628 = nvgpu.mma.sync(%419, %492, %596) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %629 = nvgpu.mma.sync(%419, %508, %597) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %630 = nvgpu.mma.sync(%419, %524, %598) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %631 = nvgpu.mma.sync(%419, %540, %599) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %632 = nvgpu.mma.sync(%419, %556, %600) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %633 = nvgpu.mma.sync(%423, %444, %601) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %634 = nvgpu.mma.sync(%423, %460, %602) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %635 = nvgpu.mma.sync(%423, %476, %603) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %636 = nvgpu.mma.sync(%423, %492, %604) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %637 = nvgpu.mma.sync(%423, %508, %605) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %638 = nvgpu.mma.sync(%423, %524, %606) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %639 = nvgpu.mma.sync(%423, %540, %607) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %640 = nvgpu.mma.sync(%423, %556, %608) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %641 = nvgpu.mma.sync(%427, %444, %609) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %642 = nvgpu.mma.sync(%427, %460, %610) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %643 = nvgpu.mma.sync(%427, %476, %611) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %644 = nvgpu.mma.sync(%427, %492, %612) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %645 = nvgpu.mma.sync(%427, %508, %613) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %646 = nvgpu.mma.sync(%427, %524, %614) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %647 = nvgpu.mma.sync(%427, %540, %615) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %648 = nvgpu.mma.sync(%427, %556, %616) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %649 = nvgpu.mma.sync(%431, %444, %617) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %650 = nvgpu.mma.sync(%431, %460, %618) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %651 = nvgpu.mma.sync(%431, %476, %619) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %652 = nvgpu.mma.sync(%431, %492, %620) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %653 = nvgpu.mma.sync(%431, %508, %621) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %654 = nvgpu.mma.sync(%431, %524, %622) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %655 = nvgpu.mma.sync(%431, %540, %623) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %656 = nvgpu.mma.sync(%431, %556, %624) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %657 = nvgpu.mma.sync(%420, %448, %625) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %658 = nvgpu.mma.sync(%420, %464, %626) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %659 = nvgpu.mma.sync(%420, %480, %627) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %660 = nvgpu.mma.sync(%420, %496, %628) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %661 = nvgpu.mma.sync(%420, %512, %629) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %662 = nvgpu.mma.sync(%420, %528, %630) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %663 = nvgpu.mma.sync(%420, %544, %631) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %664 = nvgpu.mma.sync(%420, %560, %632) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %665 = nvgpu.mma.sync(%424, %448, %633) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %666 = nvgpu.mma.sync(%424, %464, %634) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %667 = nvgpu.mma.sync(%424, %480, %635) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %668 = nvgpu.mma.sync(%424, %496, %636) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %669 = nvgpu.mma.sync(%424, %512, %637) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %670 = nvgpu.mma.sync(%424, %528, %638) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %671 = nvgpu.mma.sync(%424, %544, %639) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %672 = nvgpu.mma.sync(%424, %560, %640) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %673 = nvgpu.mma.sync(%428, %448, %641) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %674 = nvgpu.mma.sync(%428, %464, %642) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %675 = nvgpu.mma.sync(%428, %480, %643) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %676 = nvgpu.mma.sync(%428, %496, %644) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %677 = nvgpu.mma.sync(%428, %512, %645) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %678 = nvgpu.mma.sync(%428, %528, %646) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %679 = nvgpu.mma.sync(%428, %544, %647) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %680 = nvgpu.mma.sync(%428, %560, %648) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %681 = nvgpu.mma.sync(%432, %448, %649) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %682 = nvgpu.mma.sync(%432, %464, %650) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %683 = nvgpu.mma.sync(%432, %480, %651) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %684 = nvgpu.mma.sync(%432, %496, %652) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %685 = nvgpu.mma.sync(%432, %512, %653) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %686 = nvgpu.mma.sync(%432, %528, %654) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %687 = nvgpu.mma.sync(%432, %544, %655) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
- %688 = nvgpu.mma.sync(%432, %560, %656) {mmaShape = [16, 8, 8], tf32Enabled} : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %561 = nvgpu.mma.sync(%417, %436, %arg1) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %562 = nvgpu.mma.sync(%417, %452, %arg2) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %563 = nvgpu.mma.sync(%417, %468, %arg3) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %564 = nvgpu.mma.sync(%417, %484, %arg4) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %565 = nvgpu.mma.sync(%417, %500, %arg5) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %566 = nvgpu.mma.sync(%417, %516, %arg6) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %567 = nvgpu.mma.sync(%417, %532, %arg7) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %568 = nvgpu.mma.sync(%417, %548, %arg8) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %569 = nvgpu.mma.sync(%421, %436, %arg9) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %570 = nvgpu.mma.sync(%421, %452, %arg10) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %571 = nvgpu.mma.sync(%421, %468, %arg11) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %572 = nvgpu.mma.sync(%421, %484, %arg12) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %573 = nvgpu.mma.sync(%421, %500, %arg13) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %574 = nvgpu.mma.sync(%421, %516, %arg14) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %575 = nvgpu.mma.sync(%421, %532, %arg15) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %576 = nvgpu.mma.sync(%421, %548, %arg16) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %577 = nvgpu.mma.sync(%425, %436, %arg17) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %578 = nvgpu.mma.sync(%425, %452, %arg18) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %579 = nvgpu.mma.sync(%425, %468, %arg19) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %580 = nvgpu.mma.sync(%425, %484, %arg20) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %581 = nvgpu.mma.sync(%425, %500, %arg21) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %582 = nvgpu.mma.sync(%425, %516, %arg22) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %583 = nvgpu.mma.sync(%425, %532, %arg23) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %584 = nvgpu.mma.sync(%425, %548, %arg24) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %585 = nvgpu.mma.sync(%429, %436, %arg25) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %586 = nvgpu.mma.sync(%429, %452, %arg26) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %587 = nvgpu.mma.sync(%429, %468, %arg27) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %588 = nvgpu.mma.sync(%429, %484, %arg28) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %589 = nvgpu.mma.sync(%429, %500, %arg29) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %590 = nvgpu.mma.sync(%429, %516, %arg30) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %591 = nvgpu.mma.sync(%429, %532, %arg31) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %592 = nvgpu.mma.sync(%429, %548, %arg32) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %593 = nvgpu.mma.sync(%418, %440, %561) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %594 = nvgpu.mma.sync(%418, %456, %562) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %595 = nvgpu.mma.sync(%418, %472, %563) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %596 = nvgpu.mma.sync(%418, %488, %564) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %597 = nvgpu.mma.sync(%418, %504, %565) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %598 = nvgpu.mma.sync(%418, %520, %566) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %599 = nvgpu.mma.sync(%418, %536, %567) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %600 = nvgpu.mma.sync(%418, %552, %568) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %601 = nvgpu.mma.sync(%422, %440, %569) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %602 = nvgpu.mma.sync(%422, %456, %570) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %603 = nvgpu.mma.sync(%422, %472, %571) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %604 = nvgpu.mma.sync(%422, %488, %572) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %605 = nvgpu.mma.sync(%422, %504, %573) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %606 = nvgpu.mma.sync(%422, %520, %574) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %607 = nvgpu.mma.sync(%422, %536, %575) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %608 = nvgpu.mma.sync(%422, %552, %576) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %609 = nvgpu.mma.sync(%426, %440, %577) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %610 = nvgpu.mma.sync(%426, %456, %578) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %611 = nvgpu.mma.sync(%426, %472, %579) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %612 = nvgpu.mma.sync(%426, %488, %580) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %613 = nvgpu.mma.sync(%426, %504, %581) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %614 = nvgpu.mma.sync(%426, %520, %582) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %615 = nvgpu.mma.sync(%426, %536, %583) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %616 = nvgpu.mma.sync(%426, %552, %584) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %617 = nvgpu.mma.sync(%430, %440, %585) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %618 = nvgpu.mma.sync(%430, %456, %586) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %619 = nvgpu.mma.sync(%430, %472, %587) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %620 = nvgpu.mma.sync(%430, %488, %588) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %621 = nvgpu.mma.sync(%430, %504, %589) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %622 = nvgpu.mma.sync(%430, %520, %590) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %623 = nvgpu.mma.sync(%430, %536, %591) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %624 = nvgpu.mma.sync(%430, %552, %592) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %625 = nvgpu.mma.sync(%419, %444, %593) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %626 = nvgpu.mma.sync(%419, %460, %594) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %627 = nvgpu.mma.sync(%419, %476, %595) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %628 = nvgpu.mma.sync(%419, %492, %596) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %629 = nvgpu.mma.sync(%419, %508, %597) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %630 = nvgpu.mma.sync(%419, %524, %598) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %631 = nvgpu.mma.sync(%419, %540, %599) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %632 = nvgpu.mma.sync(%419, %556, %600) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %633 = nvgpu.mma.sync(%423, %444, %601) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %634 = nvgpu.mma.sync(%423, %460, %602) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %635 = nvgpu.mma.sync(%423, %476, %603) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %636 = nvgpu.mma.sync(%423, %492, %604) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %637 = nvgpu.mma.sync(%423, %508, %605) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %638 = nvgpu.mma.sync(%423, %524, %606) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %639 = nvgpu.mma.sync(%423, %540, %607) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %640 = nvgpu.mma.sync(%423, %556, %608) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %641 = nvgpu.mma.sync(%427, %444, %609) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %642 = nvgpu.mma.sync(%427, %460, %610) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %643 = nvgpu.mma.sync(%427, %476, %611) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %644 = nvgpu.mma.sync(%427, %492, %612) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %645 = nvgpu.mma.sync(%427, %508, %613) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %646 = nvgpu.mma.sync(%427, %524, %614) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %647 = nvgpu.mma.sync(%427, %540, %615) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %648 = nvgpu.mma.sync(%427, %556, %616) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %649 = nvgpu.mma.sync(%431, %444, %617) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %650 = nvgpu.mma.sync(%431, %460, %618) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %651 = nvgpu.mma.sync(%431, %476, %619) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %652 = nvgpu.mma.sync(%431, %492, %620) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %653 = nvgpu.mma.sync(%431, %508, %621) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %654 = nvgpu.mma.sync(%431, %524, %622) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %655 = nvgpu.mma.sync(%431, %540, %623) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %656 = nvgpu.mma.sync(%431, %556, %624) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %657 = nvgpu.mma.sync(%420, %448, %625) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %658 = nvgpu.mma.sync(%420, %464, %626) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %659 = nvgpu.mma.sync(%420, %480, %627) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %660 = nvgpu.mma.sync(%420, %496, %628) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %661 = nvgpu.mma.sync(%420, %512, %629) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %662 = nvgpu.mma.sync(%420, %528, %630) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %663 = nvgpu.mma.sync(%420, %544, %631) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %664 = nvgpu.mma.sync(%420, %560, %632) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %665 = nvgpu.mma.sync(%424, %448, %633) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %666 = nvgpu.mma.sync(%424, %464, %634) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %667 = nvgpu.mma.sync(%424, %480, %635) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %668 = nvgpu.mma.sync(%424, %496, %636) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %669 = nvgpu.mma.sync(%424, %512, %637) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %670 = nvgpu.mma.sync(%424, %528, %638) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %671 = nvgpu.mma.sync(%424, %544, %639) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %672 = nvgpu.mma.sync(%424, %560, %640) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %673 = nvgpu.mma.sync(%428, %448, %641) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %674 = nvgpu.mma.sync(%428, %464, %642) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %675 = nvgpu.mma.sync(%428, %480, %643) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %676 = nvgpu.mma.sync(%428, %496, %644) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %677 = nvgpu.mma.sync(%428, %512, %645) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %678 = nvgpu.mma.sync(%428, %528, %646) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %679 = nvgpu.mma.sync(%428, %544, %647) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %680 = nvgpu.mma.sync(%428, %560, %648) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %681 = nvgpu.mma.sync(%432, %448, %649) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %682 = nvgpu.mma.sync(%432, %464, %650) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %683 = nvgpu.mma.sync(%432, %480, %651) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %684 = nvgpu.mma.sync(%432, %496, %652) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %685 = nvgpu.mma.sync(%432, %512, %653) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %686 = nvgpu.mma.sync(%432, %528, %654) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %687 = nvgpu.mma.sync(%432, %544, %655) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
+ %688 = nvgpu.mma.sync(%432, %560, %656) mmaShape = [16, 8, 8] tf32Enabled : (vector<4x1xf32>, vector<2x1xf32>, vector<2x2xf32>) -> vector<2x2xf32>
scf.yield %657, %658, %659, %660, %661, %662, %663, %664, %665, %666, %667, %668, %669, %670, %671, %672, %673, %674, %675, %676, %677, %678, %679, %680, %681, %682, %683, %684, %685, %686, %687, %688 : vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>, vector<2x2xf32>
}
%211 = gpu.lane_id
@@ -1328,7 +1328,7 @@
// CHECK-NV: nvgpu.device_async_create_group
// CHECK-NV-COUNT-6: nvgpu.device_async_copy
// CHECK-NV: nvgpu.device_async_create_group
-// CHECK-NV: nvgpu.device_async_wait %{{.*}} {numGroups = 1 : i32}
+// CHECK-NV: nvgpu.device_async_wait %{{.*}} numGroups = 1
// CHECK-NV: gpu.barrier memfence [#gpu.address_space<workgroup>]
// CHECK-NV-COUNT-4: nvgpu.ldmatrix
// CHECK-NV-COUNT-16: memref.load
@@ -1344,7 +1344,7 @@
// CHECK-NV-COUNT-32: nvgpu.mma.sync
// CHECK-NV-COUNT-6: nvgpu.device_async_copy
// CHECK-NV: nvgpu.device_async_create_group
-// CHECK-NV: nvgpu.device_async_wait %{{.*}} {numGroups = 1 : i32}
+// CHECK-NV: nvgpu.device_async_wait %{{.*}} numGroups = 1
// CHECK-NV: gpu.barrier memfence [#gpu.address_space<workgroup>]
// CHECK-NV-COUNT-4: nvgpu.ldmatrix
// CHECK-NV-COUNT-16: memref.load
diff --git a/compiler/src/iree/compiler/Codegen/Common/GPU/test/vector_reduction_to_gpu.mlir b/compiler/src/iree/compiler/Codegen/Common/GPU/test/vector_reduction_to_gpu.mlir
index d99a2cd..c13445e 100644
--- a/compiler/src/iree/compiler/Codegen/Common/GPU/test/vector_reduction_to_gpu.mlir
+++ b/compiler/src/iree/compiler/Codegen/Common/GPU/test/vector_reduction_to_gpu.mlir
@@ -254,7 +254,7 @@
%0 = hal.interface.binding.subspan layout(#pipeline_layout) binding(0) alignment(64) offset(%c0) : memref<128x32xf32>
%1 = hal.interface.binding.subspan layout(#pipeline_layout) binding(1) alignment(64) offset(%c0) : memref<128x32xf32>
%workgroup_id_x = hal.interface.workgroup.id[0] : index
- %alloc = memref.alloc() {alignment = 64 : i64} : memref<32xf32, #gpu.address_space<workgroup>>
+ %alloc = memref.alloc() alignment = 64 : memref<32xf32, #gpu.address_space<workgroup>>
%2 = vector.transfer_read %0[%workgroup_id_x, %c0], %cst_0 {in_bounds = [true]} : memref<128x32xf32>, vector<32xf32>
vector.transfer_write %2, %alloc[%c0] {in_bounds = [true]} : vector<32xf32>, memref<32xf32, #gpu.address_space<workgroup>>
gpu.barrier memfence [#gpu.address_space<workgroup>]
@@ -265,7 +265,7 @@
}
// CHECK-LABEL: func.func @shared_memory_copy()
-// CHECK: %[[ALLOC:.*]] = memref.alloc() {alignment = 64 : i64} : memref<32xf32, #gpu.address_space<workgroup>>
+// CHECK: %[[ALLOC:.*]] = memref.alloc() alignment = 64 : memref<32xf32, #gpu.address_space<workgroup>>
// CHECK: vector.transfer_read {{.*}} : memref<128x32xf32>, vector<1xf32>
// CHECK: vector.transfer_write {{.*}} %[[ALLOC]]{{.*}} : vector<1xf32>, memref<32xf32, #gpu.address_space<workgroup>>
// CHECK: gpu.barrier memfence [#gpu.address_space<workgroup>]
diff --git a/compiler/src/iree/compiler/Codegen/Common/test/flatten_memref_subspan.mlir b/compiler/src/iree/compiler/Codegen/Common/test/flatten_memref_subspan.mlir
index 9211486..ef34ab4 100644
--- a/compiler/src/iree/compiler/Codegen/Common/test/flatten_memref_subspan.mlir
+++ b/compiler/src/iree/compiler/Codegen/Common/test/flatten_memref_subspan.mlir
@@ -503,7 +503,7 @@
func.func @subgroup_mma_load(%i0: index, %i1: index) -> !gpu.mma_matrix<16x16xf16, "AOp"> {
%alloc = memref.alloc() : memref<32x32xf16, 3>
- %0 = gpu.subgroup_mma_load_matrix %alloc[%i0, %i1] {leadDimension = 32 : index} : memref<32x32xf16, 3> -> !gpu.mma_matrix<16x16xf16, "AOp">
+ %0 = gpu.subgroup_mma_load_matrix %alloc[%i0, %i1] leadDimension 32 : memref<32x32xf16, 3> -> !gpu.mma_matrix<16x16xf16, "AOp">
return %0 : !gpu.mma_matrix<16x16xf16, "AOp">
}
@@ -512,14 +512,14 @@
// CHECK-SAME: (%[[I0:.+]]: index, %[[I1:.+]]: index)
// CHECK: %[[ALLOC:.+]] = memref.alloc() : memref<1024xf16, 3>
// CHECK: %[[IDX:.+]] = affine.apply #[[$MAP]]()[%[[I0]], %[[I1]]]
-// CHECK: %[[LD:.+]] = gpu.subgroup_mma_load_matrix %[[ALLOC]][%[[IDX]]] {leadDimension = 32 : index} : memref<1024xf16, 3> -> !gpu.mma_matrix<16x16xf16, "AOp">
+// CHECK: %[[LD:.+]] = gpu.subgroup_mma_load_matrix %[[ALLOC]][%[[IDX]]] leadDimension 32 : memref<1024xf16, 3> -> !gpu.mma_matrix<16x16xf16, "AOp">
// CHECK: return %[[LD]]
// -----
func.func @subgroup_mma_store(%i0: index, %i1: index, %val: !gpu.mma_matrix<16x16xf16, "COp">) {
%alloc = memref.alloc() : memref<32x32xf16, 3>
- gpu.subgroup_mma_store_matrix %val, %alloc[%i0, %i1] {leadDimension = 128 : index} : !gpu.mma_matrix<16x16xf16, "COp">, memref<32x32xf16, 3>
+ gpu.subgroup_mma_store_matrix %val, %alloc[%i0, %i1] leadDimension 128 : !gpu.mma_matrix<16x16xf16, "COp">, memref<32x32xf16, 3>
return
}
@@ -528,7 +528,7 @@
// CHECK-SAME: (%[[I0:.+]]: index, %[[I1:.+]]: index, %[[VAL:.+]]: !gpu.mma_matrix<16x16xf16, "COp">) {
// CHECK: %[[ALLOC:.+]] = memref.alloc() : memref<1024xf16, 3>
// CHECK: %[[IDX:.+]] = affine.apply #[[$MAP]]()[%[[I0]], %[[I1]]]
-// CHECK: gpu.subgroup_mma_store_matrix %[[VAL]], %[[ALLOC]][%[[IDX]]] {leadDimension = 128 : index} : !gpu.mma_matrix<16x16xf16, "COp">, memref<1024xf16, 3>
+// CHECK: gpu.subgroup_mma_store_matrix %[[VAL]], %[[ALLOC]][%[[IDX]]] leadDimension 128 : !gpu.mma_matrix<16x16xf16, "COp">, memref<1024xf16, 3>
// -----
@@ -537,7 +537,7 @@
]>
func.func @subgroup_mma_load_with_offset(%offset : index, %i0: index, %i1: index) -> !gpu.mma_matrix<16x16xf16, "AOp"> {
%subspan = hal.interface.binding.subspan layout(#pipeline_layout) binding(0) offset(%offset) : memref<32x32xf16, strided<[32, 1], offset: ?>, 3>
- %0 = gpu.subgroup_mma_load_matrix %subspan[%i0, %i1] {leadDimension = 32 : index} : memref<32x32xf16, strided<[32, 1], offset: ?>, 3> -> !gpu.mma_matrix<16x16xf16, "AOp">
+ %0 = gpu.subgroup_mma_load_matrix %subspan[%i0, %i1] leadDimension 32 : memref<32x32xf16, strided<[32, 1], offset: ?>, 3> -> !gpu.mma_matrix<16x16xf16, "AOp">
return %0 : !gpu.mma_matrix<16x16xf16, "AOp">
}
@@ -549,7 +549,7 @@
// CHECK-DAG: %[[SIZE:.+]] = affine.apply #[[$MAP1]]()[%[[OFFSET]]]
// CHECK: %[[SUBSPAN:.+]] = hal.interface.binding.subspan layout({{.+}}) binding(0) offset(%[[ZERO]]) : memref<?xf16, 3>{%[[SIZE]]}
// CHECK: %[[INDEX:.+]] = affine.apply #[[$MAP2]]()[%[[OFFSET]], %[[I0]], %[[I1]]]
-// CHECK: %[[LD:.+]] = gpu.subgroup_mma_load_matrix %[[SUBSPAN]][%[[INDEX]]] {leadDimension = 32 : index}
+// CHECK: %[[LD:.+]] = gpu.subgroup_mma_load_matrix %[[SUBSPAN]][%[[INDEX]]] leadDimension 32
// CHECK: return %[[LD]]
// -----
@@ -559,7 +559,7 @@
]>
func.func @subgroup_mma_store_with_offset(%offset : index, %i0: index, %i1: index, %val: !gpu.mma_matrix<16x16xf16, "COp">) {
%subspan = hal.interface.binding.subspan layout(#pipeline_layout) binding(0) offset(%offset) : memref<32x32xf16, strided<[32, 1], offset: ?>, 3>
- gpu.subgroup_mma_store_matrix %val, %subspan[%i0, %i1] {leadDimension = 128 : index} : !gpu.mma_matrix<16x16xf16, "COp">, memref<32x32xf16, strided<[32, 1], offset: ?>, 3>
+ gpu.subgroup_mma_store_matrix %val, %subspan[%i0, %i1] leadDimension 128 : !gpu.mma_matrix<16x16xf16, "COp">, memref<32x32xf16, strided<[32, 1], offset: ?>, 3>
return
}
@@ -571,7 +571,7 @@
// CHECK-DAG: %[[SIZE:.+]] = affine.apply #[[$MAP1]]()[%[[OFFSET]]]
// CHECK: %[[SUBSPAN:.+]] = hal.interface.binding.subspan layout({{.+}}) binding(0) offset(%[[ZERO]]) : memref<?xf16, 3>{%[[SIZE]]}
// CHECK: %[[INDEX:.+]] = affine.apply #[[$MAP2]]()[%[[OFFSET]], %[[I0]], %[[I1]]]
-// CHECK: gpu.subgroup_mma_store_matrix %[[VAL]], %[[SUBSPAN]][%[[INDEX]]] {leadDimension = 128 : index}
+// CHECK: gpu.subgroup_mma_store_matrix %[[VAL]], %[[SUBSPAN]][%[[INDEX]]] leadDimension 128
// -----
diff --git a/compiler/src/iree/compiler/Codegen/Common/test/generic_vectorization_masked_configured.mlir b/compiler/src/iree/compiler/Codegen/Common/test/generic_vectorization_masked_configured.mlir
index 6db182d..b49b287 100644
--- a/compiler/src/iree/compiler/Codegen/Common/test/generic_vectorization_masked_configured.mlir
+++ b/compiler/src/iree/compiler/Codegen/Common/test/generic_vectorization_masked_configured.mlir
@@ -199,6 +199,6 @@
// CHECK: vector.create_mask {{.*}} : vector<8xi1>
// CHECK: vector.transfer_read {{.*}} : tensor<?xf32>, vector<8xf32>
// CHECK: arith.select {{.*}} : vector<8xi1>, vector<8xf32>
-// CHECK: vector.scan <add>, {{.*}} {inclusive = true, reduction_dim = 1 : i64}
+// CHECK: vector.scan <add>, {{.*}} reduction_dim = 1, inclusive = true
// CHECK: vector.transfer_write {{.*}} : vector<8x16xf32>, tensor<?x?xf32>
// CHECK: vector.transfer_write {{.*}} : vector<8xf32>, tensor<?xf32>
diff --git a/compiler/src/iree/compiler/Codegen/Common/test/hoist_unrolled_vector_extract_insert_slice.mlir b/compiler/src/iree/compiler/Codegen/Common/test/hoist_unrolled_vector_extract_insert_slice.mlir
index 5d4f2b2..931fc76 100644
--- a/compiler/src/iree/compiler/Codegen/Common/test/hoist_unrolled_vector_extract_insert_slice.mlir
+++ b/compiler/src/iree/compiler/Codegen/Common/test/hoist_unrolled_vector_extract_insert_slice.mlir
@@ -56,111 +56,111 @@
%59 = affine.apply affine_map<(d0) -> (d0 + 16)>(%6)
%60 = affine.apply affine_map<(d0) -> (d0 + 48)>(%arg0)
%61 = vector.transfer_read %1[%60, %59], %cst {in_bounds = [true, true], permutation_map = affine_map<(d0, d1) -> (d1, d0)>} : memref<2048x1024xf16>, vector<16x16xf16>
- %62 = vector.extract_strided_slice %44 {offsets = [0, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
- %63 = vector.extract_strided_slice %arg1 {offsets = [0, 0], sizes = [16, 8], strides = [1, 1]} : vector<32x32xf32> to vector<16x8xf32>
+ %62 = vector.extract_strided_slice %44 offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
+ %63 = vector.extract_strided_slice %arg1 offsets = [0, 0], sizes = [16, 8], strides = [1, 1] : vector<32x32xf32> to vector<16x8xf32>
%64 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %26, %62, %63 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %65 = vector.extract_strided_slice %44 {offsets = [8, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
- %66 = vector.extract_strided_slice %arg1 {offsets = [0, 8], sizes = [16, 8], strides = [1, 1]} : vector<32x32xf32> to vector<16x8xf32>
+ %65 = vector.extract_strided_slice %44 offsets = [8, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
+ %66 = vector.extract_strided_slice %arg1 offsets = [0, 8], sizes = [16, 8], strides = [1, 1] : vector<32x32xf32> to vector<16x8xf32>
%67 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %26, %65, %66 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %68 = vector.extract_strided_slice %52 {offsets = [0, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
- %69 = vector.extract_strided_slice %arg1 {offsets = [0, 16], sizes = [16, 8], strides = [1, 1]} : vector<32x32xf32> to vector<16x8xf32>
+ %68 = vector.extract_strided_slice %52 offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
+ %69 = vector.extract_strided_slice %arg1 offsets = [0, 16], sizes = [16, 8], strides = [1, 1] : vector<32x32xf32> to vector<16x8xf32>
%70 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %26, %68, %69 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %71 = vector.extract_strided_slice %52 {offsets = [8, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
- %72 = vector.extract_strided_slice %arg1 {offsets = [0, 24], sizes = [16, 8], strides = [1, 1]} : vector<32x32xf32> to vector<16x8xf32>
+ %71 = vector.extract_strided_slice %52 offsets = [8, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
+ %72 = vector.extract_strided_slice %arg1 offsets = [0, 24], sizes = [16, 8], strides = [1, 1] : vector<32x32xf32> to vector<16x8xf32>
%73 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %26, %71, %72 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %74 = vector.extract_strided_slice %44 {offsets = [0, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
- %75 = vector.extract_strided_slice %arg1 {offsets = [16, 0], sizes = [16, 8], strides = [1, 1]} : vector<32x32xf32> to vector<16x8xf32>
+ %74 = vector.extract_strided_slice %44 offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
+ %75 = vector.extract_strided_slice %arg1 offsets = [16, 0], sizes = [16, 8], strides = [1, 1] : vector<32x32xf32> to vector<16x8xf32>
%76 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %34, %74, %75 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %77 = vector.extract_strided_slice %44 {offsets = [8, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
- %78 = vector.extract_strided_slice %arg1 {offsets = [16, 8], sizes = [16, 8], strides = [1, 1]} : vector<32x32xf32> to vector<16x8xf32>
+ %77 = vector.extract_strided_slice %44 offsets = [8, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
+ %78 = vector.extract_strided_slice %arg1 offsets = [16, 8], sizes = [16, 8], strides = [1, 1] : vector<32x32xf32> to vector<16x8xf32>
%79 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %34, %77, %78 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %80 = vector.extract_strided_slice %52 {offsets = [0, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
- %81 = vector.extract_strided_slice %arg1 {offsets = [16, 16], sizes = [16, 8], strides = [1, 1]} : vector<32x32xf32> to vector<16x8xf32>
+ %80 = vector.extract_strided_slice %52 offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
+ %81 = vector.extract_strided_slice %arg1 offsets = [16, 16], sizes = [16, 8], strides = [1, 1] : vector<32x32xf32> to vector<16x8xf32>
%82 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %34, %80, %81 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %83 = vector.extract_strided_slice %52 {offsets = [8, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
- %84 = vector.extract_strided_slice %arg1 {offsets = [16, 24], sizes = [16, 8], strides = [1, 1]} : vector<32x32xf32> to vector<16x8xf32>
+ %83 = vector.extract_strided_slice %52 offsets = [8, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
+ %84 = vector.extract_strided_slice %arg1 offsets = [16, 24], sizes = [16, 8], strides = [1, 1] : vector<32x32xf32> to vector<16x8xf32>
%85 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %34, %83, %84 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %86 = vector.extract_strided_slice %46 {offsets = [0, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %86 = vector.extract_strided_slice %46 offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%87 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %28, %86, %64 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %88 = vector.extract_strided_slice %46 {offsets = [8, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %88 = vector.extract_strided_slice %46 offsets = [8, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%89 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %28, %88, %67 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %90 = vector.extract_strided_slice %55 {offsets = [0, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %90 = vector.extract_strided_slice %55 offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%91 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %28, %90, %70 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %92 = vector.extract_strided_slice %55 {offsets = [8, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %92 = vector.extract_strided_slice %55 offsets = [8, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%93 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %28, %92, %73 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %94 = vector.extract_strided_slice %46 {offsets = [0, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %94 = vector.extract_strided_slice %46 offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%95 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %37, %94, %76 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %96 = vector.extract_strided_slice %46 {offsets = [8, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %96 = vector.extract_strided_slice %46 offsets = [8, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%97 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %37, %96, %79 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %98 = vector.extract_strided_slice %55 {offsets = [0, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %98 = vector.extract_strided_slice %55 offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%99 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %37, %98, %82 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %100 = vector.extract_strided_slice %55 {offsets = [8, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %100 = vector.extract_strided_slice %55 offsets = [8, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%101 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %37, %100, %85 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %102 = vector.extract_strided_slice %48 {offsets = [0, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %102 = vector.extract_strided_slice %48 offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%103 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %30, %102, %87 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %104 = vector.extract_strided_slice %48 {offsets = [8, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %104 = vector.extract_strided_slice %48 offsets = [8, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%105 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %30, %104, %89 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %106 = vector.extract_strided_slice %58 {offsets = [0, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %106 = vector.extract_strided_slice %58 offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%107 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %30, %106, %91 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %108 = vector.extract_strided_slice %58 {offsets = [8, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %108 = vector.extract_strided_slice %58 offsets = [8, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%109 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %30, %108, %93 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %110 = vector.extract_strided_slice %48 {offsets = [0, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %110 = vector.extract_strided_slice %48 offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%111 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %40, %110, %95 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %112 = vector.extract_strided_slice %48 {offsets = [8, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %112 = vector.extract_strided_slice %48 offsets = [8, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%113 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %40, %112, %97 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %114 = vector.extract_strided_slice %58 {offsets = [0, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %114 = vector.extract_strided_slice %58 offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%115 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %40, %114, %99 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %116 = vector.extract_strided_slice %58 {offsets = [8, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %116 = vector.extract_strided_slice %58 offsets = [8, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%117 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %40, %116, %101 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %118 = vector.extract_strided_slice %50 {offsets = [0, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %118 = vector.extract_strided_slice %50 offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%119 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %32, %118, %103 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %120 = vector.extract_strided_slice %50 {offsets = [8, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %120 = vector.extract_strided_slice %50 offsets = [8, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%121 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %32, %120, %105 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %122 = vector.extract_strided_slice %61 {offsets = [0, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %122 = vector.extract_strided_slice %61 offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%123 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %32, %122, %107 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %124 = vector.extract_strided_slice %61 {offsets = [8, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %124 = vector.extract_strided_slice %61 offsets = [8, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%125 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %32, %124, %109 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %126 = vector.extract_strided_slice %50 {offsets = [0, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %126 = vector.extract_strided_slice %50 offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%127 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %43, %126, %111 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %128 = vector.extract_strided_slice %50 {offsets = [8, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %128 = vector.extract_strided_slice %50 offsets = [8, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%129 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %43, %128, %113 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %130 = vector.extract_strided_slice %61 {offsets = [0, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %130 = vector.extract_strided_slice %61 offsets = [0, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%131 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %43, %130, %115 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %132 = vector.extract_strided_slice %61 {offsets = [8, 0], sizes = [8, 16], strides = [1, 1]} : vector<16x16xf16> to vector<8x16xf16>
+ %132 = vector.extract_strided_slice %61 offsets = [8, 0], sizes = [8, 16], strides = [1, 1] : vector<16x16xf16> to vector<8x16xf16>
%133 = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %43, %132, %117 : vector<16x16xf16>, vector<8x16xf16> into vector<16x8xf32>
- %134 = vector.insert_strided_slice %119, %cst_0 {offsets = [0, 0], strides = [1, 1]} : vector<16x8xf32> into vector<32x32xf32>
- %135 = vector.insert_strided_slice %121, %134 {offsets = [0, 8], strides = [1, 1]} : vector<16x8xf32> into vector<32x32xf32>
- %136 = vector.insert_strided_slice %123, %135 {offsets = [0, 16], strides = [1, 1]} : vector<16x8xf32> into vector<32x32xf32>
- %137 = vector.insert_strided_slice %125, %136 {offsets = [0, 24], strides = [1, 1]} : vector<16x8xf32> into vector<32x32xf32>
- %138 = vector.insert_strided_slice %127, %137 {offsets = [16, 0], strides = [1, 1]} : vector<16x8xf32> into vector<32x32xf32>
- %139 = vector.insert_strided_slice %129, %138 {offsets = [16, 8], strides = [1, 1]} : vector<16x8xf32> into vector<32x32xf32>
- %140 = vector.insert_strided_slice %131, %139 {offsets = [16, 16], strides = [1, 1]} : vector<16x8xf32> into vector<32x32xf32>
- %141 = vector.insert_strided_slice %133, %140 {offsets = [16, 24], strides = [1, 1]} : vector<16x8xf32> into vector<32x32xf32>
+ %134 = vector.insert_strided_slice %119, %cst_0 offsets = [0, 0], strides = [1, 1] : vector<16x8xf32> into vector<32x32xf32>
+ %135 = vector.insert_strided_slice %121, %134 offsets = [0, 8], strides = [1, 1] : vector<16x8xf32> into vector<32x32xf32>
+ %136 = vector.insert_strided_slice %123, %135 offsets = [0, 16], strides = [1, 1] : vector<16x8xf32> into vector<32x32xf32>
+ %137 = vector.insert_strided_slice %125, %136 offsets = [0, 24], strides = [1, 1] : vector<16x8xf32> into vector<32x32xf32>
+ %138 = vector.insert_strided_slice %127, %137 offsets = [16, 0], strides = [1, 1] : vector<16x8xf32> into vector<32x32xf32>
+ %139 = vector.insert_strided_slice %129, %138 offsets = [16, 8], strides = [1, 1] : vector<16x8xf32> into vector<32x32xf32>
+ %140 = vector.insert_strided_slice %131, %139 offsets = [16, 16], strides = [1, 1] : vector<16x8xf32> into vector<32x32xf32>
+ %141 = vector.insert_strided_slice %133, %140 offsets = [16, 24], strides = [1, 1] : vector<16x8xf32> into vector<32x32xf32>
scf.yield %141 : vector<32x32xf32>
}
- %8 = vector.extract_strided_slice %7 {offsets = [0, 0], sizes = [16, 8], strides = [1, 1]} : vector<32x32xf32> to vector<16x8xf32>
+ %8 = vector.extract_strided_slice %7 offsets = [0, 0], sizes = [16, 8], strides = [1, 1] : vector<32x32xf32> to vector<16x8xf32>
vector.transfer_write %8, %2[%5, %6] {in_bounds = [true, true]} : vector<16x8xf32>, memref<3456x1024xf32>
- %9 = vector.extract_strided_slice %7 {offsets = [0, 8], sizes = [16, 8], strides = [1, 1]} : vector<32x32xf32> to vector<16x8xf32>
+ %9 = vector.extract_strided_slice %7 offsets = [0, 8], sizes = [16, 8], strides = [1, 1] : vector<32x32xf32> to vector<16x8xf32>
%10 = affine.apply affine_map<(d0) -> (d0 + 8)>(%6)
vector.transfer_write %9, %2[%5, %10] {in_bounds = [true, true]} : vector<16x8xf32>, memref<3456x1024xf32>
- %11 = vector.extract_strided_slice %7 {offsets = [0, 16], sizes = [16, 8], strides = [1, 1]} : vector<32x32xf32> to vector<16x8xf32>
+ %11 = vector.extract_strided_slice %7 offsets = [0, 16], sizes = [16, 8], strides = [1, 1] : vector<32x32xf32> to vector<16x8xf32>
%12 = affine.apply affine_map<(d0) -> (d0 + 16)>(%6)
vector.transfer_write %11, %2[%5, %12] {in_bounds = [true, true]} : vector<16x8xf32>, memref<3456x1024xf32>
- %13 = vector.extract_strided_slice %7 {offsets = [0, 24], sizes = [16, 8], strides = [1, 1]} : vector<32x32xf32> to vector<16x8xf32>
+ %13 = vector.extract_strided_slice %7 offsets = [0, 24], sizes = [16, 8], strides = [1, 1] : vector<32x32xf32> to vector<16x8xf32>
%14 = affine.apply affine_map<(d0) -> (d0 + 24)>(%6)
vector.transfer_write %13, %2[%5, %14] {in_bounds = [true, true]} : vector<16x8xf32>, memref<3456x1024xf32>
- %15 = vector.extract_strided_slice %7 {offsets = [16, 0], sizes = [16, 8], strides = [1, 1]} : vector<32x32xf32> to vector<16x8xf32>
+ %15 = vector.extract_strided_slice %7 offsets = [16, 0], sizes = [16, 8], strides = [1, 1] : vector<32x32xf32> to vector<16x8xf32>
%16 = affine.apply affine_map<(d0) -> (d0 + 16)>(%5)
vector.transfer_write %15, %2[%16, %6] {in_bounds = [true, true]} : vector<16x8xf32>, memref<3456x1024xf32>
- %17 = vector.extract_strided_slice %7 {offsets = [16, 8], sizes = [16, 8], strides = [1, 1]} : vector<32x32xf32> to vector<16x8xf32>
+ %17 = vector.extract_strided_slice %7 offsets = [16, 8], sizes = [16, 8], strides = [1, 1] : vector<32x32xf32> to vector<16x8xf32>
%18 = affine.apply affine_map<(d0) -> (d0 + 16)>(%5)
%19 = affine.apply affine_map<(d0) -> (d0 + 8)>(%6)
vector.transfer_write %17, %2[%18, %19] {in_bounds = [true, true]} : vector<16x8xf32>, memref<3456x1024xf32>
- %20 = vector.extract_strided_slice %7 {offsets = [16, 16], sizes = [16, 8], strides = [1, 1]} : vector<32x32xf32> to vector<16x8xf32>
+ %20 = vector.extract_strided_slice %7 offsets = [16, 16], sizes = [16, 8], strides = [1, 1] : vector<32x32xf32> to vector<16x8xf32>
%21 = affine.apply affine_map<(d0) -> (d0 + 16)>(%5)
%22 = affine.apply affine_map<(d0) -> (d0 + 16)>(%6)
vector.transfer_write %20, %2[%21, %22] {in_bounds = [true, true]} : vector<16x8xf32>, memref<3456x1024xf32>
- %23 = vector.extract_strided_slice %7 {offsets = [16, 24], sizes = [16, 8], strides = [1, 1]} : vector<32x32xf32> to vector<16x8xf32>
+ %23 = vector.extract_strided_slice %7 offsets = [16, 24], sizes = [16, 8], strides = [1, 1] : vector<32x32xf32> to vector<16x8xf32>
%24 = affine.apply affine_map<(d0) -> (d0 + 16)>(%5)
%25 = affine.apply affine_map<(d0) -> (d0 + 24)>(%6)
vector.transfer_write %23, %2[%24, %25] {in_bounds = [true, true]} : vector<16x8xf32>, memref<3456x1024xf32>
diff --git a/compiler/src/iree/compiler/Codegen/Common/test/resolve_swizzle_hints.mlir b/compiler/src/iree/compiler/Codegen/Common/test/resolve_swizzle_hints.mlir
index 000802b..d833f6b 100644
--- a/compiler/src/iree/compiler/Codegen/Common/test/resolve_swizzle_hints.mlir
+++ b/compiler/src/iree/compiler/Codegen/Common/test/resolve_swizzle_hints.mlir
@@ -91,8 +91,8 @@
%0 = iree_codegen.swizzle_hint %src[#iree_codegen.rotate_rows<64, 4>] : memref<?xf32>
%offset = arith.constant 60 : index
%1 = vector.load %0[%offset] : memref<?xf32>, vector<8xf32>
- %2 = vector.extract_strided_slice %1 {offsets = [0], sizes = [4], strides = [1]} : vector<8xf32> to vector<4xf32>
- %3 = vector.extract_strided_slice %1 {offsets = [4], sizes = [4], strides = [1]} : vector<8xf32> to vector<4xf32>
+ %2 = vector.extract_strided_slice %1 offsets = [0], sizes = [4], strides = [1] : vector<8xf32> to vector<4xf32>
+ %3 = vector.extract_strided_slice %1 offsets = [4], sizes = [4], strides = [1] : vector<8xf32> to vector<4xf32>
return %2, %3 : vector<4xf32>, vector<4xf32>
}
@@ -110,8 +110,8 @@
%0 = iree_codegen.swizzle_hint %dst[#iree_codegen.rotate_rows<64, 4>] : memref<?xf32>
%offset = arith.constant 60 : index
%cst = arith.constant dense<0.0> : vector<8xf32>
- %1 = vector.insert_strided_slice %src0, %cst {offsets = [0], strides = [1]} : vector<4xf32> into vector<8xf32>
- %2 = vector.insert_strided_slice %src1, %1 {offsets = [4], strides = [1]} : vector<4xf32> into vector<8xf32>
+ %1 = vector.insert_strided_slice %src0, %cst offsets = [0], strides = [1] : vector<4xf32> into vector<8xf32>
+ %2 = vector.insert_strided_slice %src1, %1 offsets = [4], strides = [1] : vector<4xf32> into vector<8xf32>
vector.store %2, %0[%offset] : memref<?xf32>, vector<8xf32>
return
}
diff --git a/compiler/src/iree/compiler/Codegen/Common/test/transform_buffer_opt.mlir b/compiler/src/iree/compiler/Codegen/Common/test/transform_buffer_opt.mlir
index 003a5f2..69d5b06 100644
--- a/compiler/src/iree/compiler/Codegen/Common/test/transform_buffer_opt.mlir
+++ b/compiler/src/iree/compiler/Codegen/Common/test/transform_buffer_opt.mlir
@@ -9,7 +9,7 @@
func.func @store_to_load(%arg: vector<4xf32>) -> vector<4xf32> {
%c0 = arith.constant 0 : index
%cst_1 = arith.constant 0.000000e+00 : f32
- %alloc = memref.alloc() {alignment = 64 : i64} : memref<64xf32>
+ %alloc = memref.alloc() alignment = 64 : memref<64xf32>
vector.transfer_write %arg, %alloc[%c0] {in_bounds = [true]} : vector<4xf32>, memref<64xf32>
%r = vector.transfer_read %alloc[%c0], %cst_1 {in_bounds = [true]} : memref<64xf32>, vector<4xf32>
return %r : vector<4xf32>
diff --git a/compiler/src/iree/compiler/Codegen/Common/test/vector_layout_analysis.mlir b/compiler/src/iree/compiler/Codegen/Common/test/vector_layout_analysis.mlir
index 1a94f5c..be038f1 100644
--- a/compiler/src/iree/compiler/Codegen/Common/test/vector_layout_analysis.mlir
+++ b/compiler/src/iree/compiler/Codegen/Common/test/vector_layout_analysis.mlir
@@ -1080,7 +1080,7 @@
%srcl = iree_vector_ext.to_layout %src to layout(#layout_scan_fwd_src) : vector<16x16xf16>
// expected-remark @below {{layout of result #0 is #iree_vector_ext.nested_layout<subgroup_tile = [1, 1], batch_tile = [2, 1], outer_tile = [1, 1], thread_tile = [1, 1], element_tile = [8, 16], subgroup_strides = [0, 0], thread_strides = [0, 0]>}}
// expected-remark @below {{layout of result #1 is #iree_vector_ext.nested_layout<subgroup_tile = [1], batch_tile = [1], outer_tile = [1], thread_tile = [1], element_tile = [16], subgroup_strides = [0], thread_strides = [0]>}}
- %out:2 = vector.scan <add>, %srcl, %init {inclusive = true, reduction_dim = 0 : i64}
+ %out:2 = vector.scan <add>, %srcl, %init reduction_dim = 0, inclusive = true
: vector<16x16xf16>, vector<16xf16>
func.return %out#0, %out#1 : vector<16x16xf16>, vector<16xf16>
}
@@ -1112,7 +1112,7 @@
%init = vector.transfer_read %arr_init[%c0], %cst_0 {in_bounds = [true]} : memref<16xf16>, vector<16xf16>
// expected-remark @above {{layout of result #0 is #iree_vector_ext.nested_layout<subgroup_tile = [1], batch_tile = [1], outer_tile = [1], thread_tile = [1], element_tile = [16], subgroup_strides = [0], thread_strides = [0]>}}
// expected-remark @below {{layout of result #0 is #iree_vector_ext.nested_layout<subgroup_tile = [1, 1], batch_tile = [2, 1], outer_tile = [1, 1], thread_tile = [1, 1], element_tile = [8, 16], subgroup_strides = [0, 0], thread_strides = [0, 0]>}}
- %out:2 = vector.scan <add>, %src, %init {inclusive = false, reduction_dim = 0 : i64}
+ %out:2 = vector.scan <add>, %src, %init reduction_dim = 0, inclusive = false
: vector<16x16xf16>, vector<16xf16>
%destl = iree_vector_ext.to_layout %out#0 to layout(#layout_scan_bwd) : vector<16x16xf16>
func.return %destl, %out#1 : vector<16x16xf16>, vector<16xf16>
diff --git a/compiler/src/iree/compiler/Codegen/Common/test/vectorize_tensor_pad.mlir b/compiler/src/iree/compiler/Codegen/Common/test/vectorize_tensor_pad.mlir
index 5e87400..db32e9d 100644
--- a/compiler/src/iree/compiler/Codegen/Common/test/vectorize_tensor_pad.mlir
+++ b/compiler/src/iree/compiler/Codegen/Common/test/vectorize_tensor_pad.mlir
@@ -43,7 +43,7 @@
// CHECK: } else {
// CHECK: scf.yield %[[V3F0]] : vector<3xf32>
// CHECK: }
-// CHECK: %[[INSERT0:.+]] = vector.insert_strided_slice %[[IF0]], %[[FULL]] {offsets = [0, 0, 0], strides = [1]} : vector<3xf32> into vector<2x2x3xf32>
+// CHECK: %[[INSERT0:.+]] = vector.insert_strided_slice %[[IF0]], %[[FULL]] offsets = [0, 0, 0], strides = [1] : vector<3xf32> into vector<2x2x3xf32>
// CHECK: %[[LE:.+]] = arith.cmpi sle, %[[LOW2]], %[[I1]]
// CHECK: %[[GT:.+]] = arith.cmpi sgt, %[[UB2]], %[[I1]]
@@ -56,7 +56,7 @@
// CHECK: } else {
// CHECK: scf.yield %[[V3F0]] : vector<3xf32>
// CHECK: }
-// CHECK: %[[INSERT1:.+]] = vector.insert_strided_slice %[[IF1]], %[[INSERT0]] {offsets = [0, 1, 0], strides = [1]} : vector<3xf32> into vector<2x2x3xf32>
+// CHECK: %[[INSERT1:.+]] = vector.insert_strided_slice %[[IF1]], %[[INSERT0]] offsets = [0, 1, 0], strides = [1] : vector<3xf32> into vector<2x2x3xf32>
// CHECK: %[[LE:.+]] = arith.cmpi sle, %[[LOW1]], %[[I1]]
// CHECK: %[[GT:.+]] = arith.cmpi sgt, %[[UB1]], %[[I1]]
@@ -69,7 +69,7 @@
// CHECK: } else {
// CHECK: scf.yield %[[V3F0]] : vector<3xf32>
// CHECK: }
-// CHECK: %[[INSERT2:.+]] = vector.insert_strided_slice %[[IF2]], %[[INSERT1]] {offsets = [1, 0, 0], strides = [1]} : vector<3xf32> into vector<2x2x3xf32>
+// CHECK: %[[INSERT2:.+]] = vector.insert_strided_slice %[[IF2]], %[[INSERT1]] offsets = [1, 0, 0], strides = [1] : vector<3xf32> into vector<2x2x3xf32>
// CHECK: %[[AND3:.+]] = arith.andi %[[DIM1INDEX1INBOUND]], %[[DIM2INDEX1INBOUND]]
// CHECK: %[[IF3:.+]] = scf.if %[[AND3]] -> (vector<3xf32>) {
@@ -78,7 +78,7 @@
// CHECK: } else {
// CHECK: scf.yield %[[V3F0]] : vector<3xf32>
// CHECK: }
-// CHECK: %[[INSERT3:.+]] = vector.insert_strided_slice %[[IF3]], %[[INSERT2]] {offsets = [1, 1, 0], strides = [1]} : vector<3xf32> into vector<2x2x3xf32>
+// CHECK: %[[INSERT3:.+]] = vector.insert_strided_slice %[[IF3]], %[[INSERT2]] offsets = [1, 1, 0], strides = [1] : vector<3xf32> into vector<2x2x3xf32>
// CHECK: %[[INIT:.+]] = tensor.empty() : tensor<1x2x2x3xf32>
// CHECK: %[[WRITE:.+]] = vector.transfer_write %[[INSERT3]], %[[INIT]][%[[I0]], %[[I0]], %[[I0]], %[[I0]]] {in_bounds = [true, true, true]} : vector<2x2x3xf32>, tensor<1x2x2x3xf32>
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/GPU/ExternalInterfaces/test/gpu_scope_alloc.mlir b/compiler/src/iree/compiler/Codegen/Dialect/GPU/ExternalInterfaces/test/gpu_scope_alloc.mlir
index c72c77a..a2c6ac7 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/GPU/ExternalInterfaces/test/gpu_scope_alloc.mlir
+++ b/compiler/src/iree/compiler/Codegen/Dialect/GPU/ExternalInterfaces/test/gpu_scope_alloc.mlir
@@ -18,7 +18,7 @@
// CHECK-SAME: %[[D0:[A-Za-z0-9_]+]]: index
// CHECK: pcf.generic scope(#iree_gpu.subgroup_scope)
// CHECK-NEXT: execute[{{.*}}] {
-// CHECK-NEXT: %[[ALLOC:.+]] = memref.alloc(%[[D0]]) {alignment = 16 : i64} : memref<?x8xi32, #gpu.address_space<workgroup>>
+// CHECK-NEXT: %[[ALLOC:.+]] = memref.alloc(%[[D0]]) alignment = 16 : memref<?x8xi32, #gpu.address_space<workgroup>>
// CHECK-NEXT: util.optimization_barrier %[[ALLOC]]
// CHECK-NEXT: pcf.return
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/GPU/TransformExtensions/test/lower_inner_tiled.mlir b/compiler/src/iree/compiler/Codegen/Dialect/GPU/TransformExtensions/test/lower_inner_tiled.mlir
index a80c5de..07a8ae5 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/GPU/TransformExtensions/test/lower_inner_tiled.mlir
+++ b/compiler/src/iree/compiler/Codegen/Dialect/GPU/TransformExtensions/test/lower_inner_tiled.mlir
@@ -132,11 +132,11 @@
// CHECK-SAME: %[[LHS:[A-Za-z0-9]+]]: vector<8xf16>
// CHECK-SAME: %[[RHS:[A-Za-z0-9]+]]: vector<8xf16>
// CHECK-SAME: %[[ACC:[A-Za-z0-9]+]]: vector<4xf32>
-// CHECK: %[[LHS0:.*]] = vector.extract_strided_slice %[[LHS]] {offsets = [0], sizes = [4], strides = [1]} : vector<8xf16> to vector<4xf16>
-// CHECK: %[[RHS0:.*]] = vector.extract_strided_slice %[[RHS]] {offsets = [0], sizes = [4], strides = [1]} : vector<8xf16> to vector<4xf16>
+// CHECK: %[[LHS0:.*]] = vector.extract_strided_slice %[[LHS]] offsets = [0], sizes = [4], strides = [1] : vector<8xf16> to vector<4xf16>
+// CHECK: %[[RHS0:.*]] = vector.extract_strided_slice %[[RHS]] offsets = [0], sizes = [4], strides = [1] : vector<8xf16> to vector<4xf16>
// CHECK: %[[ACC0:.*]] = amdgpu.mfma 16x16x16 %[[RHS0]] * %[[LHS0]] + %[[ACC]]
-// CHECK: %[[LHS1:.*]] = vector.extract_strided_slice %[[LHS]] {offsets = [4], sizes = [4], strides = [1]} : vector<8xf16> to vector<4xf16>
-// CHECK: %[[RHS1:.*]] = vector.extract_strided_slice %[[RHS]] {offsets = [4], sizes = [4], strides = [1]} : vector<8xf16> to vector<4xf16>
+// CHECK: %[[LHS1:.*]] = vector.extract_strided_slice %[[LHS]] offsets = [4], sizes = [4], strides = [1] : vector<8xf16> to vector<4xf16>
+// CHECK: %[[RHS1:.*]] = vector.extract_strided_slice %[[RHS]] offsets = [4], sizes = [4], strides = [1] : vector<8xf16> to vector<4xf16>
// CHECK: %[[ACC1:.*]] = amdgpu.mfma 16x16x16 %[[RHS1]] * %[[LHS1]] + %[[ACC0]]
// CHECK: return %[[ACC1]] : vector<4xf32>
@@ -671,10 +671,10 @@
// CHECK: %[[LOW_BIT:.+]] = arith.andi %[[LANE_ID]]
// CHECK: %[[IS_ODD:.+]] = arith.cmpi ne, %[[LOW_BIT]]
// CHECK: %[[SPARSE_IDX:.+]] = arith.select %[[IS_ODD]]
-// CHECK: %[[A_LO:.+]] = vector.extract_strided_slice %[[A]] {offsets = [0], sizes = [4], strides = [1]} : vector<8xf16> to vector<4xf16>
+// CHECK: %[[A_LO:.+]] = vector.extract_strided_slice %[[A]] offsets = [0], sizes = [4], strides = [1] : vector<8xf16> to vector<4xf16>
// CHECK: %[[B_INTLV_0:.+]] = vector.shuffle %[[B]], %[[B]] [0, 1, 8, 9, 2, 3, 10, 11] : vector<16xf16>, vector<16xf16>
// CHECK: %[[SMFMAC_0:.+]] = amdgpu.sparse_mfma 16x16x32 %[[A_LO]] * %[[B_INTLV_0]] + %[[ACC_EXPAND]] sparse(%[[SPARSE_IDX]]
-// CHECK: %[[A_HI:.+]] = vector.extract_strided_slice %[[A]] {offsets = [4], sizes = [4], strides = [1]} : vector<8xf16> to vector<4xf16>
+// CHECK: %[[A_HI:.+]] = vector.extract_strided_slice %[[A]] offsets = [4], sizes = [4], strides = [1] : vector<8xf16> to vector<4xf16>
// CHECK: %[[B_INTLV_1:.+]] = vector.shuffle %[[B]], %[[B]] [4, 5, 12, 13, 6, 7, 14, 15] : vector<16xf16>, vector<16xf16>
// CHECK: %[[SMFMAC_1:.+]] = amdgpu.sparse_mfma 16x16x32 %[[A_HI]] * %[[B_INTLV_1]] + %[[SMFMAC_0]] sparse(%[[SPARSE_IDX]]
// CHECK: %[[ACC_COLLAPSE:.+]] = util.hoistable_conversion "vdmfma_deinterleave_acc" inverts("vdmfma_interleave_acc")
@@ -695,10 +695,10 @@
// CHECK: %[[LOW_BIT:.+]] = arith.andi %[[LANE_ID]]
// CHECK: %[[IS_ODD:.+]] = arith.cmpi ne, %[[LOW_BIT]]
// CHECK: %[[SPARSE_IDX:.+]] = arith.select %[[IS_ODD]]
-// CHECK: %[[A_LO:.+]] = vector.extract_strided_slice %[[A]] {offsets = [0], sizes = [4], strides = [1]} : vector<8xbf16> to vector<4xbf16>
+// CHECK: %[[A_LO:.+]] = vector.extract_strided_slice %[[A]] offsets = [0], sizes = [4], strides = [1] : vector<8xbf16> to vector<4xbf16>
// CHECK: %[[B_INTLV_0:.+]] = vector.shuffle %[[B]], %[[B]] [0, 1, 8, 9, 2, 3, 10, 11] : vector<16xbf16>, vector<16xbf16>
// CHECK: %[[SMFMAC_0:.+]] = amdgpu.sparse_mfma 16x16x32 %[[A_LO]] * %[[B_INTLV_0]] + %[[ACC_EXPAND]] sparse(%[[SPARSE_IDX]]
-// CHECK: %[[A_HI:.+]] = vector.extract_strided_slice %[[A]] {offsets = [4], sizes = [4], strides = [1]} : vector<8xbf16> to vector<4xbf16>
+// CHECK: %[[A_HI:.+]] = vector.extract_strided_slice %[[A]] offsets = [4], sizes = [4], strides = [1] : vector<8xbf16> to vector<4xbf16>
// CHECK: %[[B_INTLV_1:.+]] = vector.shuffle %[[B]], %[[B]] [4, 5, 12, 13, 6, 7, 14, 15] : vector<16xbf16>, vector<16xbf16>
// CHECK: %[[SMFMAC_1:.+]] = amdgpu.sparse_mfma 16x16x32 %[[A_HI]] * %[[B_INTLV_1]] + %[[SMFMAC_0]] sparse(%[[SPARSE_IDX]]
// CHECK: %[[ACC_COLLAPSE:.+]] = util.hoistable_conversion "vdmfma_deinterleave_acc" inverts("vdmfma_interleave_acc")
@@ -787,10 +787,10 @@
// CHECK: %[[LOW_BIT:.+]] = arith.andi %[[LANE_ID]]
// CHECK: %[[IS_ODD:.+]] = arith.cmpi ne, %[[LOW_BIT]]
// CHECK: %[[SPARSE_IDX:.+]] = arith.select %[[IS_ODD]]
-// CHECK: %[[A_LO:.+]] = vector.extract_strided_slice %[[A]] {offsets = [0], sizes = [8], strides = [1]} : vector<16xi8> to vector<8xi8>
+// CHECK: %[[A_LO:.+]] = vector.extract_strided_slice %[[A]] offsets = [0], sizes = [8], strides = [1] : vector<16xi8> to vector<8xi8>
// CHECK: %[[B_INTLV_0:.+]] = vector.shuffle %[[B]], %[[B]] [0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23] : vector<32xi8>, vector<32xi8>
// CHECK: %[[SMFMAC_0:.+]] = amdgpu.sparse_mfma 16x16x64 %[[A_LO]] * %[[B_INTLV_0]] + %[[ACC_EXPAND]] sparse(%[[SPARSE_IDX]]
-// CHECK: %[[A_HI:.+]] = vector.extract_strided_slice %[[A]] {offsets = [8], sizes = [8], strides = [1]} : vector<16xi8> to vector<8xi8>
+// CHECK: %[[A_HI:.+]] = vector.extract_strided_slice %[[A]] offsets = [8], sizes = [8], strides = [1] : vector<16xi8> to vector<8xi8>
// CHECK: %[[B_INTLV_1:.+]] = vector.shuffle %[[B]], %[[B]] [8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31] : vector<32xi8>, vector<32xi8>
// CHECK: %[[SMFMAC_1:.+]] = amdgpu.sparse_mfma 16x16x64 %[[A_HI]] * %[[B_INTLV_1]] + %[[SMFMAC_0]] sparse(%[[SPARSE_IDX]]
// CHECK: %[[ACC_COLLAPSE:.+]] = util.hoistable_conversion "vdmfma_deinterleave_acc" inverts("vdmfma_interleave_acc")
@@ -811,10 +811,10 @@
// CHECK: %[[LOW_BIT:.+]] = arith.andi %[[LANE_ID]]
// CHECK: %[[IS_ODD:.+]] = arith.cmpi ne, %[[LOW_BIT]]
// CHECK: %[[SPARSE_IDX:.+]] = arith.select %[[IS_ODD]]
-// CHECK: %[[A_LO:.+]] = vector.extract_strided_slice %[[A]] {offsets = [0], sizes = [8], strides = [1]} : vector<16xf8E5M2FNUZ> to vector<8xf8E5M2FNUZ>
+// CHECK: %[[A_LO:.+]] = vector.extract_strided_slice %[[A]] offsets = [0], sizes = [8], strides = [1] : vector<16xf8E5M2FNUZ> to vector<8xf8E5M2FNUZ>
// CHECK: %[[B_INTLV_0:.+]] = vector.shuffle %[[B]], %[[B]] [0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23] : vector<32xf8E5M2FNUZ>, vector<32xf8E5M2FNUZ>
// CHECK: %[[SMFMAC_0:.+]] = amdgpu.sparse_mfma 16x16x64 %[[A_LO]] * %[[B_INTLV_0]] + %[[ACC_EXPAND]] sparse(%[[SPARSE_IDX]]
-// CHECK: %[[A_HI:.+]] = vector.extract_strided_slice %[[A]] {offsets = [8], sizes = [8], strides = [1]} : vector<16xf8E5M2FNUZ> to vector<8xf8E5M2FNUZ>
+// CHECK: %[[A_HI:.+]] = vector.extract_strided_slice %[[A]] offsets = [8], sizes = [8], strides = [1] : vector<16xf8E5M2FNUZ> to vector<8xf8E5M2FNUZ>
// CHECK: %[[B_INTLV_1:.+]] = vector.shuffle %[[B]], %[[B]] [8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31] : vector<32xf8E5M2FNUZ>, vector<32xf8E5M2FNUZ>
// CHECK: %[[SMFMAC_1:.+]] = amdgpu.sparse_mfma 16x16x64 %[[A_HI]] * %[[B_INTLV_1]] + %[[SMFMAC_0]] sparse(%[[SPARSE_IDX]]
// CHECK: %[[ACC_COLLAPSE:.+]] = util.hoistable_conversion "vdmfma_deinterleave_acc" inverts("vdmfma_interleave_acc")
@@ -835,10 +835,10 @@
// CHECK: %[[LOW_BIT:.+]] = arith.andi %[[LANE_ID]]
// CHECK: %[[IS_ODD:.+]] = arith.cmpi ne, %[[LOW_BIT]]
// CHECK: %[[SPARSE_IDX:.+]] = arith.select %[[IS_ODD]]
-// CHECK: %[[A_LO:.+]] = vector.extract_strided_slice %[[A]] {offsets = [0], sizes = [8], strides = [1]} : vector<16xf8E5M2FNUZ> to vector<8xf8E5M2FNUZ>
+// CHECK: %[[A_LO:.+]] = vector.extract_strided_slice %[[A]] offsets = [0], sizes = [8], strides = [1] : vector<16xf8E5M2FNUZ> to vector<8xf8E5M2FNUZ>
// CHECK: %[[B_INTLV_0:.+]] = vector.shuffle %[[B]], %[[B]] [0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23] : vector<32xf8E4M3FNUZ>, vector<32xf8E4M3FNUZ>
// CHECK: %[[SMFMAC_0:.+]] = amdgpu.sparse_mfma 16x16x64 %[[A_LO]] * %[[B_INTLV_0]] + %[[ACC_EXPAND]] sparse(%[[SPARSE_IDX]]
-// CHECK: %[[A_HI:.+]] = vector.extract_strided_slice %[[A]] {offsets = [8], sizes = [8], strides = [1]} : vector<16xf8E5M2FNUZ> to vector<8xf8E5M2FNUZ>
+// CHECK: %[[A_HI:.+]] = vector.extract_strided_slice %[[A]] offsets = [8], sizes = [8], strides = [1] : vector<16xf8E5M2FNUZ> to vector<8xf8E5M2FNUZ>
// CHECK: %[[B_INTLV_1:.+]] = vector.shuffle %[[B]], %[[B]] [8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31] : vector<32xf8E4M3FNUZ>, vector<32xf8E4M3FNUZ>
// CHECK: %[[SMFMAC_1:.+]] = amdgpu.sparse_mfma 16x16x64 %[[A_HI]] * %[[B_INTLV_1]] + %[[SMFMAC_0]] sparse(%[[SPARSE_IDX]]
// CHECK: %[[ACC_COLLAPSE:.+]] = util.hoistable_conversion "vdmfma_deinterleave_acc" inverts("vdmfma_interleave_acc")
@@ -859,10 +859,10 @@
// CHECK: %[[LOW_BIT:.+]] = arith.andi %[[LANE_ID]]
// CHECK: %[[IS_ODD:.+]] = arith.cmpi ne, %[[LOW_BIT]]
// CHECK: %[[SPARSE_IDX:.+]] = arith.select %[[IS_ODD]]
-// CHECK: %[[A_LO:.+]] = vector.extract_strided_slice %[[A]] {offsets = [0], sizes = [8], strides = [1]} : vector<16xf8E4M3FNUZ> to vector<8xf8E4M3FNUZ>
+// CHECK: %[[A_LO:.+]] = vector.extract_strided_slice %[[A]] offsets = [0], sizes = [8], strides = [1] : vector<16xf8E4M3FNUZ> to vector<8xf8E4M3FNUZ>
// CHECK: %[[B_INTLV_0:.+]] = vector.shuffle %[[B]], %[[B]] [0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23] : vector<32xf8E5M2FNUZ>, vector<32xf8E5M2FNUZ>
// CHECK: %[[SMFMAC_0:.+]] = amdgpu.sparse_mfma 16x16x64 %[[A_LO]] * %[[B_INTLV_0]] + %[[ACC_EXPAND]] sparse(%[[SPARSE_IDX]]
-// CHECK: %[[A_HI:.+]] = vector.extract_strided_slice %[[A]] {offsets = [8], sizes = [8], strides = [1]} : vector<16xf8E4M3FNUZ> to vector<8xf8E4M3FNUZ>
+// CHECK: %[[A_HI:.+]] = vector.extract_strided_slice %[[A]] offsets = [8], sizes = [8], strides = [1] : vector<16xf8E4M3FNUZ> to vector<8xf8E4M3FNUZ>
// CHECK: %[[B_INTLV_1:.+]] = vector.shuffle %[[B]], %[[B]] [8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31] : vector<32xf8E5M2FNUZ>, vector<32xf8E5M2FNUZ>
// CHECK: %[[SMFMAC_1:.+]] = amdgpu.sparse_mfma 16x16x64 %[[A_HI]] * %[[B_INTLV_1]] + %[[SMFMAC_0]] sparse(%[[SPARSE_IDX]]
// CHECK: %[[ACC_COLLAPSE:.+]] = util.hoistable_conversion "vdmfma_deinterleave_acc" inverts("vdmfma_interleave_acc")
@@ -883,10 +883,10 @@
// CHECK: %[[LOW_BIT:.+]] = arith.andi %[[LANE_ID]]
// CHECK: %[[IS_ODD:.+]] = arith.cmpi ne, %[[LOW_BIT]]
// CHECK: %[[SPARSE_IDX:.+]] = arith.select %[[IS_ODD]]
-// CHECK: %[[A_LO:.+]] = vector.extract_strided_slice %[[A]] {offsets = [0], sizes = [8], strides = [1]} : vector<16xf8E4M3FNUZ> to vector<8xf8E4M3FNUZ>
+// CHECK: %[[A_LO:.+]] = vector.extract_strided_slice %[[A]] offsets = [0], sizes = [8], strides = [1] : vector<16xf8E4M3FNUZ> to vector<8xf8E4M3FNUZ>
// CHECK: %[[B_INTLV_0:.+]] = vector.shuffle %[[B]], %[[B]] [0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23] : vector<32xf8E4M3FNUZ>, vector<32xf8E4M3FNUZ>
// CHECK: %[[SMFMAC_0:.+]] = amdgpu.sparse_mfma 16x16x64 %[[A_LO]] * %[[B_INTLV_0]] + %[[ACC_EXPAND]] sparse(%[[SPARSE_IDX]]
-// CHECK: %[[A_HI:.+]] = vector.extract_strided_slice %[[A]] {offsets = [8], sizes = [8], strides = [1]} : vector<16xf8E4M3FNUZ> to vector<8xf8E4M3FNUZ>
+// CHECK: %[[A_HI:.+]] = vector.extract_strided_slice %[[A]] offsets = [8], sizes = [8], strides = [1] : vector<16xf8E4M3FNUZ> to vector<8xf8E4M3FNUZ>
// CHECK: %[[B_INTLV_1:.+]] = vector.shuffle %[[B]], %[[B]] [8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31] : vector<32xf8E4M3FNUZ>, vector<32xf8E4M3FNUZ>
// CHECK: %[[SMFMAC_1:.+]] = amdgpu.sparse_mfma 16x16x64 %[[A_HI]] * %[[B_INTLV_1]] + %[[SMFMAC_0]] sparse(%[[SPARSE_IDX]]
// CHECK: %[[ACC_COLLAPSE:.+]] = util.hoistable_conversion "vdmfma_deinterleave_acc" inverts("vdmfma_interleave_acc")
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/GPU/TransformExtensions/test/unroll_multi_mma.mlir b/compiler/src/iree/compiler/Codegen/Dialect/GPU/TransformExtensions/test/unroll_multi_mma.mlir
index f8ca1d1..c104cba 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/GPU/TransformExtensions/test/unroll_multi_mma.mlir
+++ b/compiler/src/iree/compiler/Codegen/Dialect/GPU/TransformExtensions/test/unroll_multi_mma.mlir
@@ -32,39 +32,39 @@
// CHECK: %[[ACC_DIST:.+]]:4 = util.hoistable_conversion "unroll_acc_distribute" inverts("unroll_acc_reassemble")
// CHECK-SAME: (%[[ACC_B:.+]] = %[[ACC]])
-// CHECK: vector.extract_strided_slice %[[ACC_B]] {offsets = [0, 0]
-// CHECK: vector.extract_strided_slice %[[ACC_B]] {offsets = [0, 1]
-// CHECK: vector.extract_strided_slice %[[ACC_B]] {offsets = [1, 0]
-// CHECK: vector.extract_strided_slice %[[ACC_B]] {offsets = [1, 1]
-// CHECK: vector.extract_strided_slice %[[LHS]] {offsets = [0, 0]
-// CHECK: vector.extract_strided_slice %[[RHS]] {offsets = [0, 0]
+// CHECK: vector.extract_strided_slice %[[ACC_B]] offsets = [0, 0]
+// CHECK: vector.extract_strided_slice %[[ACC_B]] offsets = [0, 1]
+// CHECK: vector.extract_strided_slice %[[ACC_B]] offsets = [1, 0]
+// CHECK: vector.extract_strided_slice %[[ACC_B]] offsets = [1, 1]
+// CHECK: vector.extract_strided_slice %[[LHS]] offsets = [0, 0]
+// CHECK: vector.extract_strided_slice %[[RHS]] offsets = [0, 0]
// CHECK: %[[MMA0_K0:.+]] = iree_codegen.inner_tiled ins(%{{.*}}, %{{.*}}) outs(%[[ACC_DIST]]#0)
-// CHECK: vector.extract_strided_slice %[[LHS]] {offsets = [0, 0]
-// CHECK: vector.extract_strided_slice %[[RHS]] {offsets = [0, 1]
+// CHECK: vector.extract_strided_slice %[[LHS]] offsets = [0, 0]
+// CHECK: vector.extract_strided_slice %[[RHS]] offsets = [0, 1]
// CHECK: %[[MMA1_K0:.+]] = iree_codegen.inner_tiled ins(%{{.*}}, %{{.*}}) outs(%[[ACC_DIST]]#1)
-// CHECK: vector.extract_strided_slice %[[LHS]] {offsets = [1, 0]
-// CHECK: vector.extract_strided_slice %[[RHS]] {offsets = [0, 0]
+// CHECK: vector.extract_strided_slice %[[LHS]] offsets = [1, 0]
+// CHECK: vector.extract_strided_slice %[[RHS]] offsets = [0, 0]
// CHECK: %[[MMA2_K0:.+]] = iree_codegen.inner_tiled ins(%{{.*}}, %{{.*}}) outs(%[[ACC_DIST]]#2)
-// CHECK: vector.extract_strided_slice %[[LHS]] {offsets = [1, 0]
-// CHECK: vector.extract_strided_slice %[[RHS]] {offsets = [0, 1]
+// CHECK: vector.extract_strided_slice %[[LHS]] offsets = [1, 0]
+// CHECK: vector.extract_strided_slice %[[RHS]] offsets = [0, 1]
// CHECK: %[[MMA3_K0:.+]] = iree_codegen.inner_tiled ins(%{{.*}}, %{{.*}}) outs(%[[ACC_DIST]]#3)
-// CHECK: vector.extract_strided_slice %[[LHS]] {offsets = [0, 1]
-// CHECK: vector.extract_strided_slice %[[RHS]] {offsets = [1, 0]
+// CHECK: vector.extract_strided_slice %[[LHS]] offsets = [0, 1]
+// CHECK: vector.extract_strided_slice %[[RHS]] offsets = [1, 0]
// CHECK: %[[MMA0:.+]] = iree_codegen.inner_tiled ins(%{{.*}}, %{{.*}}) outs(%[[MMA0_K0]])
-// CHECK: vector.extract_strided_slice %[[LHS]] {offsets = [0, 1]
-// CHECK: vector.extract_strided_slice %[[RHS]] {offsets = [1, 1]
+// CHECK: vector.extract_strided_slice %[[LHS]] offsets = [0, 1]
+// CHECK: vector.extract_strided_slice %[[RHS]] offsets = [1, 1]
// CHECK: %[[MMA1:.+]] = iree_codegen.inner_tiled ins(%{{.*}}, %{{.*}}) outs(%[[MMA1_K0]])
-// CHECK: vector.extract_strided_slice %[[LHS]] {offsets = [1, 1]
-// CHECK: vector.extract_strided_slice %[[RHS]] {offsets = [1, 0]
+// CHECK: vector.extract_strided_slice %[[LHS]] offsets = [1, 1]
+// CHECK: vector.extract_strided_slice %[[RHS]] offsets = [1, 0]
// CHECK: %[[MMA2:.+]] = iree_codegen.inner_tiled ins(%{{.*}}, %{{.*}}) outs(%[[MMA2_K0]])
-// CHECK: vector.extract_strided_slice %[[LHS]] {offsets = [1, 1]
-// CHECK: vector.extract_strided_slice %[[RHS]] {offsets = [1, 1]
+// CHECK: vector.extract_strided_slice %[[LHS]] offsets = [1, 1]
+// CHECK: vector.extract_strided_slice %[[RHS]] offsets = [1, 1]
// CHECK: %[[MMA3:.+]] = iree_codegen.inner_tiled ins(%{{.*}}, %{{.*}}) outs(%[[MMA3_K0]])
// CHECK: %[[RES:.+]] = util.hoistable_conversion "unroll_acc_reassemble" inverts("unroll_acc_distribute")
-// CHECK: vector.insert_strided_slice %{{.+}}, %{{.+}} {offsets = [0, 0, 0]
-// CHECK: vector.insert_strided_slice %{{.+}}, %{{.+}} {offsets = [0, 1, 0]
-// CHECK: vector.insert_strided_slice %{{.+}}, %{{.+}} {offsets = [1, 0, 0]
-// CHECK: vector.insert_strided_slice %{{.+}}, %{{.+}} {offsets = [1, 1, 0]
+// CHECK: vector.insert_strided_slice %{{.+}}, %{{.+}} offsets = [0, 0, 0]
+// CHECK: vector.insert_strided_slice %{{.+}}, %{{.+}} offsets = [0, 1, 0]
+// CHECK: vector.insert_strided_slice %{{.+}}, %{{.+}} offsets = [1, 0, 0]
+// CHECK: vector.insert_strided_slice %{{.+}}, %{{.+}} offsets = [1, 1, 0]
// CHECK: return %[[RES]]
// -----
@@ -133,7 +133,7 @@
// CHECK-LABEL: func @unroll_scaled_multi_mma
// CHECK-SAME: %[[LHS_SCALE:[A-Za-z0-9]+]]: vector<1x2x1xf8E8M0FNU>
-// CHECK-COUNT-2: vector.extract_strided_slice %[[LHS_SCALE]] {offsets = [0, 0]
-// CHECK-NOT: vector.extract_strided_slice %[[LHS_SCALE]] {offsets = [0, 0]
-// CHECK-COUNT-2: vector.extract_strided_slice %[[LHS_SCALE]] {offsets = [0, 1]
+// CHECK-COUNT-2: vector.extract_strided_slice %[[LHS_SCALE]] offsets = [0, 0]
+// CHECK-NOT: vector.extract_strided_slice %[[LHS_SCALE]] offsets = [0, 0]
+// CHECK-COUNT-2: vector.extract_strided_slice %[[LHS_SCALE]] offsets = [0, 1]
// CHECK-NOT: vector.extract_strided_slice %[[LHS_SCALE]]
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/PCF/ExternalInterfaces/test/bufferize.mlir b/compiler/src/iree/compiler/Codegen/Dialect/PCF/ExternalInterfaces/test/bufferize.mlir
index 708d962..1ba7b65 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/PCF/ExternalInterfaces/test/bufferize.mlir
+++ b/compiler/src/iree/compiler/Codegen/Dialect/PCF/ExternalInterfaces/test/bufferize.mlir
@@ -19,8 +19,8 @@
// CHECK-SAME: %[[D2:[A-Za-z0-9]+]]: index
// CHECK-SAME: %[[D3:[A-Za-z0-9]+]]: index
-// CHECK-DAG: %[[ALLOC:.+]] = memref.alloc(%[[D0]]) {alignment = 64 : i64} : memref<?xi32>
-// CHECK-DAG: %[[ALLOC1:.+]] = memref.alloc(%[[D3]]) {alignment = 64 : i64} : memref<?xi32, "foo">
+// CHECK-DAG: %[[ALLOC:.+]] = memref.alloc(%[[D0]]) alignment = 64 : memref<?xi32>
+// CHECK-DAG: %[[ALLOC1:.+]] = memref.alloc(%[[D3]]) alignment = 64 : memref<?xi32, "foo">
// CHECK: pcf.generic scope(#pcf.test_scope)
// CHECK-NEXT: execute(%[[REF:[A-Za-z0-9_]+]] = %[[ALLOC]],
// CHECK-SAME: %[[REF1:[A-Za-z0-9_]+]],
@@ -74,7 +74,7 @@
// CHECK-SAME: %[[D2:[A-Za-z0-9]+]]: index
// CHECK-SAME: %[[INIT1:[A-Za-z0-9]+]]: memref<?xi32, "foo">
-// CHECK: %[[ALLOC:.+]] = memref.alloc(%[[D0]]) {alignment = 64 : i64} : memref<?xi32>
+// CHECK: %[[ALLOC:.+]] = memref.alloc(%[[D0]]) alignment = 64 : memref<?xi32>
// CHECK: pcf.generic scope(#pcf.test_scope)
// CHECK-NEXT: execute(%[[REF:[A-Za-z0-9_]+]] = %[[ALLOC]],
// CHECK-SAME: %[[REF1:[A-Za-z0-9_]+]],
@@ -110,8 +110,8 @@
// CHECK-SAME: %[[D2:[A-Za-z0-9]+]]: index
// CHECK-SAME: %[[D3:[A-Za-z0-9]+]]: index
-// CHECK-DAG: %[[ALLOC:.+]] = memref.alloc(%[[D0]]) {alignment = 64 : i64} : memref<?xi32>
-// CHECK-DAG: %[[ALLOC1:.+]] = memref.alloc(%[[D3]]) {alignment = 64 : i64} : memref<?xi32, "foo">
+// CHECK-DAG: %[[ALLOC:.+]] = memref.alloc(%[[D0]]) alignment = 64 : memref<?xi32>
+// CHECK-DAG: %[[ALLOC1:.+]] = memref.alloc(%[[D3]]) alignment = 64 : memref<?xi32, "foo">
// CHECK: pcf.loop scope(#pcf.test_scope) count
// CHECK-NEXT: execute(%[[REF:[A-Za-z0-9_]+]] = %[[ALLOC]],
// CHECK-SAME: %[[REF1:[A-Za-z0-9_]+]],
@@ -146,7 +146,7 @@
// CHECK-SAME: %[[D2:[A-Za-z0-9]+]]: index
// CHECK-SAME: %[[INIT1:[A-Za-z0-9]+]]: memref<?xi32, "foo">
-// CHECK: %[[ALLOC:.+]] = memref.alloc(%[[D0]]) {alignment = 64 : i64} : memref<?xi32>
+// CHECK: %[[ALLOC:.+]] = memref.alloc(%[[D0]]) alignment = 64 : memref<?xi32>
// CHECK: pcf.loop sync true scope(#pcf.test_scope) count
// CHECK-NEXT: execute(%[[REF:[A-Za-z0-9_]+]] = %[[ALLOC]],
// CHECK-SAME: %[[REF1:[A-Za-z0-9_]+]],
@@ -171,7 +171,7 @@
// CHECK-LABEL: @write_tensor
// CHECK-SAME: %[[DST:[A-Za-z0-9]+]]: !pcf.sref<?xi32, #pcf.test_scope>
-// CHECK: %[[SRC:.+]] = memref.alloc() {alignment = 64 : i64} : memref<2xi32>
+// CHECK: %[[SRC:.+]] = memref.alloc() alignment = 64 : memref<2xi32>
// CHECK-NEXT: pcf.write_slice %[[SRC]] into %[[DST]][1] [2] [1] : memref<2xi32> into !pcf.sref<?xi32, #pcf.test_scope>
// -----
@@ -237,7 +237,7 @@
// CHECK-LABEL: @bufferize_generic_with_initializer(
// CHECK-SAME: %[[D0:[A-Za-z0-9]+]]: index
// CHECK-SAME: %[[D1:[A-Za-z0-9]+]]: index
-// CHECK: %[[ALLOC:.+]] = memref.alloc(%[[D0]], %[[D1]]) {alignment = 64 : i64} : memref<?x?xf32>
+// CHECK: %[[ALLOC:.+]] = memref.alloc(%[[D0]], %[[D1]]) alignment = 64 : memref<?x?xf32>
// CHECK: pcf.generic scope(#pcf.test_scope) initialize {
// CHECK-NEXT: %[[C42:.+]] = arith.constant 42
// CHECK-NEXT: pcf.yield %[[C42]]
@@ -268,7 +268,7 @@
// CHECK-LABEL: @bufferize_loop_tied_result_users(
// CHECK-SAME: %[[D0:[A-Za-z0-9]+]]: index
// CHECK-SAME: %[[N:[A-Za-z0-9]+]]: index
-// CHECK: %[[INIT:.+]] = memref.alloc() {alignment = 64 : i64} : memref<4xi32>
+// CHECK: %[[INIT:.+]] = memref.alloc() alignment = 64 : memref<4xi32>
// CHECK: %[[LOOP:.+]]:2 = pcf.loop scope(#pcf.test_scope) count(%[[N]])
// CHECK-NEXT: execute(%{{.*}} = %[[INIT]], %{{.*}})[%{{.*}}: index]
// CHECK-NEXT: : (!pcf.sref<4xi32, #pcf.test_scope>,
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/PCF/Transforms/test/convert_sref_to_memref.mlir b/compiler/src/iree/compiler/Codegen/Dialect/PCF/Transforms/test/convert_sref_to_memref.mlir
index d1a9bdd..d6366b2 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/PCF/Transforms/test/convert_sref_to_memref.mlir
+++ b/compiler/src/iree/compiler/Codegen/Dialect/PCF/Transforms/test/convert_sref_to_memref.mlir
@@ -38,8 +38,8 @@
// CHECK-SAME: %[[ARG0:[A-Za-z0-9_]+]]: index
// CHECK-SAME: %[[ARG1:[A-Za-z0-9_]+]]: index
// CHECK-SAME: %[[ARG2:[A-Za-z0-9_]+]]: index
-// CHECK-DAG: %[[ALLOC:.+]] = memref.alloc(%[[ARG0]]) {alignment = 16 : i64} : memref<?xi32>
-// CHECK-DAG: %[[ALLOC1:.+]] = memref.alloc(%[[ARG1]], %[[ARG2]]) {alignment = 16 : i64} : memref<?x?xi32>
+// CHECK-DAG: %[[ALLOC:.+]] = memref.alloc(%[[ARG0]]) alignment = 16 : memref<?xi32>
+// CHECK-DAG: %[[ALLOC1:.+]] = memref.alloc(%[[ARG1]], %[[ARG2]]) alignment = 16 : memref<?x?xi32>
// CHECK: pcf.generic scope(#pcf.test_scope)
// CHECK-NEXT: execute[{{.*}}] {
// CHECK-NEXT: util.optimization_barrier %[[ALLOC]], %[[ALLOC1]]
@@ -91,7 +91,7 @@
// CHECK: pcf.generic scope(#pcf.sequential)
// CHECK-NEXT: execute[{{.*}}] {
// CHECK-NEXT: %[[I:.+]] = arith.constant 42 : index
-// CHECK-NEXT: %[[ALLOC:.+]] = memref.alloc(%[[I]]) {alignment = 16 : i64} : memref<?x5xi32>
+// CHECK-NEXT: %[[ALLOC:.+]] = memref.alloc(%[[I]]) alignment = 16 : memref<?x5xi32>
// CHECK-NEXT: util.optimization_barrier %[[I]], %[[ALLOC]]
// CHECK-NEXT: pcf.return
@@ -135,8 +135,8 @@
// CHECK-SAME: %[[ARG0:[A-Za-z0-9_]+]]: index
// CHECK-SAME: %[[ARG1:[A-Za-z0-9_]+]]: index
// CHECK-SAME: %[[ARG2:[A-Za-z0-9_]+]]: index
-// CHECK-DAG: %[[ALLOC:.+]] = memref.alloc(%[[ARG0]]) {alignment = 16 : i64} : memref<?xi32>
-// CHECK-DAG: %[[ALLOC1:.+]] = memref.alloc(%[[ARG1]], %[[ARG2]]) {alignment = 16 : i64} : memref<?x?xi32>
+// CHECK-DAG: %[[ALLOC:.+]] = memref.alloc(%[[ARG0]]) alignment = 16 : memref<?xi32>
+// CHECK-DAG: %[[ALLOC1:.+]] = memref.alloc(%[[ARG1]], %[[ARG2]]) alignment = 16 : memref<?x?xi32>
// CHECK: pcf.loop scope(#pcf.test_scope)
// CHECK-NEXT: execute[{{.*}}] {
// CHECK-NEXT: util.optimization_barrier %[[ALLOC]], %[[ALLOC1]]
@@ -286,7 +286,7 @@
// CHECK-LABEL: @convert_alloc
// CHECK-SAME: %[[D0:[A-Za-z0-9]+]]: index
-// CHECK: %[[ALLOC:.+]] = memref.alloc(%[[D0]]) {alignment = 16 : i64} : memref<?x5xi32>
+// CHECK: %[[ALLOC:.+]] = memref.alloc(%[[D0]]) alignment = 16 : memref<?x5xi32>
// CHECK: return %[[ALLOC]] : memref<?x5xi32>
// -----
@@ -413,7 +413,7 @@
// CHECK-LABEL: @convert_tensor_read_slice_no_tied_init
// CHECK-SAME: %[[DIM0:[A-Za-z0-9_]+]]: index
// CHECK-SAME: %[[DIM1:[A-Za-z0-9_]+]]: index
-// CHECK-DAG: %[[ALLOC:.+]] = memref.alloc(%[[DIM0]], %[[DIM1]]) {alignment = 16 : i64} : memref<?x?xi32>
+// CHECK-DAG: %[[ALLOC:.+]] = memref.alloc(%[[DIM0]], %[[DIM1]]) alignment = 16 : memref<?x?xi32>
// CHECK: pcf.generic
// CHECK-NEXT: execute[{{.*}}] {
// CHECK-DAG: %[[SV:.+]] = memref.subview %[[ALLOC]][1, 2] [3, 4] [1, 1] : memref<?x?xi32> to memref<3x4xi32, strided<[?, 1], offset: ?>>
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/VectorExt/Transforms/test/lower_transfer_gather_scatter_to_vector.mlir b/compiler/src/iree/compiler/Codegen/Dialect/VectorExt/Transforms/test/lower_transfer_gather_scatter_to_vector.mlir
index ae80017..1d62fa0 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/VectorExt/Transforms/test/lower_transfer_gather_scatter_to_vector.mlir
+++ b/compiler/src/iree/compiler/Codegen/Dialect/VectorExt/Transforms/test/lower_transfer_gather_scatter_to_vector.mlir
@@ -14,10 +14,10 @@
%4 = vector.step : vector<16xindex>
%5 = arith.muli %4, %cst : vector<16xindex>
%6 = iree_vector_ext.transfer_gather %arg0[%c0, %c0, %c0] [%5 : vector<16xindex>], %cst_0 {indexing_maps = [#map, #map1]} : tensor<1x1x31xf32>, vector<16xf32>
- %7 = vector.insert_strided_slice %6, %0 {offsets = [0, 0], strides = [1]} : vector<16xf32> into vector<1x16xf32>
- %8 = vector.insert_strided_slice %7, %1 {offsets = [0, 0, 0], strides = [1, 1]} : vector<1x16xf32> into vector<1x1x16xf32>
- %9 = vector.insert_strided_slice %8, %2 {offsets = [0, 0, 0, 0], strides = [1, 1, 1]} : vector<1x1x16xf32> into vector<1x1x1x16xf32>
- %10 = vector.insert_strided_slice %9, %3 {offsets = [0, 0, 0, 0, 0], strides = [1, 1, 1, 1]} : vector<1x1x1x16xf32> into vector<1x1x1x1x16xf32>
+ %7 = vector.insert_strided_slice %6, %0 offsets = [0, 0], strides = [1] : vector<16xf32> into vector<1x16xf32>
+ %8 = vector.insert_strided_slice %7, %1 offsets = [0, 0, 0], strides = [1, 1] : vector<1x16xf32> into vector<1x1x16xf32>
+ %9 = vector.insert_strided_slice %8, %2 offsets = [0, 0, 0, 0], strides = [1, 1, 1] : vector<1x1x16xf32> into vector<1x1x1x16xf32>
+ %10 = vector.insert_strided_slice %9, %3 offsets = [0, 0, 0, 0, 0], strides = [1, 1, 1, 1] : vector<1x1x1x16xf32> into vector<1x1x1x1x16xf32>
%11 = vector.transfer_write %10, %arg1[%c0, %c0, %c0, %c0, %c0] {in_bounds = [true, true, true, true, true]} : vector<1x1x1x1x16xf32>, tensor<1x1x1x1x16xf32>
return %11 : tensor<1x1x1x1x16xf32>
}
diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/test/aarch64_dotprod_vector_lowering.mlir b/compiler/src/iree/compiler/Codegen/LLVMCPU/test/aarch64_dotprod_vector_lowering.mlir
index 732b2e6..c1dea25 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMCPU/test/aarch64_dotprod_vector_lowering.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMCPU/test/aarch64_dotprod_vector_lowering.mlir
@@ -24,10 +24,10 @@
// CHECK-LABEL: @mmt4d_kernel_dispatch(
// CHECK: %[[LHS_FLAT32:.+]] = vector.transfer_read {{.*}} : memref<1x2x32xi8>, vector<32xi8>
// CHECK: %[[RHS_FLAT32:.+]] = vector.transfer_read {{.*}} : memref<1x2x32xi8>, vector<32xi8>
-// CHECK: %[[LHS_FLAT16_0:.+]] = vector.extract_strided_slice %[[LHS_FLAT32]] {offsets = [0], sizes = [16], strides = [1]} : vector<32xi8> to vector<16xi8>
-// CHECK: %[[LHS_FLAT16_1:.+]] = vector.extract_strided_slice %[[LHS_FLAT32]] {offsets = [16], sizes = [16], strides = [1]} : vector<32xi8> to vector<16xi8>
-// CHECK: %[[RHS_FLAT16_0:.+]] = vector.extract_strided_slice %[[RHS_FLAT32]] {offsets = [0], sizes = [16], strides = [1]} : vector<32xi8> to vector<16xi8>
-// CHECK: %[[RHS_FLAT16_1:.+]] = vector.extract_strided_slice %[[RHS_FLAT32]] {offsets = [16], sizes = [16], strides = [1]} : vector<32xi8> to vector<16xi8>
+// CHECK: %[[LHS_FLAT16_0:.+]] = vector.extract_strided_slice %[[LHS_FLAT32]] offsets = [0], sizes = [16], strides = [1] : vector<32xi8> to vector<16xi8>
+// CHECK: %[[LHS_FLAT16_1:.+]] = vector.extract_strided_slice %[[LHS_FLAT32]] offsets = [16], sizes = [16], strides = [1] : vector<32xi8> to vector<16xi8>
+// CHECK: %[[RHS_FLAT16_0:.+]] = vector.extract_strided_slice %[[RHS_FLAT32]] offsets = [0], sizes = [16], strides = [1] : vector<32xi8> to vector<16xi8>
+// CHECK: %[[RHS_FLAT16_1:.+]] = vector.extract_strided_slice %[[RHS_FLAT32]] offsets = [16], sizes = [16], strides = [1] : vector<32xi8> to vector<16xi8>
// CHECK: llvm.inline_asm
// CHECK-SAME: {{((.*sdot){16})}}
// CHECK-SAME: %[[LHS_FLAT16_0]], %[[LHS_FLAT16_1]], %[[RHS_FLAT16_0]], %[[RHS_FLAT16_1]],
diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/test/assign_workgroup_local_memory.mlir b/compiler/src/iree/compiler/Codegen/LLVMCPU/test/assign_workgroup_local_memory.mlir
index b4693ac..9f563c5 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMCPU/test/assign_workgroup_local_memory.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMCPU/test/assign_workgroup_local_memory.mlir
@@ -61,7 +61,7 @@
%1 = memref.alloc() : memref<4xf32, #iree_codegen.workgroup_local>
// CHECK: %[[C64:.+]] = arith.constant 64 : index
// CHECK: memref.view %[[PACKED]][%[[C64]]][] : memref<80xi8, #iree_codegen.workgroup_local> to memref<4xf32, #iree_codegen.workgroup_local>
- %2 = memref.alloc() {alignment = 64 : i64} : memref<4xf32, #iree_codegen.workgroup_local>
+ %2 = memref.alloc() alignment = 64 : memref<4xf32, #iree_codegen.workgroup_local>
return
}
// CHECK: iree_codegen.dispatch_config @dispatch workgroup_local_memory = 80
diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/test/pipeline_pad_conv_tests.mlir b/compiler/src/iree/compiler/Codegen/LLVMCPU/test/pipeline_pad_conv_tests.mlir
index 09e9ff9..6e10efc 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMCPU/test/pipeline_pad_conv_tests.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMCPU/test/pipeline_pad_conv_tests.mlir
@@ -29,5 +29,5 @@
//
// Check that the stack buffer is bounded by tiling sizes.
//
-// CHECK: memref.alloca() {alignment = 64 : i64} : memref<1x8x1x8xf32>
+// CHECK: memref.alloca() alignment = 64 : memref<1x8x1x8xf32>
// CHECK: vector.fma
diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/test/vector_contract_to_arm_asm.mlir b/compiler/src/iree/compiler/Codegen/LLVMCPU/test/vector_contract_to_arm_asm.mlir
index 26c1765..e6ef975 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMCPU/test/vector_contract_to_arm_asm.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMCPU/test/vector_contract_to_arm_asm.mlir
@@ -33,26 +33,26 @@
// CHECK-DAG: %[[LHS1D:.+]] = vector.shape_cast %[[LHS]] : vector<8x4xi8> to vector<32xi8>
// CHECK-DAG: %[[RHS1D:.+]] = vector.shape_cast %[[RHS]] : vector<8x4xi8> to vector<32xi8>
// CHECK-DAG: %[[ACC1D:.+]] = vector.shape_cast %[[ACC]] : vector<8x8xi32> to vector<64xi32>
-// CHECK-DAG: %[[LHS1D_0:.+]] = vector.extract_strided_slice %[[LHS1D]] {offsets = [0], sizes = [16], strides = [1]} : vector<32xi8> to vector<16xi8>
-// CHECK-DAG: %[[RHS1D_0:.+]] = vector.extract_strided_slice %[[RHS1D]] {offsets = [0], sizes = [16], strides = [1]} : vector<32xi8> to vector<16xi8>
-// CHECK-DAG: %[[LHS1D_1:.+]] = vector.extract_strided_slice %[[LHS1D]] {offsets = [16], sizes = [16], strides = [1]} : vector<32xi8> to vector<16xi8>
-// CHECK-DAG: %[[RHS1D_1:.+]] = vector.extract_strided_slice %[[RHS1D]] {offsets = [16], sizes = [16], strides = [1]} : vector<32xi8> to vector<16xi8>
-// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] {offsets = [0], sizes = [4], strides = [1]} : vector<64xi32> to vector<4xi32>
-// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] {offsets = [4], sizes = [4], strides = [1]} : vector<64xi32> to vector<4xi32>
-// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] {offsets = [8], sizes = [4], strides = [1]} : vector<64xi32> to vector<4xi32>
-// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] {offsets = [12], sizes = [4], strides = [1]} : vector<64xi32> to vector<4xi32>
-// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] {offsets = [16], sizes = [4], strides = [1]} : vector<64xi32> to vector<4xi32>
-// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] {offsets = [20], sizes = [4], strides = [1]} : vector<64xi32> to vector<4xi32>
-// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] {offsets = [24], sizes = [4], strides = [1]} : vector<64xi32> to vector<4xi32>
-// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] {offsets = [28], sizes = [4], strides = [1]} : vector<64xi32> to vector<4xi32>
-// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] {offsets = [32], sizes = [4], strides = [1]} : vector<64xi32> to vector<4xi32>
-// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] {offsets = [36], sizes = [4], strides = [1]} : vector<64xi32> to vector<4xi32>
-// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] {offsets = [40], sizes = [4], strides = [1]} : vector<64xi32> to vector<4xi32>
-// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] {offsets = [44], sizes = [4], strides = [1]} : vector<64xi32> to vector<4xi32>
-// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] {offsets = [48], sizes = [4], strides = [1]} : vector<64xi32> to vector<4xi32>
-// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] {offsets = [52], sizes = [4], strides = [1]} : vector<64xi32> to vector<4xi32>
-// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] {offsets = [56], sizes = [4], strides = [1]} : vector<64xi32> to vector<4xi32>
-// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] {offsets = [60], sizes = [4], strides = [1]} : vector<64xi32> to vector<4xi32>
+// CHECK-DAG: %[[LHS1D_0:.+]] = vector.extract_strided_slice %[[LHS1D]] offsets = [0], sizes = [16], strides = [1] : vector<32xi8> to vector<16xi8>
+// CHECK-DAG: %[[RHS1D_0:.+]] = vector.extract_strided_slice %[[RHS1D]] offsets = [0], sizes = [16], strides = [1] : vector<32xi8> to vector<16xi8>
+// CHECK-DAG: %[[LHS1D_1:.+]] = vector.extract_strided_slice %[[LHS1D]] offsets = [16], sizes = [16], strides = [1] : vector<32xi8> to vector<16xi8>
+// CHECK-DAG: %[[RHS1D_1:.+]] = vector.extract_strided_slice %[[RHS1D]] offsets = [16], sizes = [16], strides = [1] : vector<32xi8> to vector<16xi8>
+// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] offsets = [0], sizes = [4], strides = [1] : vector<64xi32> to vector<4xi32>
+// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] offsets = [4], sizes = [4], strides = [1] : vector<64xi32> to vector<4xi32>
+// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] offsets = [8], sizes = [4], strides = [1] : vector<64xi32> to vector<4xi32>
+// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] offsets = [12], sizes = [4], strides = [1] : vector<64xi32> to vector<4xi32>
+// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] offsets = [16], sizes = [4], strides = [1] : vector<64xi32> to vector<4xi32>
+// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] offsets = [20], sizes = [4], strides = [1] : vector<64xi32> to vector<4xi32>
+// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] offsets = [24], sizes = [4], strides = [1] : vector<64xi32> to vector<4xi32>
+// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] offsets = [28], sizes = [4], strides = [1] : vector<64xi32> to vector<4xi32>
+// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] offsets = [32], sizes = [4], strides = [1] : vector<64xi32> to vector<4xi32>
+// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] offsets = [36], sizes = [4], strides = [1] : vector<64xi32> to vector<4xi32>
+// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] offsets = [40], sizes = [4], strides = [1] : vector<64xi32> to vector<4xi32>
+// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] offsets = [44], sizes = [4], strides = [1] : vector<64xi32> to vector<4xi32>
+// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] offsets = [48], sizes = [4], strides = [1] : vector<64xi32> to vector<4xi32>
+// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] offsets = [52], sizes = [4], strides = [1] : vector<64xi32> to vector<4xi32>
+// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] offsets = [56], sizes = [4], strides = [1] : vector<64xi32> to vector<4xi32>
+// CHECK-DAG: {{.+}} = vector.extract_strided_slice %[[ACC1D]] offsets = [60], sizes = [4], strides = [1] : vector<64xi32> to vector<4xi32>
// CHECK-DAG: %[[ASM:.+]] = llvm.inline_asm asm_dialect = att
// CHECK-SAME: {{((.*sdot){16})}}
// CHECK-SAME: "{{(\=w,){16}(w,){4}0,1,.*,15}}"
@@ -74,22 +74,22 @@
// CHECK-DAG: %[[RES13:.+]] = llvm.extractvalue %[[ASM]][13]
// CHECK-DAG: %[[RES14:.+]] = llvm.extractvalue %[[ASM]][14]
// CHECK-DAG: %[[RES15:.+]] = llvm.extractvalue %[[ASM]][15]
-// CHECK: %[[INS0:.+]] = vector.insert_strided_slice %[[RES0]], %[[INITRES]] {offsets = [0], strides = [1]} : vector<4xi32> into vector<64xi32>
-// CHECK: %[[INS1:.+]] = vector.insert_strided_slice %[[RES1]], %[[INS0]] {offsets = [4], strides = [1]} : vector<4xi32> into vector<64xi32>
-// CHECK: %[[INS2:.+]] = vector.insert_strided_slice %[[RES2]], %[[INS1]] {offsets = [8], strides = [1]} : vector<4xi32> into vector<64xi32>
-// CHECK: %[[INS3:.+]] = vector.insert_strided_slice %[[RES3]], %[[INS2]] {offsets = [12], strides = [1]} : vector<4xi32> into vector<64xi32>
-// CHECK: %[[INS4:.+]] = vector.insert_strided_slice %[[RES4]], %[[INS3]] {offsets = [16], strides = [1]} : vector<4xi32> into vector<64xi32>
-// CHECK: %[[INS5:.+]] = vector.insert_strided_slice %[[RES5]], %[[INS4]] {offsets = [20], strides = [1]} : vector<4xi32> into vector<64xi32>
-// CHECK: %[[INS6:.+]] = vector.insert_strided_slice %[[RES6]], %[[INS5]] {offsets = [24], strides = [1]} : vector<4xi32> into vector<64xi32>
-// CHECK: %[[INS7:.+]] = vector.insert_strided_slice %[[RES7]], %[[INS6]] {offsets = [28], strides = [1]} : vector<4xi32> into vector<64xi32>
-// CHECK: %[[INS8:.+]] = vector.insert_strided_slice %[[RES8]], %[[INS7]] {offsets = [32], strides = [1]} : vector<4xi32> into vector<64xi32>
-// CHECK: %[[INS9:.+]] = vector.insert_strided_slice %[[RES9]], %[[INS8]] {offsets = [36], strides = [1]} : vector<4xi32> into vector<64xi32>
-// CHECK: %[[INS10:.+]] = vector.insert_strided_slice %[[RES10]], %[[INS9]] {offsets = [40], strides = [1]} : vector<4xi32> into vector<64xi32>
-// CHECK: %[[INS11:.+]] = vector.insert_strided_slice %[[RES11]], %[[INS10]] {offsets = [44], strides = [1]} : vector<4xi32> into vector<64xi32>
-// CHECK: %[[INS12:.+]] = vector.insert_strided_slice %[[RES12]], %[[INS11]] {offsets = [48], strides = [1]} : vector<4xi32> into vector<64xi32>
-// CHECK: %[[INS13:.+]] = vector.insert_strided_slice %[[RES13]], %[[INS12]] {offsets = [52], strides = [1]} : vector<4xi32> into vector<64xi32>
-// CHECK: %[[INS14:.+]] = vector.insert_strided_slice %[[RES14]], %[[INS13]] {offsets = [56], strides = [1]} : vector<4xi32> into vector<64xi32>
-// CHECK: %[[INS15:.+]] = vector.insert_strided_slice %[[RES15]], %{{.+}} {offsets = [60], strides = [1]} : vector<4xi32> into vector<64xi32>
+// CHECK: %[[INS0:.+]] = vector.insert_strided_slice %[[RES0]], %[[INITRES]] offsets = [0], strides = [1] : vector<4xi32> into vector<64xi32>
+// CHECK: %[[INS1:.+]] = vector.insert_strided_slice %[[RES1]], %[[INS0]] offsets = [4], strides = [1] : vector<4xi32> into vector<64xi32>
+// CHECK: %[[INS2:.+]] = vector.insert_strided_slice %[[RES2]], %[[INS1]] offsets = [8], strides = [1] : vector<4xi32> into vector<64xi32>
+// CHECK: %[[INS3:.+]] = vector.insert_strided_slice %[[RES3]], %[[INS2]] offsets = [12], strides = [1] : vector<4xi32> into vector<64xi32>
+// CHECK: %[[INS4:.+]] = vector.insert_strided_slice %[[RES4]], %[[INS3]] offsets = [16], strides = [1] : vector<4xi32> into vector<64xi32>
+// CHECK: %[[INS5:.+]] = vector.insert_strided_slice %[[RES5]], %[[INS4]] offsets = [20], strides = [1] : vector<4xi32> into vector<64xi32>
+// CHECK: %[[INS6:.+]] = vector.insert_strided_slice %[[RES6]], %[[INS5]] offsets = [24], strides = [1] : vector<4xi32> into vector<64xi32>
+// CHECK: %[[INS7:.+]] = vector.insert_strided_slice %[[RES7]], %[[INS6]] offsets = [28], strides = [1] : vector<4xi32> into vector<64xi32>
+// CHECK: %[[INS8:.+]] = vector.insert_strided_slice %[[RES8]], %[[INS7]] offsets = [32], strides = [1] : vector<4xi32> into vector<64xi32>
+// CHECK: %[[INS9:.+]] = vector.insert_strided_slice %[[RES9]], %[[INS8]] offsets = [36], strides = [1] : vector<4xi32> into vector<64xi32>
+// CHECK: %[[INS10:.+]] = vector.insert_strided_slice %[[RES10]], %[[INS9]] offsets = [40], strides = [1] : vector<4xi32> into vector<64xi32>
+// CHECK: %[[INS11:.+]] = vector.insert_strided_slice %[[RES11]], %[[INS10]] offsets = [44], strides = [1] : vector<4xi32> into vector<64xi32>
+// CHECK: %[[INS12:.+]] = vector.insert_strided_slice %[[RES12]], %[[INS11]] offsets = [48], strides = [1] : vector<4xi32> into vector<64xi32>
+// CHECK: %[[INS13:.+]] = vector.insert_strided_slice %[[RES13]], %[[INS12]] offsets = [52], strides = [1] : vector<4xi32> into vector<64xi32>
+// CHECK: %[[INS14:.+]] = vector.insert_strided_slice %[[RES14]], %[[INS13]] offsets = [56], strides = [1] : vector<4xi32> into vector<64xi32>
+// CHECK: %[[INS15:.+]] = vector.insert_strided_slice %[[RES15]], %{{.+}} offsets = [60], strides = [1] : vector<4xi32> into vector<64xi32>
// CHECK: %[[RESULT1D:.+]] = vector.shape_cast %[[INS15]] : vector<64xi32> to vector<8x8xi32>
// CHECK: return %[[RESULT1D]] : vector<8x8xi32>
diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/test/vector_contract_to_arm_intrinsics.mlir b/compiler/src/iree/compiler/Codegen/LLVMCPU/test/vector_contract_to_arm_intrinsics.mlir
index 466bc11..4259dcd 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMCPU/test/vector_contract_to_arm_intrinsics.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMCPU/test/vector_contract_to_arm_intrinsics.mlir
@@ -13,26 +13,26 @@
// CHECK-DAG: %[[ACC_ROW_5:.*]] = vector.extract %[[ACC]][5] : vector<8xi32> from vector<8x8xi32>
// CHECK-DAG: %[[ACC_ROW_6:.*]] = vector.extract %[[ACC]][6] : vector<8xi32> from vector<8x8xi32>
// CHECK-DAG: %[[ACC_ROW_7:.*]] = vector.extract %[[ACC]][7] : vector<8xi32> from vector<8x8xi32>
-// CHECK-DAG: %[[ACC_CHUNK_00:.*]] = vector.extract_strided_slice %[[ACC_ROW_0]] {offsets = [0]
-// CHECK-DAG: %[[ACC_CHUNK_01:.*]] = vector.extract_strided_slice %[[ACC_ROW_0]] {offsets = [4]
-// CHECK-DAG: %[[ACC_CHUNK_02:.*]] = vector.extract_strided_slice %[[ACC_ROW_1]] {offsets = [0]
-// CHECK-DAG: %[[ACC_CHUNK_03:.*]] = vector.extract_strided_slice %[[ACC_ROW_1]] {offsets = [4]
-// CHECK-DAG: %[[ACC_CHUNK_04:.*]] = vector.extract_strided_slice %[[ACC_ROW_2]] {offsets = [0]
-// CHECK-DAG: %[[ACC_CHUNK_05:.*]] = vector.extract_strided_slice %[[ACC_ROW_2]] {offsets = [4]
-// CHECK-DAG: %[[ACC_CHUNK_06:.*]] = vector.extract_strided_slice %[[ACC_ROW_3]] {offsets = [0]
-// CHECK-DAG: %[[ACC_CHUNK_07:.*]] = vector.extract_strided_slice %[[ACC_ROW_3]] {offsets = [4]
-// CHECK-DAG: %[[ACC_CHUNK_08:.*]] = vector.extract_strided_slice %[[ACC_ROW_4]] {offsets = [0]
-// CHECK-DAG: %[[ACC_CHUNK_09:.*]] = vector.extract_strided_slice %[[ACC_ROW_4]] {offsets = [4]
-// CHECK-DAG: %[[ACC_CHUNK_10:.*]] = vector.extract_strided_slice %[[ACC_ROW_5]] {offsets = [0]
-// CHECK-DAG: %[[ACC_CHUNK_11:.*]] = vector.extract_strided_slice %[[ACC_ROW_5]] {offsets = [4]
-// CHECK-DAG: %[[ACC_CHUNK_12:.*]] = vector.extract_strided_slice %[[ACC_ROW_6]] {offsets = [0]
-// CHECK-DAG: %[[ACC_CHUNK_13:.*]] = vector.extract_strided_slice %[[ACC_ROW_6]] {offsets = [4]
-// CHECK-DAG: %[[ACC_CHUNK_14:.*]] = vector.extract_strided_slice %[[ACC_ROW_7]] {offsets = [0]
-// CHECK-DAG: %[[ACC_CHUNK_15:.*]] = vector.extract_strided_slice %[[ACC_ROW_7]] {offsets = [4]
-// CHECK-DAG: %[[LHS_HALF_0:.*]] = vector.extract_strided_slice %[[LHS]] {offsets = [0, 0]
-// CHECK-DAG: %[[LHS_HALF_1:.*]] = vector.extract_strided_slice %[[LHS]] {offsets = [4, 0]
-// CHECK-DAG: %[[RHS_HALF_0:.*]] = vector.extract_strided_slice %[[RHS]] {offsets = [0, 0]
-// CHECK-DAG: %[[RHS_HALF_1:.*]] = vector.extract_strided_slice %[[RHS]] {offsets = [4, 0]
+// CHECK-DAG: %[[ACC_CHUNK_00:.*]] = vector.extract_strided_slice %[[ACC_ROW_0]] offsets = [0]
+// CHECK-DAG: %[[ACC_CHUNK_01:.*]] = vector.extract_strided_slice %[[ACC_ROW_0]] offsets = [4]
+// CHECK-DAG: %[[ACC_CHUNK_02:.*]] = vector.extract_strided_slice %[[ACC_ROW_1]] offsets = [0]
+// CHECK-DAG: %[[ACC_CHUNK_03:.*]] = vector.extract_strided_slice %[[ACC_ROW_1]] offsets = [4]
+// CHECK-DAG: %[[ACC_CHUNK_04:.*]] = vector.extract_strided_slice %[[ACC_ROW_2]] offsets = [0]
+// CHECK-DAG: %[[ACC_CHUNK_05:.*]] = vector.extract_strided_slice %[[ACC_ROW_2]] offsets = [4]
+// CHECK-DAG: %[[ACC_CHUNK_06:.*]] = vector.extract_strided_slice %[[ACC_ROW_3]] offsets = [0]
+// CHECK-DAG: %[[ACC_CHUNK_07:.*]] = vector.extract_strided_slice %[[ACC_ROW_3]] offsets = [4]
+// CHECK-DAG: %[[ACC_CHUNK_08:.*]] = vector.extract_strided_slice %[[ACC_ROW_4]] offsets = [0]
+// CHECK-DAG: %[[ACC_CHUNK_09:.*]] = vector.extract_strided_slice %[[ACC_ROW_4]] offsets = [4]
+// CHECK-DAG: %[[ACC_CHUNK_10:.*]] = vector.extract_strided_slice %[[ACC_ROW_5]] offsets = [0]
+// CHECK-DAG: %[[ACC_CHUNK_11:.*]] = vector.extract_strided_slice %[[ACC_ROW_5]] offsets = [4]
+// CHECK-DAG: %[[ACC_CHUNK_12:.*]] = vector.extract_strided_slice %[[ACC_ROW_6]] offsets = [0]
+// CHECK-DAG: %[[ACC_CHUNK_13:.*]] = vector.extract_strided_slice %[[ACC_ROW_6]] offsets = [4]
+// CHECK-DAG: %[[ACC_CHUNK_14:.*]] = vector.extract_strided_slice %[[ACC_ROW_7]] offsets = [0]
+// CHECK-DAG: %[[ACC_CHUNK_15:.*]] = vector.extract_strided_slice %[[ACC_ROW_7]] offsets = [4]
+// CHECK-DAG: %[[LHS_HALF_0:.*]] = vector.extract_strided_slice %[[LHS]] offsets = [0, 0]
+// CHECK-DAG: %[[LHS_HALF_1:.*]] = vector.extract_strided_slice %[[LHS]] offsets = [4, 0]
+// CHECK-DAG: %[[RHS_HALF_0:.*]] = vector.extract_strided_slice %[[RHS]] offsets = [0, 0]
+// CHECK-DAG: %[[RHS_HALF_1:.*]] = vector.extract_strided_slice %[[RHS]] offsets = [4, 0]
// CHECK-DAG: %[[LHS_CHUNK_00:.*]] = vector.shuffle %[[LHS_HALF_0]], %[[ZERO]] [0, 0, 0, 0]
// CHECK-DAG: %[[LHS_CHUNK_01:.*]] = vector.shuffle %[[LHS_HALF_0]], %[[ZERO]] [0, 0, 0, 0]
// CHECK-DAG: %[[LHS_CHUNK_02:.*]] = vector.shuffle %[[LHS_HALF_0]], %[[ZERO]] [1, 1, 1, 1]
@@ -65,22 +65,22 @@
// CHECK-DAG: %[[SDOT_CHUNK_13:.*]] = arm_neon.2d.sdot %[[ACC_CHUNK_13]], %[[RHS_HALF_1]], %[[LHS_CHUNK_13]]
// CHECK-DAG: %[[SDOT_CHUNK_14:.*]] = arm_neon.2d.sdot %[[ACC_CHUNK_14]], %[[RHS_HALF_0]], %[[LHS_CHUNK_14]]
// CHECK-DAG: %[[SDOT_CHUNK_15:.*]] = arm_neon.2d.sdot %[[ACC_CHUNK_15]], %[[RHS_HALF_1]], %[[LHS_CHUNK_15]]
-// CHECK-DAG: %[[RES_00:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_00]], %[[ACC]] {offsets = [0, 0]
-// CHECK-DAG: %[[RES_01:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_01]], %[[RES_00]] {offsets = [0, 4]
-// CHECK-DAG: %[[RES_02:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_02]], %[[RES_01]] {offsets = [1, 0]
-// CHECK-DAG: %[[RES_03:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_03]], %[[RES_02]] {offsets = [1, 4]
-// CHECK-DAG: %[[RES_04:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_04]], %[[RES_03]] {offsets = [2, 0]
-// CHECK-DAG: %[[RES_05:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_05]], %[[RES_04]] {offsets = [2, 4]
-// CHECK-DAG: %[[RES_06:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_06]], %[[RES_05]] {offsets = [3, 0]
-// CHECK-DAG: %[[RES_07:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_07]], %[[RES_06]] {offsets = [3, 4]
-// CHECK-DAG: %[[RES_08:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_08]], %[[RES_07]] {offsets = [4, 0]
-// CHECK-DAG: %[[RES_09:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_09]], %[[RES_08]] {offsets = [4, 4]
-// CHECK-DAG: %[[RES_10:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_10]], %[[RES_09]] {offsets = [5, 0]
-// CHECK-DAG: %[[RES_11:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_11]], %[[RES_10]] {offsets = [5, 4]
-// CHECK-DAG: %[[RES_12:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_12]], %[[RES_11]] {offsets = [6, 0]
-// CHECK-DAG: %[[RES_13:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_13]], %[[RES_12]] {offsets = [6, 4]
-// CHECK-DAG: %[[RES_14:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_14]], %[[RES_13]] {offsets = [7, 0]
-// CHECK-DAG: %[[RES_15:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_15]], %[[RES_14]] {offsets = [7, 4]
+// CHECK-DAG: %[[RES_00:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_00]], %[[ACC]] offsets = [0, 0]
+// CHECK-DAG: %[[RES_01:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_01]], %[[RES_00]] offsets = [0, 4]
+// CHECK-DAG: %[[RES_02:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_02]], %[[RES_01]] offsets = [1, 0]
+// CHECK-DAG: %[[RES_03:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_03]], %[[RES_02]] offsets = [1, 4]
+// CHECK-DAG: %[[RES_04:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_04]], %[[RES_03]] offsets = [2, 0]
+// CHECK-DAG: %[[RES_05:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_05]], %[[RES_04]] offsets = [2, 4]
+// CHECK-DAG: %[[RES_06:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_06]], %[[RES_05]] offsets = [3, 0]
+// CHECK-DAG: %[[RES_07:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_07]], %[[RES_06]] offsets = [3, 4]
+// CHECK-DAG: %[[RES_08:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_08]], %[[RES_07]] offsets = [4, 0]
+// CHECK-DAG: %[[RES_09:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_09]], %[[RES_08]] offsets = [4, 4]
+// CHECK-DAG: %[[RES_10:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_10]], %[[RES_09]] offsets = [5, 0]
+// CHECK-DAG: %[[RES_11:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_11]], %[[RES_10]] offsets = [5, 4]
+// CHECK-DAG: %[[RES_12:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_12]], %[[RES_11]] offsets = [6, 0]
+// CHECK-DAG: %[[RES_13:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_13]], %[[RES_12]] offsets = [6, 4]
+// CHECK-DAG: %[[RES_14:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_14]], %[[RES_13]] offsets = [7, 0]
+// CHECK-DAG: %[[RES_15:.*]] = vector.insert_strided_slice %[[SDOT_CHUNK_15]], %[[RES_14]] offsets = [7, 4]
// CHECK: return %[[RES_15]]
func.func @vector_i8i8i32matmul(
%lhs: vector<8x4xi8>,
diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/test/vector_lowering.mlir b/compiler/src/iree/compiler/Codegen/LLVMCPU/test/vector_lowering.mlir
index 26ef0ab..4cbe62f 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMCPU/test/vector_lowering.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMCPU/test/vector_lowering.mlir
@@ -16,7 +16,7 @@
%c16 = arith.constant 16 : index
%cst_0 = arith.constant dense<0.000000e+00> : vector<8x32xf32>
%cst_1 = arith.constant dense<6.000000e+00> : vector<8x32xf32>
- %alloca = memref.alloca() {alignment = 64 : i64} : memref<8x32xf32>
+ %alloca = memref.alloca() alignment = 64 : memref<8x32xf32>
%0 = hal.interface.binding.subspan layout(#pipeline_layout) binding(0) alignment(64) offset(%c0) flags(ReadOnly) : memref<391x384xf32>
%1 = hal.interface.binding.subspan layout(#pipeline_layout) binding(1) alignment(64) offset(%c0) flags(ReadOnly) : memref<384x384xf32>
%2 = hal.interface.binding.subspan layout(#pipeline_layout) binding(2) alignment(64) offset(%c0) flags(ReadOnly) : memref<384xf32>
@@ -93,7 +93,7 @@
%c16 = arith.constant 16 : index
%cst_0 = arith.constant dense<0.000000e+00> : vector<8x32xf32>
%cst_1 = arith.constant dense<6.000000e+00> : vector<8x32xf32>
- %alloca = memref.alloca() {alignment = 64 : i64} : memref<8x32xf32>
+ %alloca = memref.alloca() alignment = 64 : memref<8x32xf32>
%0 = hal.interface.binding.subspan layout(#pipeline_layout) binding(0) alignment(64) offset(%c0) flags(ReadOnly) : memref<391x384xf32>
%1 = hal.interface.binding.subspan layout(#pipeline_layout) binding(1) alignment(64) offset(%c0) flags(ReadOnly) : memref<384x384xf32>
%2 = hal.interface.binding.subspan layout(#pipeline_layout) binding(2) alignment(64) offset(%c0) flags(ReadOnly) : memref<384xf32>
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/pipeline_tile_and_fuse_mma_sync.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/pipeline_tile_and_fuse_mma_sync.mlir
index 748597b..99fa509 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/pipeline_tile_and_fuse_mma_sync.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/pipeline_tile_and_fuse_mma_sync.mlir
@@ -51,7 +51,7 @@
// CHECK: vector.transpose {{.*}}, [1, 0, 2] : vector<2x2x2xf16> to vector<2x2x2xf16>
// CHECK: vector.shape_cast {{.*}} : vector<2x2x2xf16> to vector<4x2xf16>
// Verify nvgpu.mma.sync is generated with correct shape
-// CHECK-COUNT-8: nvgpu.mma.sync({{.*}}) {mmaShape = [16, 8, 16]}
+// CHECK-COUNT-8: nvgpu.mma.sync({{.*}}) mmaShape = [16, 8, 16]
// CHECK: scf.yield
// -----
@@ -95,7 +95,7 @@
// CHECK: vector.transpose {{.*}}, [1, 0, 2] : vector<2x2x2xf16> to vector<2x2x2xf16>
// CHECK: vector.shape_cast {{.*}} : vector<2x2x2xf16> to vector<4x2xf16>
// Verify nvgpu.mma.sync is generated with f16 output type
-// CHECK-COUNT-8: nvgpu.mma.sync({{.*}}) {mmaShape = [16, 8, 16]} : ({{.*}}) -> vector<2x2xf16>
+// CHECK-COUNT-8: nvgpu.mma.sync({{.*}}) mmaShape = [16, 8, 16] : ({{.*}}) -> vector<2x2xf16>
// -----
@@ -137,5 +137,5 @@
// CHECK-DAG: memref.alloc() : memref<{{.*}}xbf16, #gpu.address_space<workgroup>>
// CHECK: scf.for
// Verify nvgpu.mma.sync is generated with correct shape for BF16
-// CHECK-COUNT-8: nvgpu.mma.sync({{.*}}) {mmaShape = [16, 8, 16]} : ({{.*}}) -> vector<2x2xf32>
+// CHECK-COUNT-8: nvgpu.mma.sync({{.*}}) mmaShape = [16, 8, 16] : ({{.*}}) -> vector<2x2xf32>
// CHECK: scf.yield
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/pipeline_vector_distribute_mma_sync.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/pipeline_vector_distribute_mma_sync.mlir
index 8a80b02..fdb19cc 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/pipeline_vector_distribute_mma_sync.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/pipeline_vector_distribute_mma_sync.mlir
@@ -35,7 +35,7 @@
// CHECK-LABEL: func.func @matmul_256x256x256_f16_f32()
// CHECK: scf.for {{.*}} = %c0 to %c256 step %c32 iter_args({{.*}}) -> (vector<2x2xf32>)
-// CHECK-COUNT-2: nvgpu.mma.sync({{.*}}) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf32>) -> vector<2x2xf32>
+// CHECK-COUNT-2: nvgpu.mma.sync({{.*}}) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf32>) -> vector<2x2xf32>
// CHECK: scf.yield
// -----
@@ -70,5 +70,5 @@
// CHECK-LABEL: func.func @matmul_256x256x256_f16_f16()
// CHECK: scf.for {{.*}} = %c0 to %c256 step %c32 iter_args({{.*}}) -> (vector<2x2xf16>)
-// CHECK-COUNT-2: nvgpu.mma.sync({{.*}}) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
+// CHECK-COUNT-2: nvgpu.mma.sync({{.*}}) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf16>) -> vector<2x2xf16>
// CHECK: scf.yield
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/gpu_nested_layout_vector_distribution_wide_shuffle.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/gpu_nested_layout_vector_distribution_wide_shuffle.mlir
index 4759ccf..d87e7b0 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/gpu_nested_layout_vector_distribution_wide_shuffle.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/gpu_nested_layout_vector_distribution_wide_shuffle.mlir
@@ -195,7 +195,7 @@
// CHECK-LABEL: @scan_f64_gfx942_carve_out
func.func @scan_f64_gfx942_carve_out(%src: vector<16xf64>, %init: vector<f64>) -> (vector<16xf64>, vector<f64>) {
%src_l = iree_vector_ext.to_layout %src to layout(#layout_scan_f64) : vector<16xf64>
- %out:2 = vector.scan <add>, %src_l, %init {inclusive = true, reduction_dim = 0 : i64}
+ %out:2 = vector.scan <add>, %src_l, %init reduction_dim = 0, inclusive = true
: vector<16xf64>, vector<f64>
return %out#0, %out#1 : vector<16xf64>, vector<f64>
}
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_igemm_tile_and_fuse.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_igemm_tile_and_fuse.mlir
index ae23c4b..df78071 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_igemm_tile_and_fuse.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_igemm_tile_and_fuse.mlir
@@ -68,7 +68,7 @@
// CHECK-DAG: vector.transpose %[[RHS_MM]], [0, 2, 3, 1] : vector<2x4x4x1xf16> to vector<2x4x1x4xf16>
// CHECK-COUNT-32: amdgpu.mfma 16x16x16
// CHECK: vector.shape_cast %[[LOOP]]#{{.+}} : vector<4xf32> to vector<4x1xf32>
-// CHECK: vector.insert_strided_slice {{.*}} {offsets = [3, 0, 3, 0, 0]{{.*}}} : vector<4x1xf32> into vector<4x1x4x4x1xf32>
+// CHECK: vector.insert_strided_slice {{.*}} offsets = [3, 0, 3, 0, 0]{{.*}} : vector<4x1xf32> into vector<4x1x4x4x1xf32>
// CHECK: %[[LOOP_T:.+]] = vector.transpose %{{.+}}, [0, 1, 2, 4, 3, 5] : vector<1x4x1x4x4x1xf32> to vector<1x4x1x4x4x1xf32>
// CHECK: %[[CAST:.+]] = vector.shape_cast %[[LOOP_T]] : vector<1x4x1x4x4x1xf32> to vector<4x1x4x4x1xf32>
// CHECK: vector.transfer_write %[[CAST]], %[[BUF2]]
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse.mlir
index e85c9c2..c5c20f7 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse.mlir
@@ -131,7 +131,7 @@
// CHECK-COUNT-4: amdgpu.mfma 16x16x16
// CHECK: scf.yield
// CHECK: %[[SC:.+]] = vector.shape_cast %[[LOOP]]#0 : vector<4xf32> to vector<4x1xf32>
-// CHECK: %[[INS:.+]] = vector.insert_strided_slice %[[SC]], %{{.+}} {offsets = [1, 1, 0, 0]{{.*}}} : vector<4x1xf32> into vector<2x2x4x1xf32>
+// CHECK: %[[INS:.+]] = vector.insert_strided_slice %[[SC]], %{{.+}} offsets = [1, 1, 0, 0]{{.*}} : vector<4x1xf32> into vector<2x2x4x1xf32>
// CHECK: %[[LOOP_T:.+]] = vector.transpose %{{.+}}, [0, 2, 1, 3] : vector<2x2x4x1xf32> to vector<2x4x2x1xf32>
// CHECK: vector.transfer_write %[[LOOP_T]], %[[BUF2]]
// CHECK: iree_codegen.dispatch_config @matmul_transpose_b_mfma workgroup_size = [128, 2, 1] subgroup_size = 64
@@ -201,7 +201,7 @@
// CHECK-COUNT-8: amdgpu.wmma 16x16x16 {{.*}} : vector<16xf16>, vector<16xf16>, vector<8xf32>
// CHECK: scf.yield
// CHECK: %[[SC:.+]] = vector.shape_cast %[[LOOP]]#0 : vector<8xf32> to vector<8x1x1xf32>
-// CHECK: %[[INS:.+]] = vector.insert_strided_slice %[[SC]], %{{.+}} {offsets = [1, 1, 0, 0, 0]{{.*}}} : vector<8x1x1xf32> into vector<2x2x8x1x1xf32>
+// CHECK: %[[INS:.+]] = vector.insert_strided_slice %[[SC]], %{{.+}} offsets = [1, 1, 0, 0, 0]{{.*}} : vector<8x1x1xf32> into vector<2x2x8x1x1xf32>
// CHECK: %[[LOOP_T:.+]] = vector.transpose %{{.+}}, [0, 2, 3, 1, 4] : vector<2x2x8x1x1xf32> to vector<2x8x1x2x1xf32>
// CHECK: vector.transfer_write %[[LOOP_T]], %[[BUF2]]
// CHECK: iree_codegen.dispatch_config @matmul_transpose_b_wmmar3 workgroup_size = [64, 2, 1] subgroup_size = 32
@@ -1012,7 +1012,7 @@
// CHECK-COUNT-4: amdgpu.mfma 16x16x16
// CHECK: scf.yield
// CHECK: %[[SC:.+]] = vector.shape_cast %[[LOOP]]#0 : vector<4xf32> to vector<4x1xf32>
-// CHECK: %[[INS:.+]] = vector.insert_strided_slice %[[SC]], %{{.+}} {offsets = [1, 1, 0, 0]{{.*}}} : vector<4x1xf32> into vector<2x2x4x1xf32>
+// CHECK: %[[INS:.+]] = vector.insert_strided_slice %[[SC]], %{{.+}} offsets = [1, 1, 0, 0]{{.*}} : vector<4x1xf32> into vector<2x2x4x1xf32>
// CHECK: %[[LOOP_T:.+]] = vector.transpose %{{.+}}, [0, 2, 1, 3] : vector<2x2x4x1xf32> to vector<2x4x2x1xf32>
// CHECK: vector.transfer_write %[[LOOP_T]]
// CHECK: scf.for {{.*}} {
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse_gfx950.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse_gfx950.mlir
index cd1dbea..1dc5bd3 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse_gfx950.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse_gfx950.mlir
@@ -109,10 +109,10 @@
// CHECK-DAG: %[[B_EXTRACT11:.+]] = vector.extract %[[B_READ]][1, 1, 0, 0] : vector<32xf4E2M1FN> from vector<2x4x1x1x32xf4E2M1FN>
// CHECK-DAG: %[[B_EXTRACT12:.+]] = vector.extract %[[B_READ]][1, 2, 0, 0] : vector<32xf4E2M1FN> from vector<2x4x1x1x32xf4E2M1FN>
// CHECK-DAG: %[[B_EXTRACT13:.+]] = vector.extract %[[B_READ]][1, 3, 0, 0] : vector<32xf4E2M1FN> from vector<2x4x1x1x32xf4E2M1FN>
-// CHECK-DAG: %[[A_SCALE_VECTOR0:.+]] = vector.extract_strided_slice {{.*}} {offsets = [0], sizes = [4], strides = [1]} : vector<32xf8E8M0FNU> to vector<4xf8E8M0FNU>
-// CHECK-DAG: %[[A_SCALE_VECTOR7:.+]] = vector.extract_strided_slice {{.*}} {offsets = [28], sizes = [4], strides = [1]} : vector<32xf8E8M0FNU> to vector<4xf8E8M0FNU>
-// CHECK-DAG: %[[B_SCALE_VECTOR0:.+]] = vector.extract_strided_slice {{.*}} {offsets = [0], sizes = [4], strides = [1]} : vector<8xf8E8M0FNU> to vector<4xf8E8M0FNU>
-// CHECK-DAG: %[[B_SCALE_VECTOR1:.+]] = vector.extract_strided_slice {{.*}} {offsets = [4], sizes = [4], strides = [1]} : vector<8xf8E8M0FNU> to vector<4xf8E8M0FNU>
+// CHECK-DAG: %[[A_SCALE_VECTOR0:.+]] = vector.extract_strided_slice {{.*}} offsets = [0], sizes = [4], strides = [1] : vector<32xf8E8M0FNU> to vector<4xf8E8M0FNU>
+// CHECK-DAG: %[[A_SCALE_VECTOR7:.+]] = vector.extract_strided_slice {{.*}} offsets = [28], sizes = [4], strides = [1] : vector<32xf8E8M0FNU> to vector<4xf8E8M0FNU>
+// CHECK-DAG: %[[B_SCALE_VECTOR0:.+]] = vector.extract_strided_slice {{.*}} offsets = [0], sizes = [4], strides = [1] : vector<8xf8E8M0FNU> to vector<4xf8E8M0FNU>
+// CHECK-DAG: %[[B_SCALE_VECTOR1:.+]] = vector.extract_strided_slice {{.*}} offsets = [4], sizes = [4], strides = [1] : vector<8xf8E8M0FNU> to vector<4xf8E8M0FNU>
// CHECK-DAG: %[[C_00_1:.+]] = amdgpu.scaled_mfma 16x16x128 (%[[A_SCALE_VECTOR0]][0] * %[[A_EXTRACT00]]) * (%[[B_SCALE_VECTOR0]][0] * %[[B_EXTRACT00]]) + %arg[[#ITER_BASE]]
// CHECK-DAG: %[[C_00_2:.+]] = amdgpu.scaled_mfma 16x16x128 (%[[A_SCALE_VECTOR0]][1] * %[[A_EXTRACT01]]) * (%[[B_SCALE_VECTOR0]][1] * %[[B_EXTRACT01]]) + %[[C_00_1]]
// CHECK-DAG: %[[C_00_3:.+]] = amdgpu.scaled_mfma 16x16x128 (%[[A_SCALE_VECTOR0]][2] * %[[A_EXTRACT02]]) * (%[[B_SCALE_VECTOR0]][2] * %[[B_EXTRACT02]]) + %[[C_00_2]]
@@ -130,10 +130,10 @@
// CHECK-DAG: %[[C_71_3:.+]] = amdgpu.scaled_mfma 16x16x128 (%[[A_SCALE_VECTOR7]][2] * %[[A_EXTRACT72]]) * (%[[B_SCALE_VECTOR1]][2] * %[[B_EXTRACT12]]) + %[[C_71_2]]
// CHECK-DAG: %[[C_71_4:.+]] = amdgpu.scaled_mfma 16x16x128 (%[[A_SCALE_VECTOR7]][3] * %[[A_EXTRACT73]]) * (%[[B_SCALE_VECTOR1]][3] * %[[B_EXTRACT13]]) + %[[C_71_3]]
// CHECK: scf.yield
-// CHECK: vector.insert_strided_slice %[[LOOP]]#0, %{{.+}} {offsets = [0, 0, 0, 0, 0]{{.*}}} : vector<4xf32> into vector<8x2x1x1x4xf32>
-// CHECK: vector.insert_strided_slice %[[LOOP]]#1, %{{.+}} {offsets = [0, 1, 0, 0, 0]{{.*}}} : vector<4xf32> into vector<8x2x1x1x4xf32>
-// CHECK: vector.insert_strided_slice %[[LOOP]]#14, %{{.+}} {offsets = [7, 0, 0, 0, 0]{{.*}}} : vector<4xf32> into vector<8x2x1x1x4xf32>
-// CHECK: vector.insert_strided_slice %[[LOOP]]#15, %{{.+}} {offsets = [7, 1, 0, 0, 0]{{.*}}} : vector<4xf32> into vector<8x2x1x1x4xf32>
+// CHECK: vector.insert_strided_slice %[[LOOP]]#0, %{{.+}} offsets = [0, 0, 0, 0, 0]{{.*}} : vector<4xf32> into vector<8x2x1x1x4xf32>
+// CHECK: vector.insert_strided_slice %[[LOOP]]#1, %{{.+}} offsets = [0, 1, 0, 0, 0]{{.*}} : vector<4xf32> into vector<8x2x1x1x4xf32>
+// CHECK: vector.insert_strided_slice %[[LOOP]]#14, %{{.+}} offsets = [7, 0, 0, 0, 0]{{.*}} : vector<4xf32> into vector<8x2x1x1x4xf32>
+// CHECK: vector.insert_strided_slice %[[LOOP]]#15, %{{.+}} offsets = [7, 1, 0, 0, 0]{{.*}} : vector<4xf32> into vector<8x2x1x1x4xf32>
// CHECK: vector.transfer_read %[[BUFFER_C]]
// CHECK: arith.addf
// CHECK: vector.transfer_write
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_vector_distribute_gfx942.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_vector_distribute_gfx942.mlir
index d4c7528..40b8aa9 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_vector_distribute_gfx942.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_vector_distribute_gfx942.mlir
@@ -504,12 +504,12 @@
// CHECK: %[[A_CAST:.+]] = vector.shape_cast %{{.+}} : vector<1x8xf16> to vector<8xf16>
// CHECK: %[[B_CAST:.+]] = vector.shape_cast %{{.+}} : vector<1x8xf16> to vector<8xf16>
-// CHECK: %[[A_SLICE_0:.+]] = vector.extract_strided_slice %[[A_CAST]] {offsets = [0], sizes = [4], strides = [1]} : vector<8xf16> to vector<4xf16>
-// CHECK: %[[B_SLICE_0:.+]] = vector.extract_strided_slice %[[B_CAST]] {offsets = [0], sizes = [4], strides = [1]} : vector<8xf16> to vector<4xf16>
+// CHECK: %[[A_SLICE_0:.+]] = vector.extract_strided_slice %[[A_CAST]] offsets = [0], sizes = [4], strides = [1] : vector<8xf16> to vector<4xf16>
+// CHECK: %[[B_SLICE_0:.+]] = vector.extract_strided_slice %[[B_CAST]] offsets = [0], sizes = [4], strides = [1] : vector<8xf16> to vector<4xf16>
// CHECK: %[[MFMA_0:.*]] = amdgpu.mfma 32x32x8 %[[A_SLICE_0]] * %[[B_SLICE_0]] + %[[ACC]] blgp = none
// CHECK-SAME: : vector<4xf16>, vector<4xf16>, vector<16xf32>
-// CHECK: %[[A_SLICE_1:.+]] = vector.extract_strided_slice %[[A_CAST]] {offsets = [4], sizes = [4], strides = [1]} : vector<8xf16> to vector<4xf16>
-// CHECK: %[[B_SLICE_1:.+]] = vector.extract_strided_slice %[[B_CAST]] {offsets = [4], sizes = [4], strides = [1]} : vector<8xf16> to vector<4xf16>
+// CHECK: %[[A_SLICE_1:.+]] = vector.extract_strided_slice %[[A_CAST]] offsets = [4], sizes = [4], strides = [1] : vector<8xf16> to vector<4xf16>
+// CHECK: %[[B_SLICE_1:.+]] = vector.extract_strided_slice %[[B_CAST]] offsets = [4], sizes = [4], strides = [1] : vector<8xf16> to vector<4xf16>
// CHECK: amdgpu.mfma 32x32x8 %[[A_SLICE_1]] * %[[B_SLICE_1]] + %[[MFMA_0]] blgp = none
// CHECK-SAME: : vector<4xf16>, vector<4xf16>, vector<16xf32>
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/create_async_groups.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/create_async_groups.mlir
index 1bd7f7a..5bfb282 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/create_async_groups.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/create_async_groups.mlir
@@ -9,7 +9,7 @@
%c4 = arith.constant 4 : index
%cst_0 = arith.constant 0.000000e+00 : f32
// Make sure we emit the bypassL1.
- // CHECK: %[[CP0:.*]] = nvgpu.device_async_copy {{.*}}, {{.*}}, 4 {bypassL1} :
+ // CHECK: %[[CP0:.*]] = nvgpu.device_async_copy {{.*}}, {{.*}}, 4 bypassL1 :
%1 = vector.transfer_read %a[%c0, %c0], %cst_0 {in_bounds = [true]} : memref<1024x1024xf32>, vector<4xf32>
vector.transfer_write %1, %0[%c0, %c0, %c0] {in_bounds = [true]} : vector<4xf32>, memref<4x32x16xf32, #gpu.address_space<workgroup>>
// CHECK-NOT: nvgpu.device_async_create_group
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/legalize_nd_vectors.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/legalize_nd_vectors.mlir
index fbf6a24..05f6734 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/legalize_nd_vectors.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/legalize_nd_vectors.mlir
@@ -316,11 +316,11 @@
// nvgpu.mma.sync is legal despite having n-D vectors; materializations bridge
// the 1-D converted values and the n-D op interface.
func.func @mma_sync_legal(%a: vector<4x2xf16>, %b: vector<2x2xf16>, %c: vector<2x2xf32>) -> vector<2x2xf32> {
- %0 = nvgpu.mma.sync(%a, %b, %c) {mmaShape = [16, 8, 16]} : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf32>) -> vector<2x2xf32>
+ %0 = nvgpu.mma.sync(%a, %b, %c) mmaShape = [16, 8, 16] : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf32>) -> vector<2x2xf32>
return %0 : vector<2x2xf32>
}
// CHECK-LABEL: func.func @mma_sync_legal
-// CHECK: nvgpu.mma.sync({{.*}}) {mmaShape = [16, 8, 16]}
+// CHECK: nvgpu.mma.sync({{.*}}) mmaShape = [16, 8, 16]
// CHECK-SAME: : (vector<4x2xf16>, vector<2x2xf16>, vector<2x2xf32>) -> vector<2x2xf32>
// CHECK: return {{.*}} : vector<2xf32>, vector<2xf32>
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/nvvm_pipeline_test.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/nvvm_pipeline_test.mlir
index 0b95ecf..aa1bfb2 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/nvvm_pipeline_test.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/nvvm_pipeline_test.mlir
@@ -466,6 +466,6 @@
// SM80-LABEL: llvm.func @matmul_f16
// SM80-NOT: nvgpu.mma.sync
-// SM80-COUNT-64: nvvm.mma.sync{{.*}}shape = #nvvm.shape<m = 16, n = 8, k = 16>
+// SM80-COUNT-64: nvvm.mma.sync{{.*}}shape = <m = 16, n = 8, k = 16>
// SM80-NOT: nvvm.mma.sync
// SM80: llvm.return
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/pack_shared_memory_alloc.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/pack_shared_memory_alloc.mlir
index 6158173..bab2e63 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/pack_shared_memory_alloc.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/pack_shared_memory_alloc.mlir
@@ -22,6 +22,6 @@
// CHECK: %[[C512:.+]] = arith.constant 512 : index
// CHECK: memref.view %[[PACKED]][%[[C512]]][] : memref<1024xi8, #gpu.address_space<workgroup>> to memref<128xf32, #gpu.address_space<workgroup>>
// CHECK: nvgpu.device_async_create_group
-// CHECK: nvgpu.device_async_wait %0 {numGroups = 0 : i32}
+// CHECK: nvgpu.device_async_wait %0 numGroups = 0
// CHECK: gpu.barrier memfence [#gpu.address_space<workgroup>]
// CHECK: memref.view %[[PACKED]][%[[C0]]][] : memref<1024xi8, #gpu.address_space<workgroup>> to memref<32xf32, #gpu.address_space<workgroup>>
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/rocdl_load_to_transpose_load.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/rocdl_load_to_transpose_load.mlir
index a309263..4a7810b 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/rocdl_load_to_transpose_load.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/rocdl_load_to_transpose_load.mlir
@@ -408,8 +408,8 @@
// CHECK: %[[ROW_OFFSET:.+]] = arith.addi %[[DIV4]], %[[C4]] : index
// CHECK: %[[ROW1:.+]] = arith.addi %[[ROW]], %[[ROW_OFFSET]] : index
// CHECK: %[[L1:.+]] = amdgpu.transpose_load %{{.*}}[%[[ROW1]], %[[NEW_COL]]] : memref<128x256xf16, #gpu.address_space<workgroup>> -> vector<4xf16>
-// CHECK: vector.insert_strided_slice %[[L0]], {{.*}} {offsets = [0], strides = [1]}
-// CHECK: vector.insert_strided_slice %[[L1]], {{.*}} {offsets = [4], strides = [1]}
+// CHECK: vector.insert_strided_slice %[[L0]], {{.*}} offsets = [0], strides = [1]
+// CHECK: vector.insert_strided_slice %[[L1]], {{.*}} offsets = [4], strides = [1]
// CHECK: vector.shape_cast {{.*}} : vector<8xf16> to vector<8x1xf16>
func.func @transform_unroll_f16_8x1() -> vector<8x1xf16> {
%src = memref.alloc() : memref<128x256xf16, #gpu.address_space<workgroup>>
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/transform_dialect_bufferize.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/transform_dialect_bufferize.mlir
index 9637bb9..c07aa76 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/transform_dialect_bufferize.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/transform_dialect_bufferize.mlir
@@ -18,7 +18,7 @@
%5 = linalg.fill ins(%cst : f32) outs(%50 : tensor<250x1020xf32>) -> tensor<250x1020xf32>
// CHECK: linalg.fill ins(%{{.*}} : f32) outs(%{{.*}} : memref<250x1020xf32, #hal.descriptor_type<storage_buffer>>)
- // CHECK: memref.alloc() {alignment = 64 : i64} : memref<250x500xf32, #gpu.address_space<workgroup>>
+ // CHECK: memref.alloc() alignment = 64 : memref<250x500xf32, #gpu.address_space<workgroup>>
// CHECK: gpu.barrier memfence [#gpu.address_space<workgroup>]
// CHECK: linalg.generic
// CHECK: gpu.barrier memfence [#gpu.address_space<workgroup>]
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/transform_dialect_pack_shared_memory_alloc.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/transform_dialect_pack_shared_memory_alloc.mlir
index e1823cc..eb32d4a 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/transform_dialect_pack_shared_memory_alloc.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/transform_dialect_pack_shared_memory_alloc.mlir
@@ -8,7 +8,7 @@
// CHECK: %[[C512:.+]] = arith.constant 512 : index
// CHECK: memref.view %[[PACKED]][%[[C512]]][] : memref<1024xi8, #gpu.address_space<workgroup>> to memref<128xf32, #gpu.address_space<workgroup>>
// CHECK: nvgpu.device_async_create_group
-// CHECK: nvgpu.device_async_wait %0 {numGroups = 0 : i32}
+// CHECK: nvgpu.device_async_wait %0 numGroups = 0
// CHECK: gpu.barrier
// CHECK: memref.view %[[PACKED]][%[[C0]]][] : memref<1024xi8, #gpu.address_space<workgroup>> to memref<32xf32, #gpu.address_space<workgroup>>
func.func @shared_memory_disjoint() {
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/transform_dialect_vector_to_nvgpu_mma.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/transform_dialect_vector_to_nvgpu_mma.mlir
index 42aed57..9cf6560 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/transform_dialect_vector_to_nvgpu_mma.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/transform_dialect_vector_to_nvgpu_mma.mlir
@@ -68,7 +68,7 @@
%vc = vector.transfer_read %c[%c0, %c0], %cst: memref<16x16xf32>, vector<16x16xf32>
// CHECK-NOT: vector.contract
- // CHECK: nvgpu.mma.sync{{.*}} tf32Enabled}
+ // CHECK: nvgpu.mma.sync{{.*}} tf32Enabled
%vres = vector.contract #matmat_trait %va, %vb, %vc
: vector<16x16xf32>, vector<16x16xf32> into vector<16x16xf32>
vector.transfer_write %vres, %c[%c0, %c0]: vector<16x16xf32>, memref<16x16xf32>
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/transform_gpu_pipelining.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/transform_gpu_pipelining.mlir
index bd82f0b..6a4ea9e 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/transform_gpu_pipelining.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/transform_gpu_pipelining.mlir
@@ -39,18 +39,18 @@
nvgpu.device_async_wait %21
gpu.barrier memfence [#gpu.address_space<workgroup>]
%22 = affine.apply affine_map<()[s0] -> (s0 * 16)>()[%2]
- %23 = gpu.subgroup_mma_load_matrix %4[%16, %22, %c0] {leadDimension = 40 : index} : memref<4x32x40xf16, 3> -> !gpu.mma_matrix<16x16xf16, "AOp">
- %24 = gpu.subgroup_mma_load_matrix %4[%16, %22, %c16] {leadDimension = 40 : index} : memref<4x32x40xf16, 3> -> !gpu.mma_matrix<16x16xf16, "AOp">
+ %23 = gpu.subgroup_mma_load_matrix %4[%16, %22, %c0] leadDimension 40 : memref<4x32x40xf16, 3> -> !gpu.mma_matrix<16x16xf16, "AOp">
+ %24 = gpu.subgroup_mma_load_matrix %4[%16, %22, %c16] leadDimension 40 : memref<4x32x40xf16, 3> -> !gpu.mma_matrix<16x16xf16, "AOp">
%25 = affine.apply affine_map<()[s0] -> ((s0 floordiv 32) * 16)>()[%1]
- %26 = gpu.subgroup_mma_load_matrix %5[%16, %c0, %25] {leadDimension = 40 : index} : memref<4x32x40xf16, 3> -> !gpu.mma_matrix<16x16xf16, "BOp">
- %27 = gpu.subgroup_mma_load_matrix %5[%16, %c16, %25] {leadDimension = 40 : index} : memref<4x32x40xf16, 3> -> !gpu.mma_matrix<16x16xf16, "BOp">
+ %26 = gpu.subgroup_mma_load_matrix %5[%16, %c0, %25] leadDimension 40 : memref<4x32x40xf16, 3> -> !gpu.mma_matrix<16x16xf16, "BOp">
+ %27 = gpu.subgroup_mma_load_matrix %5[%16, %c16, %25] leadDimension 40 : memref<4x32x40xf16, 3> -> !gpu.mma_matrix<16x16xf16, "BOp">
%28 = gpu.subgroup_mma_compute %23, %26, %arg1 : !gpu.mma_matrix<16x16xf16, "AOp">, !gpu.mma_matrix<16x16xf16, "BOp"> -> !gpu.mma_matrix<16x16xf16, "COp">
%29 = gpu.subgroup_mma_compute %24, %27, %28 : !gpu.mma_matrix<16x16xf16, "AOp">, !gpu.mma_matrix<16x16xf16, "BOp"> -> !gpu.mma_matrix<16x16xf16, "COp">
scf.yield %29 : !gpu.mma_matrix<16x16xf16, "COp">
}
%12 = affine.apply affine_map<()[s0, s1] -> (s0 * 16 + s1 * 32)>()[%2, %workgroup_id_y]
%13 = affine.apply affine_map<()[s0, s1] -> (s1 * 32 + (s0 floordiv 32) * 16)>()[%1, %workgroup_id_x]
- gpu.subgroup_mma_store_matrix %11, %8[%12, %13] {leadDimension = 1024 : index} : !gpu.mma_matrix<16x16xf16, "COp">, memref<3456x1024xf16>
+ gpu.subgroup_mma_store_matrix %11, %8[%12, %13] leadDimension 1024 : !gpu.mma_matrix<16x16xf16, "COp">, memref<3456x1024xf16>
return
}
}
@@ -76,7 +76,7 @@
// CHECK: nvgpu.device_async_copy
// CHECK: nvgpu.device_async_create_group
// CHECK: scf.for
-// CHECK: nvgpu.device_async_wait %{{.*}} {numGroups = 3 : i32}
+// CHECK: nvgpu.device_async_wait %{{.*}} numGroups = 3
// CHECK: nvgpu.device_async_copy
// CHECK: nvgpu.device_async_copy
// CHECK: nvgpu.device_async_create_group
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/transform_vector_to_mma.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/transform_vector_to_mma.mlir
index 7f39db9..1b6f81c 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/transform_vector_to_mma.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/transform_vector_to_mma.mlir
@@ -23,15 +23,15 @@
%6 = affine.apply affine_map<()[s0] -> ((s0 floordiv 32) * 16)>()[%3]
// CHECK: gpu.subgroup_mma_constant_matrix %{{.*}} : !gpu.mma_matrix<16x16xf32, "COp">
// CHECK: scf.for {{.*}} -> (!gpu.mma_matrix<16x16xf32, "COp">) {
-// CHECK: gpu.subgroup_mma_load_matrix {{.*}} {leadDimension = 32 : index} : memref<32x32xf32> -> !gpu.mma_matrix<16x8xf32, "AOp">
-// CHECK: gpu.subgroup_mma_load_matrix {{.*}} {leadDimension = 32 : index} : memref<32x32xf32> -> !gpu.mma_matrix<16x8xf32, "AOp">
-// CHECK: gpu.subgroup_mma_load_matrix {{.*}} {leadDimension = 32 : index} : memref<32x32xf32> -> !gpu.mma_matrix<8x16xf32, "BOp">
-// CHECK: gpu.subgroup_mma_load_matrix {{.*}} {leadDimension = 32 : index} : memref<32x32xf32> -> !gpu.mma_matrix<8x16xf32, "BOp">
+// CHECK: gpu.subgroup_mma_load_matrix {{.*}} leadDimension 32 : memref<32x32xf32> -> !gpu.mma_matrix<16x8xf32, "AOp">
+// CHECK: gpu.subgroup_mma_load_matrix {{.*}} leadDimension 32 : memref<32x32xf32> -> !gpu.mma_matrix<16x8xf32, "AOp">
+// CHECK: gpu.subgroup_mma_load_matrix {{.*}} leadDimension 32 : memref<32x32xf32> -> !gpu.mma_matrix<8x16xf32, "BOp">
+// CHECK: gpu.subgroup_mma_load_matrix {{.*}} leadDimension 32 : memref<32x32xf32> -> !gpu.mma_matrix<8x16xf32, "BOp">
// CHECK: gpu.subgroup_mma_compute {{.*}} : !gpu.mma_matrix<16x8xf32, "AOp">, !gpu.mma_matrix<8x16xf32, "BOp"> -> !gpu.mma_matrix<16x16xf32, "COp">
// CHECK: gpu.subgroup_mma_compute {{.*}} : !gpu.mma_matrix<16x8xf32, "AOp">, !gpu.mma_matrix<8x16xf32, "BOp"> -> !gpu.mma_matrix<16x16xf32, "COp">
// CHECK: scf.yield {{.*}} : !gpu.mma_matrix<16x16xf32, "COp">
// CHECK: }
-// CHECK: gpu.subgroup_mma_store_matrix {{.*}} {leadDimension = 32 : index} : !gpu.mma_matrix<16x16xf32, "COp">, memref<32x32xf32>
+// CHECK: gpu.subgroup_mma_store_matrix {{.*}} leadDimension 32 : !gpu.mma_matrix<16x16xf32, "COp">, memref<32x32xf32>
%7 = scf.for %arg0 = %c0 to %c32 step %c16 iter_args(%arg1 = %cst) -> (vector<16x16xf32>) {
%10 = affine.apply affine_map<(d0)[s0] -> (d0 + s0)>(%c0)[%5]
%11 = affine.apply affine_map<(d0)[s0] -> (d0 + s0)>(%c0)[%arg0]
@@ -92,7 +92,7 @@
%0 = hal.interface.binding.subspan layout(#pipeline_layout) binding(0) alignment(64) offset(%c0) : memref<32x32xf32>
%1 = hal.interface.binding.subspan layout(#pipeline_layout) binding(1) alignment(64) offset(%c0) : memref<32x32xf32>
%2 = hal.interface.binding.subspan layout(#pipeline_layout) binding(2) alignment(64) offset(%c0) : memref<32x32xf32>
- %alloc = memref.alloc() {alignment = 64 : i64} : memref<32x32xf32>
+ %alloc = memref.alloc() alignment = 64 : memref<32x32xf32>
%3 = gpu.thread_id x
%4 = gpu.thread_id y
%5 = affine.apply affine_map<()[s0] -> (s0 * 16)>()[%4]
@@ -101,15 +101,15 @@
// CHECK: scf.for {{.*}} -> (!gpu.mma_matrix<16x16xf32, "COp">) {
// CHECK: arith.addi {{.*}} : vector<4xindex>
// CHECK: vector.gather {{.*}} : memref<32x32xf32>, vector<4x4xindex>, vector<4x4xi1>, vector<4x4xf32> into vector<4x4xf32>
-// CHECK: gpu.subgroup_mma_load_matrix {{.*}} {leadDimension = 32 : index} : memref<32x32xf32> -> !gpu.mma_matrix<16x8xf32, "AOp">
-// CHECK: gpu.subgroup_mma_load_matrix {{.*}} {leadDimension = 32 : index} : memref<32x32xf32> -> !gpu.mma_matrix<16x8xf32, "AOp">
-// CHECK: gpu.subgroup_mma_load_matrix {{.*}} {leadDimension = 32 : index} : memref<32x32xf32> -> !gpu.mma_matrix<8x16xf32, "BOp">
-// CHECK: gpu.subgroup_mma_load_matrix {{.*}} {leadDimension = 32 : index} : memref<32x32xf32> -> !gpu.mma_matrix<8x16xf32, "BOp">
+// CHECK: gpu.subgroup_mma_load_matrix {{.*}} leadDimension 32 : memref<32x32xf32> -> !gpu.mma_matrix<16x8xf32, "AOp">
+// CHECK: gpu.subgroup_mma_load_matrix {{.*}} leadDimension 32 : memref<32x32xf32> -> !gpu.mma_matrix<16x8xf32, "AOp">
+// CHECK: gpu.subgroup_mma_load_matrix {{.*}} leadDimension 32 : memref<32x32xf32> -> !gpu.mma_matrix<8x16xf32, "BOp">
+// CHECK: gpu.subgroup_mma_load_matrix {{.*}} leadDimension 32 : memref<32x32xf32> -> !gpu.mma_matrix<8x16xf32, "BOp">
// CHECK: gpu.subgroup_mma_compute {{.*}} : !gpu.mma_matrix<16x8xf32, "AOp">, !gpu.mma_matrix<8x16xf32, "BOp"> -> !gpu.mma_matrix<16x16xf32, "COp">
// CHECK: gpu.subgroup_mma_compute {{.*}} : !gpu.mma_matrix<16x8xf32, "AOp">, !gpu.mma_matrix<8x16xf32, "BOp"> -> !gpu.mma_matrix<16x16xf32, "COp">
// CHECK: scf.yield {{.*}} : !gpu.mma_matrix<16x16xf32, "COp">
// CHECK: }
-// CHECK: gpu.subgroup_mma_store_matrix {{.*}} {leadDimension = 32 : index} : !gpu.mma_matrix<16x16xf32, "COp">, memref<32x32xf32>
+// CHECK: gpu.subgroup_mma_store_matrix {{.*}} leadDimension 32 : !gpu.mma_matrix<16x16xf32, "COp">, memref<32x32xf32>
%7 = scf.for %arg0 = %c0 to %c32 step %c16 iter_args(%arg1 = %cst) -> (vector<16x16xf32>) {
%10 = vector.broadcast %arg0 : index to vector<4xindex>
%11 = arith.addi %10, %cst_1 : vector<4xindex>
diff --git a/compiler/src/iree/compiler/Codegen/SPIRV/test/break_down_large_vector.mlir b/compiler/src/iree/compiler/Codegen/SPIRV/test/break_down_large_vector.mlir
index 3db6cf0..958a2d0 100644
--- a/compiler/src/iree/compiler/Codegen/SPIRV/test/break_down_large_vector.mlir
+++ b/compiler/src/iree/compiler/Codegen/SPIRV/test/break_down_large_vector.mlir
@@ -4,7 +4,7 @@
func.func @extract_strided_slice_8_elements(%input: vector<8xf16>) -> vector<4xf16> {
// CHECK-COUNT-4: vector.extract
// CHECK: vector.from_elements
- %0 = vector.extract_strided_slice %input {offsets = [1], sizes = [4], strides = [1]} : vector<8xf16> to vector<4xf16>
+ %0 = vector.extract_strided_slice %input offsets = [1], sizes = [4], strides = [1] : vector<8xf16> to vector<4xf16>
return %0: vector<4xf16>
}
@@ -13,7 +13,7 @@
// CHECK-LABEL: func @extract_strided_slice_4_elements
func.func @extract_strided_slice_4_elements(%input: vector<4xf16>) -> vector<2xf16> {
// CHECK: vector.extract_strided_slice
- %0 = vector.extract_strided_slice %input {offsets = [1], sizes = [2], strides = [1]} : vector<4xf16> to vector<2xf16>
+ %0 = vector.extract_strided_slice %input offsets = [1], sizes = [2], strides = [1] : vector<4xf16> to vector<2xf16>
return %0: vector<2xf16>
}
@@ -35,7 +35,7 @@
func.func @bitcast_extract_extend_0(%input: vector<1xi32>) -> vector<4xi32> {
%bitcast = vector.bitcast %input : vector<1xi32> to vector<8xi4>
- %extract = vector.extract_strided_slice %bitcast {offsets = [0], sizes = [4], strides = [1]} : vector<8xi4> to vector<4xi4>
+ %extract = vector.extract_strided_slice %bitcast offsets = [0], sizes = [4], strides = [1] : vector<8xi4> to vector<4xi4>
%extend = arith.extui %extract : vector<4xi4> to vector<4xi32>
return %extend : vector<4xi32>
}
@@ -61,7 +61,7 @@
func.func @bitcast_extract_extend_1(%input: vector<4xi32>) -> vector<4xi32> {
%bitcast = vector.bitcast %input : vector<4xi32> to vector<32xi4>
- %extract = vector.extract_strided_slice %bitcast {offsets = [20], sizes = [4], strides = [1]} : vector<32xi4> to vector<4xi4>
+ %extract = vector.extract_strided_slice %bitcast offsets = [20], sizes = [4], strides = [1] : vector<32xi4> to vector<4xi4>
%extend = arith.extui %extract : vector<4xi4> to vector<4xi32>
return %extend : vector<4xi32>
}
diff --git a/compiler/src/iree/compiler/Codegen/SPIRV/test/initial_vector_lowering_index_type.mlir b/compiler/src/iree/compiler/Codegen/SPIRV/test/initial_vector_lowering_index_type.mlir
index db5751d..e4d15d3 100644
--- a/compiler/src/iree/compiler/Codegen/SPIRV/test/initial_vector_lowering_index_type.mlir
+++ b/compiler/src/iree/compiler/Codegen/SPIRV/test/initial_vector_lowering_index_type.mlir
@@ -23,15 +23,15 @@
// CHECK-DAG: %[[CST2:.+]] = arith.constant dense<2> : vector<1xindex>
// CHECK-DAG: %[[CST1:.+]] = arith.constant dense<1> : vector<1xindex>
// CHECK: %[[STEP:.+]] = vector.step : vector<1xindex>
-// CHECK: %[[INS0:.+]] = vector.insert_strided_slice %[[STEP]], %{{.+}} {offsets = [0], strides = [1]} : vector<1xindex> into vector<5xindex>
+// CHECK: %[[INS0:.+]] = vector.insert_strided_slice %[[STEP]], %{{.+}} offsets = [0], strides = [1] : vector<1xindex> into vector<5xindex>
// CHECK: %[[ADD1:.+]] = arith.addi %[[STEP]], %[[CST1]] : vector<1xindex>
-// CHECK: %[[INS1:.+]] = vector.insert_strided_slice %[[ADD1]], %[[INS0]] {offsets = [1], strides = [1]} : vector<1xindex> into vector<5xindex>
+// CHECK: %[[INS1:.+]] = vector.insert_strided_slice %[[ADD1]], %[[INS0]] offsets = [1], strides = [1] : vector<1xindex> into vector<5xindex>
// CHECK: %[[ADD2:.+]] = arith.addi %[[STEP]], %[[CST2]] : vector<1xindex>
-// CHECK: %[[INS2:.+]] = vector.insert_strided_slice %[[ADD2]], %[[INS1]] {offsets = [2], strides = [1]} : vector<1xindex> into vector<5xindex>
+// CHECK: %[[INS2:.+]] = vector.insert_strided_slice %[[ADD2]], %[[INS1]] offsets = [2], strides = [1] : vector<1xindex> into vector<5xindex>
// CHECK: %[[ADD3:.+]] = arith.addi %[[STEP]], %[[CST3]] : vector<1xindex>
-// CHECK: %[[INS3:.+]] = vector.insert_strided_slice %[[ADD3]], %[[INS2]] {offsets = [3], strides = [1]} : vector<1xindex> into vector<5xindex>
+// CHECK: %[[INS3:.+]] = vector.insert_strided_slice %[[ADD3]], %[[INS2]] offsets = [3], strides = [1] : vector<1xindex> into vector<5xindex>
// CHECK: %[[ADD4:.+]] = arith.addi %[[STEP]], %[[CST4]] : vector<1xindex>
-// CHECK: %[[INS4:.+]] = vector.insert_strided_slice %[[ADD4]], %[[INS3]] {offsets = [4], strides = [1]} : vector<1xindex> into vector<5xindex>
+// CHECK: %[[INS4:.+]] = vector.insert_strided_slice %[[ADD4]], %[[INS3]] offsets = [4], strides = [1] : vector<1xindex> into vector<5xindex>
// CHECK: vector.store %[[INS4]], %{{.+}}[%{{.+}}] : memref<5xindex>, vector<5xindex>
func.func @step_unroll(%dest: memref<5xindex>) {
%c0 = arith.constant 0 : index
diff --git a/compiler/src/iree/compiler/Codegen/SPIRV/test/lowering_matmul_fusion.mlir b/compiler/src/iree/compiler/Codegen/SPIRV/test/lowering_matmul_fusion.mlir
index 5a279ec..ac52bf9 100644
--- a/compiler/src/iree/compiler/Codegen/SPIRV/test/lowering_matmul_fusion.mlir
+++ b/compiler/src/iree/compiler/Codegen/SPIRV/test/lowering_matmul_fusion.mlir
@@ -84,9 +84,9 @@
// CHECK: %[[SCALE0:.+]] = vector.transfer_read %[[SCALE_SUB]]
// CHECK: %[[SCALE1:.+]] = vector.transfer_read %[[SCALE_SUB]]
// CHECK: %[[ZP:.+]] = vector.transfer_read %[[ZP_SUB]]
-// CHECK: %[[SLICE0:.+]] = vector.extract_strided_slice %[[ZP]] {offsets = [0], sizes = [4], strides = [1]} : vector<8xi4> to vector<4xi4>
+// CHECK: %[[SLICE0:.+]] = vector.extract_strided_slice %[[ZP]] offsets = [0], sizes = [4], strides = [1] : vector<8xi4> to vector<4xi4>
// CHECK: %[[ZP_EXT0:.+]] = arith.extsi %[[SLICE0]] : vector<4xi4> to vector<4xi32>
-// CHECK: %[[SLICE1:.+]] = vector.extract_strided_slice %[[ZP]] {offsets = [4], sizes = [4], strides = [1]} : vector<8xi4> to vector<4xi4>
+// CHECK: %[[SLICE1:.+]] = vector.extract_strided_slice %[[ZP]] offsets = [4], sizes = [4], strides = [1] : vector<8xi4> to vector<4xi4>
// CHECK: %[[ZP_EXT1:.+]] = arith.extsi %[[SLICE1]] : vector<4xi4> to vector<4xi32>
// CHECK: scf.for %arg5 = %c0 to %c96 step %c32 iter_args({{.+}}) -> (vector<4xf32>, vector<4xf32>, vector<4xf32>, vector<4xf32>, vector<4xf32>)
diff --git a/compiler/src/iree/compiler/Codegen/SPIRV/test/lowering_reduction.mlir b/compiler/src/iree/compiler/Codegen/SPIRV/test/lowering_reduction.mlir
index b0560c2..bd47786 100644
--- a/compiler/src/iree/compiler/Codegen/SPIRV/test/lowering_reduction.mlir
+++ b/compiler/src/iree/compiler/Codegen/SPIRV/test/lowering_reduction.mlir
@@ -146,12 +146,12 @@
// CHECK: scf.for %[[IV:.+]] = %[[C0]] to %[[C9216]] step %[[C1024]] {
// CHECK: %[[OFFSET:.+]] = affine.apply {{.*}}(%[[IV]])[%[[TIDX]]]
// CHECK: %[[READ:.+]] = vector.transfer_read %[[SPAN0]][%[[DELIN]]#0, %[[DELIN]]#1, %[[OFFSET]]], %[[PV]] {in_bounds = [true]} : memref<10x9216x9216xf16{{.*}}>, vector<8xf16>
-// CHECK: %[[SLICE0:.+]] = vector.extract_strided_slice %[[READ]] {offsets = [0], sizes = [4], strides = [1]}
+// CHECK: %[[SLICE0:.+]] = vector.extract_strided_slice %[[READ]] offsets = [0], sizes = [4], strides = [1]
// CHECK: %[[DIV0:.+]] = arith.divf %[[SLICE0]], %[[BROADCAST]] : vector<4xf16>
-// CHECK: %[[SLICE1:.+]] = vector.insert_strided_slice %[[DIV0]], %cst {offsets = [0], strides = [1]}
-// CHECK: %[[SLICE2:.+]] = vector.extract_strided_slice %[[READ]] {offsets = [4], sizes = [4], strides = [1]}
+// CHECK: %[[SLICE1:.+]] = vector.insert_strided_slice %[[DIV0]], %cst offsets = [0], strides = [1]
+// CHECK: %[[SLICE2:.+]] = vector.extract_strided_slice %[[READ]] offsets = [4], sizes = [4], strides = [1]
// CHECK: %[[DIV1:.+]] = arith.divf %[[SLICE2]], %[[BROADCAST]] : vector<4xf16>
-// CHECK: %[[SLICE3:.+]] = vector.insert_strided_slice %[[DIV1]], %[[SLICE1]] {offsets = [4], strides = [1]}
+// CHECK: %[[SLICE3:.+]] = vector.insert_strided_slice %[[DIV1]], %[[SLICE1]] offsets = [4], strides = [1]
// CHECK: vector.transfer_write %[[SLICE3]], %[[SPAN1]][%[[DELIN]]#0, %[[DELIN]]#1, %{{.*}}] {in_bounds = [true]} : vector<8xf16>, memref<10x9216x9216xf16{{.*}}>
// CHECK: }
// CHECK: }
diff --git a/compiler/src/iree/compiler/Codegen/SPIRV/test/tile_and_promote_cooperative_matrix.mlir b/compiler/src/iree/compiler/Codegen/SPIRV/test/tile_and_promote_cooperative_matrix.mlir
index 3ebe1d1..274d3c8 100644
--- a/compiler/src/iree/compiler/Codegen/SPIRV/test/tile_and_promote_cooperative_matrix.mlir
+++ b/compiler/src/iree/compiler/Codegen/SPIRV/test/tile_and_promote_cooperative_matrix.mlir
@@ -374,7 +374,7 @@
%subview = memref.subview %2[0, %arg0, %arg1] [1, 64, 128] [1, 1, 1] : memref<1x4096x4096xf32> to memref<1x64x128xf32, strided<[16777216, 4096, 1], offset: ?>>
%subview_0 = memref.subview %0[0, %arg0, 0] [1, 64, 512] [1, 1, 1] : memref<1x4096x512xf16> to memref<1x64x512xf16, strided<[2097152, 512, 1], offset: ?>>
%subview_1 = memref.subview %1[0, 0, %arg1] [1, 512, 128] [1, 1, 1] : memref<1x512x4096xf16> to memref<1x512x128xf16, strided<[2097152, 4096, 1], offset: ?>>
- %alloc = memref.alloc() {alignment = 128 : i64} : memref<1x64x128xf16, #gpu.address_space<workgroup>>
+ %alloc = memref.alloc() alignment = 128 : memref<1x64x128xf16, #gpu.address_space<workgroup>>
linalg.fill ins(%cst : f16) outs(%alloc : memref<1x64x128xf16, #gpu.address_space<workgroup>>)
linalg.batch_matmul {lowering_config = #config} ins(%subview_0, %subview_1 : memref<1x64x512xf16, strided<[2097152, 512, 1], offset: ?>>, memref<1x512x128xf16, strided<[2097152, 4096, 1], offset: ?>>) outs(%alloc : memref<1x64x128xf16, #gpu.address_space<workgroup>>)
linalg.generic {indexing_maps = [#map2, #map2], iterator_types = ["parallel", "parallel", "parallel"]} ins(%alloc : memref<1x64x128xf16, #gpu.address_space<workgroup>>) outs(%subview : memref<1x64x128xf32, strided<[16777216, 4096, 1], offset: ?>>) {
@@ -391,7 +391,7 @@
// PROMOTEC-DAG: %[[LHS_ALLOC:.+]] = memref.alloc() : memref<1x64x32xf16, #gpu.address_space<workgroup>>
// PROMOTEC-DAG: %[[RHS_ALLOC:.+]] = memref.alloc() : memref<1x32x128xf16, #gpu.address_space<workgroup>>
-// PROMOTEC-DAG: %[[C_ALLOC:.+]] = memref.alloc() {alignment = 128 : i64} : memref<1x64x128xf16, #gpu.address_space<workgroup>>
+// PROMOTEC-DAG: %[[C_ALLOC:.+]] = memref.alloc() alignment = 128 : memref<1x64x128xf16, #gpu.address_space<workgroup>>
// PROMOTEC: linalg.fill
// PROMOTEC-SAME: __internal_linalg_transform__ = "workgroup_memory"
diff --git a/compiler/src/iree/compiler/Codegen/SPIRV/test/vectorize_gather.mlir b/compiler/src/iree/compiler/Codegen/SPIRV/test/vectorize_gather.mlir
index e436221..c61c982 100644
--- a/compiler/src/iree/compiler/Codegen/SPIRV/test/vectorize_gather.mlir
+++ b/compiler/src/iree/compiler/Codegen/SPIRV/test/vectorize_gather.mlir
@@ -59,5 +59,5 @@
// CHECK: %[[EXTRACT3:.+]] = vector.extract %[[LOAD3]][0] : i8 from vector<1xi8>
// CHECK: %[[VEC:.+]] = vector.from_elements %[[EXTRACT0]], %[[EXTRACT1]], %[[EXTRACT2]], %[[EXTRACT3]] : vector<4xi8>
-// CHECK: vector.insert_strided_slice %[[VEC]], %[[INIT]] {offsets = [0], strides = [1]} : vector<4xi8> into vector<16xi8>
+// CHECK: vector.insert_strided_slice %[[VEC]], %[[INIT]] offsets = [0], strides = [1] : vector<4xi8> into vector<16xi8>
// CHECK-COUNT-12: vector.load %[[ARG0]][%{{.+}}#0, %{{.+}}#1, %{{.+}}#2] : memref<16x1082x1922xi8>, vector<1xi8>
diff --git a/compiler/src/iree/compiler/Codegen/SPIRV/test/vectorize_load_store.mlir b/compiler/src/iree/compiler/Codegen/SPIRV/test/vectorize_load_store.mlir
index 2494d9b..810f15b 100644
--- a/compiler/src/iree/compiler/Codegen/SPIRV/test/vectorize_load_store.mlir
+++ b/compiler/src/iree/compiler/Codegen/SPIRV/test/vectorize_load_store.mlir
@@ -31,9 +31,9 @@
// BASE: %[[LOAD2:.+]] = memref.load %[[ARG]][%[[IDX0]], %[[OFFSET2]]]
// BASE: %[[VEC:.+]] = vector.shuffle %[[LOAD1]], %[[LOAD2]] [0, 1, 2, 3, 4, 5, 6, 7] : vector<4xf32>, vector<4xf32>
-// BASE: %[[VEC0:.+]] = vector.extract_strided_slice %[[VEC]] {offsets = [0], sizes = [4], strides = [1]} : vector<8xf32> to vector<4xf32>
+// BASE: %[[VEC0:.+]] = vector.extract_strided_slice %[[VEC]] offsets = [0], sizes = [4], strides = [1] : vector<8xf32> to vector<4xf32>
// BASE: memref.store %[[VEC0]], %[[ALLOC]][%[[IDX0]], %[[OFFSET1]]]
-// BASE: %[[VEC1:.+]] = vector.extract_strided_slice %[[VEC]] {offsets = [4], sizes = [4], strides = [1]} : vector<8xf32> to vector<4xf32>
+// BASE: %[[VEC1:.+]] = vector.extract_strided_slice %[[VEC]] offsets = [4], sizes = [4], strides = [1] : vector<8xf32> to vector<4xf32>
// BASE: memref.store %[[VEC1]], %[[ALLOC]][%[[IDX0]], %4]
// -----
@@ -386,15 +386,15 @@
// CHECK-SAME: (%[[I0:.+]]: index, %[[I1:.+]]: index)
func.func @vectorize_alloc_with_mma_load_store(%i0: index, %i1: index) {
%alloc = memref.alloc() : memref<32x32xf16, 3>
- %0 = gpu.subgroup_mma_load_matrix %alloc[%i0, %i1] {leadDimension = 32 : index} : memref<32x32xf16, 3> -> !gpu.mma_matrix<16x16xf16, "COp">
- gpu.subgroup_mma_store_matrix %0, %alloc[%i0, %i1] {leadDimension = 32 : index} : !gpu.mma_matrix<16x16xf16, "COp">, memref<32x32xf16, 3>
+ %0 = gpu.subgroup_mma_load_matrix %alloc[%i0, %i1] leadDimension 32 : memref<32x32xf16, 3> -> !gpu.mma_matrix<16x16xf16, "COp">
+ gpu.subgroup_mma_store_matrix %0, %alloc[%i0, %i1] leadDimension 32 : !gpu.mma_matrix<16x16xf16, "COp">, memref<32x32xf16, 3>
return
}
// CHECK: %[[ALLOC:.+]] = memref.alloc() : memref<32x4xvector<4xf32>, 3>
// CHECK: %[[IDX:.+]] = affine.apply affine_map<()[s0] -> (s0 floordiv 8)>()[%[[I1]]]
-// CHECK: %[[LD:.+]] = gpu.subgroup_mma_load_matrix %[[ALLOC]][%[[I0]], %[[IDX]]] {leadDimension = 4 : index} : memref<32x4xvector<4xf32>, 3> -> !gpu.mma_matrix<16x16xf16, "COp">
-// CHECK: gpu.subgroup_mma_store_matrix %[[LD]], %[[ALLOC]][%[[I0]], %[[IDX]]] {leadDimension = 4 : index} : !gpu.mma_matrix<16x16xf16, "COp">, memref<32x4xvector<4xf32>, 3>
+// CHECK: %[[LD:.+]] = gpu.subgroup_mma_load_matrix %[[ALLOC]][%[[I0]], %[[IDX]]] leadDimension 4 : memref<32x4xvector<4xf32>, 3> -> !gpu.mma_matrix<16x16xf16, "COp">
+// CHECK: gpu.subgroup_mma_store_matrix %[[LD]], %[[ALLOC]][%[[I0]], %[[IDX]]] leadDimension 4 : !gpu.mma_matrix<16x16xf16, "COp">, memref<32x4xvector<4xf32>, 3>
// -----
@@ -402,32 +402,32 @@
// CHECK-SAME: (%[[I0:.+]]: index, %[[I1:.+]]: index)
func.func @vectorize_alloc_with_mma_load_store(%i0: index, %i1: index) {
%alloc = memref.alloc() : memref<32x32xf16, 3>
- %0 = gpu.subgroup_mma_load_matrix %alloc[%i0, %i1] {leadDimension = 16 : index} : memref<32x32xf16, 3> -> !gpu.mma_matrix<16x16xf16, "COp">
- gpu.subgroup_mma_store_matrix %0, %alloc[%i0, %i1] {leadDimension = 16 : index} : !gpu.mma_matrix<16x16xf16, "COp">, memref<32x32xf16, 3>
+ %0 = gpu.subgroup_mma_load_matrix %alloc[%i0, %i1] leadDimension 16 : memref<32x32xf16, 3> -> !gpu.mma_matrix<16x16xf16, "COp">
+ gpu.subgroup_mma_store_matrix %0, %alloc[%i0, %i1] leadDimension 16 : !gpu.mma_matrix<16x16xf16, "COp">, memref<32x32xf16, 3>
return
}
// CHECK: affine.apply affine_map<()[s0] -> (s0 floordiv 8)>()
// CHECK: gpu.subgroup_mma_load_matrix
-// CHECK-SAME: leadDimension = 2 : index
+// CHECK-SAME: leadDimension 2
// CHECK: gpu.subgroup_mma_store_matrix
-// CHECK-SAME: leadDimension = 2 : index
+// CHECK-SAME: leadDimension 2
// -----
// CHECK-LABEL: func.func @vectorize_alloc_with_mma_load_store_unaligned_case
func.func @vectorize_alloc_with_mma_load_store_unaligned_case(%i0: index, %i1: index) {
%alloc = memref.alloc() : memref<32x32xf16, 3>
- %0 = gpu.subgroup_mma_load_matrix %alloc[%i0, %i1] {leadDimension = 18 : index} : memref<32x32xf16, 3> -> !gpu.mma_matrix<16x16xf16, "COp">
- gpu.subgroup_mma_store_matrix %0, %alloc[%i0, %i1] {leadDimension = 18 : index} : !gpu.mma_matrix<16x16xf16, "COp">, memref<32x32xf16, 3>
+ %0 = gpu.subgroup_mma_load_matrix %alloc[%i0, %i1] leadDimension 18 : memref<32x32xf16, 3> -> !gpu.mma_matrix<16x16xf16, "COp">
+ gpu.subgroup_mma_store_matrix %0, %alloc[%i0, %i1] leadDimension 18 : !gpu.mma_matrix<16x16xf16, "COp">, memref<32x32xf16, 3>
return
}
// CHECK-NOT: affine.apply
// CHECK: gpu.subgroup_mma_load_matrix
-// CHECK-SAME: leadDimension = 18 : index
+// CHECK-SAME: leadDimension 18
// CHECK: gpu.subgroup_mma_store_matrix
-// CHECK-SAME: leadDimension = 18 : index
+// CHECK-SAME: leadDimension 18
// -----
@@ -485,8 +485,8 @@
%c0 = arith.constant 0 : index
%span0 = hal.interface.binding.subspan layout(#pipeline_layout) binding(0) alignment(64) offset(%c0) flags(ReadOnly) : memref<32x1280xf16, strided<[1280, 1], offset: 11840>, #hal.descriptor_type<storage_buffer>>
%span1 = hal.interface.binding.subspan layout(#pipeline_layout) binding(1) alignment(64) offset(%c0) : memref<32x1280xf16, strided<[1280, 1], offset: 11840>, #hal.descriptor_type<storage_buffer>>
- %val = gpu.subgroup_mma_load_matrix %span0[%i0, %i1] {leadDimension = 1280 : index} : memref<32x1280xf16, strided<[1280, 1], offset: 11840>, #hal.descriptor_type<storage_buffer>> -> !gpu.mma_matrix<16x16xf16, "COp">
- gpu.subgroup_mma_store_matrix %val, %span1[%i0, %i1] {leadDimension = 1280 : index} : !gpu.mma_matrix<16x16xf16, "COp">, memref<32x1280xf16, strided<[1280, 1], offset: 11840>, #hal.descriptor_type<storage_buffer>>
+ %val = gpu.subgroup_mma_load_matrix %span0[%i0, %i1] leadDimension 1280 : memref<32x1280xf16, strided<[1280, 1], offset: 11840>, #hal.descriptor_type<storage_buffer>> -> !gpu.mma_matrix<16x16xf16, "COp">
+ gpu.subgroup_mma_store_matrix %val, %span1[%i0, %i1] leadDimension 1280 : !gpu.mma_matrix<16x16xf16, "COp">, memref<32x1280xf16, strided<[1280, 1], offset: 11840>, #hal.descriptor_type<storage_buffer>>
return
}
@@ -494,8 +494,8 @@
// CHECK: %[[SPAN0:.+]] = hal.interface.binding.subspan {{.+}} offset(%[[C0]]) flags(ReadOnly) : memref<32x160xvector<4xf32>, strided<[160, 1], offset: 1480>, #hal.descriptor_type<storage_buffer>>
// CHECK: %[[SPAN1:.+]] = hal.interface.binding.subspan {{.+}} offset(%[[C0]]) : memref<32x160xvector<4xf32>, strided<[160, 1], offset: 1480>, #hal.descriptor_type<storage_buffer>>
// CHECK: %[[APPLY:.+]] = affine.apply affine_map<()[s0] -> (s0 floordiv 8)>()[%[[I1]]]
-// CHECK: %[[VAL:.+]] = gpu.subgroup_mma_load_matrix %[[SPAN0]][%[[I0]], %[[APPLY]]] {leadDimension = 160 : index}
-// CHECK: gpu.subgroup_mma_store_matrix %[[VAL]], %[[SPAN1]][%[[I0]], %[[APPLY]]] {leadDimension = 160 : index}
+// CHECK: %[[VAL:.+]] = gpu.subgroup_mma_load_matrix %[[SPAN0]][%[[I0]], %[[APPLY]]] leadDimension 160
+// CHECK: gpu.subgroup_mma_store_matrix %[[VAL]], %[[SPAN1]][%[[I0]], %[[APPLY]]] leadDimension 160
// -----
@@ -599,10 +599,10 @@
// CHECK: %[[LOAD2:.+]] = memref.load %[[SUBSPAN]][%[[OFFSET2]]]
// CHECK: %[[OFFSET3:.+]] = affine.apply affine_map<()[s0] -> (s0 floordiv 2 + 3)>()[%[[INDEX]]]
// CHECK: %[[LOAD3:.+]] = memref.load %[[SUBSPAN]][%[[OFFSET3]]]
-// CHECK: %[[INSERT0:.+]] = vector.insert_strided_slice %[[LOAD0]], %[[INIT]] {offsets = [0], strides = [1]} : vector<2xi32> into vector<8xi32>
-// CHECK: %[[INSERT1:.+]] = vector.insert_strided_slice %[[LOAD1]], %[[INSERT0]] {offsets = [2], strides = [1]} : vector<2xi32> into vector<8xi32>
-// CHECK: %[[INSERT2:.+]] = vector.insert_strided_slice %[[LOAD2]], %[[INSERT1]] {offsets = [4], strides = [1]} : vector<2xi32> into vector<8xi32>
-// CHECK: %[[INSERT3:.+]] = vector.insert_strided_slice %[[LOAD3]], %[[INSERT2]] {offsets = [6], strides = [1]} : vector<2xi32> into vector<8xi32>
+// CHECK: %[[INSERT0:.+]] = vector.insert_strided_slice %[[LOAD0]], %[[INIT]] offsets = [0], strides = [1] : vector<2xi32> into vector<8xi32>
+// CHECK: %[[INSERT1:.+]] = vector.insert_strided_slice %[[LOAD1]], %[[INSERT0]] offsets = [2], strides = [1] : vector<2xi32> into vector<8xi32>
+// CHECK: %[[INSERT2:.+]] = vector.insert_strided_slice %[[LOAD2]], %[[INSERT1]] offsets = [4], strides = [1] : vector<2xi32> into vector<8xi32>
+// CHECK: %[[INSERT3:.+]] = vector.insert_strided_slice %[[LOAD3]], %[[INSERT2]] offsets = [6], strides = [1] : vector<2xi32> into vector<8xi32>
// CHECK: return %[[LOAD0]], %[[INSERT3]]
// -----
@@ -626,15 +626,15 @@
// CHECK: %[[OFFSET0:.+]] = affine.apply affine_map<()[s0] -> (s0 floordiv 2)>()[%[[INDEX]]]
// CHECK: memref.store %[[VAL0]], %[[SUBSPAN]][%[[OFFSET0]]]
-// CHECK: %[[SLICE0:.+]] = vector.extract_strided_slice %[[VAL1]] {offsets = [0], sizes = [2], strides = [1]} : vector<8xi32> to vector<2xi32>
+// CHECK: %[[SLICE0:.+]] = vector.extract_strided_slice %[[VAL1]] offsets = [0], sizes = [2], strides = [1] : vector<8xi32> to vector<2xi32>
// CHECK: memref.store %[[SLICE0]], %[[SUBSPAN]][%[[OFFSET0]]]
-// CHECK: %[[SLICE1:.+]] = vector.extract_strided_slice %[[VAL1]] {offsets = [2], sizes = [2], strides = [1]} : vector<8xi32> to vector<2xi32>
+// CHECK: %[[SLICE1:.+]] = vector.extract_strided_slice %[[VAL1]] offsets = [2], sizes = [2], strides = [1] : vector<8xi32> to vector<2xi32>
// CHECK: %[[OFFSET1:.+]] = affine.apply affine_map<()[s0] -> (s0 floordiv 2 + 1)>()[%[[INDEX]]]
// CHECK: memref.store %[[SLICE1]], %[[SUBSPAN]][%[[OFFSET1]]]
-// CHECK: %[[SLICE2:.+]] = vector.extract_strided_slice %[[VAL1]] {offsets = [4], sizes = [2], strides = [1]} : vector<8xi32> to vector<2xi32>
+// CHECK: %[[SLICE2:.+]] = vector.extract_strided_slice %[[VAL1]] offsets = [4], sizes = [2], strides = [1] : vector<8xi32> to vector<2xi32>
// CHECK: %[[OFFSET2:.+]] = affine.apply affine_map<()[s0] -> (s0 floordiv 2 + 2)>()[%[[INDEX]]]
// CHECK: memref.store %[[SLICE2]], %[[SUBSPAN]][%[[OFFSET2]]]
-// CHECK: %[[SLICE3:.+]] = vector.extract_strided_slice %[[VAL1]] {offsets = [6], sizes = [2], strides = [1]} : vector<8xi32> to vector<2xi32>
+// CHECK: %[[SLICE3:.+]] = vector.extract_strided_slice %[[VAL1]] offsets = [6], sizes = [2], strides = [1] : vector<8xi32> to vector<2xi32>
// CHECK: %[[OFFSET3:.+]] = affine.apply affine_map<()[s0] -> (s0 floordiv 2 + 3)>()[%[[INDEX]]]
// CHECK: memref.store %[[SLICE3]], %[[SUBSPAN]][%[[OFFSET3]]]
diff --git a/compiler/src/iree/compiler/Codegen/SPIRV/test/vectorize_matmul.mlir b/compiler/src/iree/compiler/Codegen/SPIRV/test/vectorize_matmul.mlir
index ad195d3..58d9c2b 100644
--- a/compiler/src/iree/compiler/Codegen/SPIRV/test/vectorize_matmul.mlir
+++ b/compiler/src/iree/compiler/Codegen/SPIRV/test/vectorize_matmul.mlir
@@ -172,30 +172,30 @@
// CHECK-COUNT-2: vector.transfer_read %[[LHS]]{{.+}} : tensor<2x128xf16>, vector<8xf16>
// CHECK-COUNT-8: vector.transfer_read %[[RHS]]{{.+}} : tensor<128x8xf16>, vector<8xf16>
// CHECK-COUNT-32: vector.fma {{.+}} : vector<4xf16>
-// CHECK: %[[ISS0:.+]] = vector.insert_strided_slice %{{.+}}, %[[ZERO]] {offsets = [0], strides = [1]} : vector<4xf16> into vector<8xf16>
-// CHECK: %[[ISS1:.+]] = vector.insert_strided_slice %{{.+}}, %[[ISS0]] {offsets = [4], strides = [1]} : vector<4xf16> into vector<8xf16>
-// CHECK: %[[ISS2:.+]] = vector.insert_strided_slice %{{.+}}, %[[ZERO]] {offsets = [0], strides = [1]} : vector<4xf16> into vector<8xf16>
-// CHECK: %[[ISS3:.+]] = vector.insert_strided_slice %{{.+}}, %[[ISS2]] {offsets = [4], strides = [1]} : vector<4xf16> into vector<8xf16>
+// CHECK: %[[ISS0:.+]] = vector.insert_strided_slice %{{.+}}, %[[ZERO]] offsets = [0], strides = [1] : vector<4xf16> into vector<8xf16>
+// CHECK: %[[ISS1:.+]] = vector.insert_strided_slice %{{.+}}, %[[ISS0]] offsets = [4], strides = [1] : vector<4xf16> into vector<8xf16>
+// CHECK: %[[ISS2:.+]] = vector.insert_strided_slice %{{.+}}, %[[ZERO]] offsets = [0], strides = [1] : vector<4xf16> into vector<8xf16>
+// CHECK: %[[ISS3:.+]] = vector.insert_strided_slice %{{.+}}, %[[ISS2]] offsets = [4], strides = [1] : vector<4xf16> into vector<8xf16>
// CHECK: scf.yield %[[ISS1]], %[[ISS3]] : vector<8xf16>, vector<8xf16>
// CHECK: }
// CHECK: %[[X0:.+]] = vector.transfer_read %[[X]]{{.+}} : tensor<2x8xf16>, vector<8xf16>
// CHECK: %[[X1:.+]] = vector.transfer_read %[[X]]{{.+}} : tensor<2x8xf16>, vector<8xf16>
-// CHECK: %[[LHS0:.+]] = vector.extract_strided_slice %[[FOR]]#0 {offsets = [0], sizes = [4], strides = [1]} : vector<8xf16> to vector<4xf16>
-// CHECK: %[[RHS0:.+]] = vector.extract_strided_slice %[[X0]] {offsets = [0], sizes = [4], strides = [1]} : vector<8xf16> to vector<4xf16>
+// CHECK: %[[LHS0:.+]] = vector.extract_strided_slice %[[FOR]]#0 offsets = [0], sizes = [4], strides = [1] : vector<8xf16> to vector<4xf16>
+// CHECK: %[[RHS0:.+]] = vector.extract_strided_slice %[[X0]] offsets = [0], sizes = [4], strides = [1] : vector<8xf16> to vector<4xf16>
// CHECK: %[[DIV0:.+]] = arith.divf %[[LHS0]], %[[RHS0]]
-// CHECK: %[[ISS0:.+]] = vector.insert_strided_slice %[[DIV0]], %[[ZERO]] {offsets = [0], strides = [1]} : vector<4xf16> into vector<8xf16>
-// CHECK: %[[LHS1:.+]] = vector.extract_strided_slice %[[FOR]]#0 {offsets = [4], sizes = [4], strides = [1]} : vector<8xf16> to vector<4xf16>
-// CHECK: %[[RHS1:.+]] = vector.extract_strided_slice %[[X0]] {offsets = [4], sizes = [4], strides = [1]} : vector<8xf16> to vector<4xf16>
+// CHECK: %[[ISS0:.+]] = vector.insert_strided_slice %[[DIV0]], %[[ZERO]] offsets = [0], strides = [1] : vector<4xf16> into vector<8xf16>
+// CHECK: %[[LHS1:.+]] = vector.extract_strided_slice %[[FOR]]#0 offsets = [4], sizes = [4], strides = [1] : vector<8xf16> to vector<4xf16>
+// CHECK: %[[RHS1:.+]] = vector.extract_strided_slice %[[X0]] offsets = [4], sizes = [4], strides = [1] : vector<8xf16> to vector<4xf16>
// CHECK: %[[DIV1:.+]] = arith.divf %[[LHS1]], %[[RHS1]]
-// CHECK: %[[ISS1:.+]] = vector.insert_strided_slice %[[DIV1]], %[[ISS0]] {offsets = [4], strides = [1]} : vector<4xf16> into vector<8xf16>
-// CHECK: %[[LHS2:.+]] = vector.extract_strided_slice %[[FOR]]#1 {offsets = [0], sizes = [4], strides = [1]} : vector<8xf16> to vector<4xf16>
-// CHECK: %[[RHS2:.+]] = vector.extract_strided_slice %[[X1]] {offsets = [0], sizes = [4], strides = [1]} : vector<8xf16> to vector<4xf16>
+// CHECK: %[[ISS1:.+]] = vector.insert_strided_slice %[[DIV1]], %[[ISS0]] offsets = [4], strides = [1] : vector<4xf16> into vector<8xf16>
+// CHECK: %[[LHS2:.+]] = vector.extract_strided_slice %[[FOR]]#1 offsets = [0], sizes = [4], strides = [1] : vector<8xf16> to vector<4xf16>
+// CHECK: %[[RHS2:.+]] = vector.extract_strided_slice %[[X1]] offsets = [0], sizes = [4], strides = [1] : vector<8xf16> to vector<4xf16>
// CHECK: %[[DIV2:.+]] = arith.divf %[[LHS2]], %[[RHS2]]
-// CHECK: %[[ISS2:.+]] = vector.insert_strided_slice %[[DIV2]], %[[ZERO]] {offsets = [0], strides = [1]} : vector<4xf16> into vector<8xf16>
-// CHECK: %[[LHS3:.+]] = vector.extract_strided_slice %[[FOR]]#1 {offsets = [4], sizes = [4], strides = [1]} : vector<8xf16> to vector<4xf16>
-// CHECK: %[[RHS3:.+]] = vector.extract_strided_slice %[[X1]] {offsets = [4], sizes = [4], strides = [1]} : vector<8xf16> to vector<4xf16>
+// CHECK: %[[ISS2:.+]] = vector.insert_strided_slice %[[DIV2]], %[[ZERO]] offsets = [0], strides = [1] : vector<4xf16> into vector<8xf16>
+// CHECK: %[[LHS3:.+]] = vector.extract_strided_slice %[[FOR]]#1 offsets = [4], sizes = [4], strides = [1] : vector<8xf16> to vector<4xf16>
+// CHECK: %[[RHS3:.+]] = vector.extract_strided_slice %[[X1]] offsets = [4], sizes = [4], strides = [1] : vector<8xf16> to vector<4xf16>
// CHECK: %[[DIV3:.+]] = arith.divf %[[LHS3]], %[[RHS3]]
-// CHECK: %[[ISS3:.+]] = vector.insert_strided_slice %[[DIV3]], %[[ISS2]] {offsets = [4], strides = [1]} : vector<4xf16> into vector<8xf16>
+// CHECK: %[[ISS3:.+]] = vector.insert_strided_slice %[[DIV3]], %[[ISS2]] offsets = [4], strides = [1] : vector<4xf16> into vector<8xf16>
// CHECK: %[[W0:.+]] = vector.transfer_write %[[ISS1]], %[[Y]][%c0, %c0] {in_bounds = [true]} : vector<8xf16>, tensor<2x8xf16>
// CHECK: %[[W1:.+]] = vector.transfer_write %[[ISS3]], %[[W0]][%c1, %c0] {in_bounds = [true]} : vector<8xf16>, tensor<2x8xf16>
// CHECK: return %[[W1]]
diff --git a/third_party/llvm-project b/third_party/llvm-project
index d37fa5a..d98828d 160000
--- a/third_party/llvm-project
+++ b/third_party/llvm-project
@@ -1 +1 @@
-Subproject commit d37fa5a838db382c4138e9612616cb0ac4ef448a
+Subproject commit d98828d394e4967148f6992afc3f23662a8e17a8
