Update riscv.md (#7012)

docs/website/docs/building-from-source/riscv.md

diff --git a/docs/website/docs/building-from-source/riscv.md b/docs/website/docs/building-from-source/riscv.md
index 3d172f6..c8d06e4 100644
--- a/docs/website/docs/building-from-source/riscv.md
+++ b/docs/website/docs/building-from-source/riscv.md
@@ -148,8 +148,8 @@
   -iree-llvm-target-triple=riscv64 \
   -iree-llvm-target-cpu=generic-rv64 \
   -iree-llvm-target-abi=lp64d \
-  -iree-llvm-target-cpu-features="+m,+a,+f,+experimental-v" \
-  -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 \
+  -iree-llvm-target-cpu-features="+m,+a,+f,+d,+experimental-v" \
+  -riscv-v-vector-bits-min=256 -riscv-v-fixed-length-vector-lmul-max=8 \
   iree_input.mlir -o mobilenet-dylib.vmfb
 ```