Reduce default tile size used by default to 64 from 128 to expose more parallelism (#6752)
diff --git a/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp b/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp index a74a175..f65e912 100644 --- a/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp +++ b/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp
@@ -79,7 +79,7 @@ "iree-codegen-llvm-generic-ops-workgroup-size", llvm::cl::desc( "linalg.generic and linalg.indexed_generic workgroup tile size"), - llvm::cl::init(128)); + llvm::cl::init(64)); /// Sets the lowering configuration for dispatch region with root op that /// implements the contraction operation interface.
diff --git a/iree/compiler/Codegen/LLVMCPU/test/materialize_launch_configuration.mlir b/iree/compiler/Codegen/LLVMCPU/test/materialize_launch_configuration.mlir index ba0ee07..9c8a4c1 100644 --- a/iree/compiler/Codegen/LLVMCPU/test/materialize_launch_configuration.mlir +++ b/iree/compiler/Codegen/LLVMCPU/test/materialize_launch_configuration.mlir
@@ -169,8 +169,8 @@ } } } -// CHECK-DAG: #[[CONFIG:.+]] = {tileSizes = {{\[}}[128, 128]{{\]}}} -// CHECK-DAG: #[[MAP0:.+]] = affine_map<()[s0] -> (s0 ceildiv 128)> +// CHECK-DAG: #[[CONFIG:.+]] = {tileSizes = {{\[}}[64, 64]{{\]}}} +// CHECK-DAG: #[[MAP0:.+]] = affine_map<()[s0] -> (s0 ceildiv 64)> // CHECK: hal.executable.entry_point @add // CHECK-NEXT: (%[[ARG0:[a-zA-Z0-9_]+]]: index // CHECK-SAME: %[[ARG1:[a-zA-Z0-9_]+]]: index @@ -265,8 +265,8 @@ } } } -// CHECK-DAG: #[[CONFIG:.+]] = {tileSizes = {{\[}}[0, 128, 128, 128]{{\]}}} -// CHECK-DAG: #[[MAP0:.+]] = affine_map<()[s0] -> (s0 ceildiv 128)> +// CHECK-DAG: #[[CONFIG:.+]] = {tileSizes = {{\[}}[0, 64, 64, 64]{{\]}}} +// CHECK-DAG: #[[MAP0:.+]] = affine_map<()[s0] -> (s0 ceildiv 64)> // CHECK: hal.executable.entry_point @add4D // CHECK-NEXT: (%[[ARG0:[a-zA-Z0-9_]+]]: index // CHECK-SAME: %[[ARG1:[a-zA-Z0-9_]+]]: index