| commit | 4e9b3bdb39dd7eb8d63b4fefa22d86d460261564 | [log] [tgz] |
|---|---|---|
| author | Cullen Rhodes <cullen.rhodes@arm.com> | Wed Jun 07 18:23:57 2023 +0100 |
| committer | GitHub <noreply@github.com> | Wed Jun 07 10:23:57 2023 -0700 |
| tree | 86be44db5fc29c50be1b5a110148eebba2facde4 | |
| parent | 0b91c98ce58f34ba6098b591c9a5879f3a679f52 [diff] |
[LLVMCPU] Add pass to enable Armv9 Streaming SVE mode (#13558)
This patch adds a pass 'iree-llvmcpu-enable-aarch64-ssve' that enables the Armv9 Scalable Matrix Extension (SME) Streaming SVE (SSVE) mode [1].
SSVE is enabled in the LLVM backend at the function boundary by specifying one of the following attributes [2]:
aarch64_pstate_sm_enabled - calls to functions with this attribute are
wrapped with 'smstart sm' / 'smstop sm' [3].
Changes the function ABI.
aarch64_pstate_sm_body - 'smstart sm' / 'smstop sm' are emitted in the
function prologue / epilogue for functions
marked with this attribute. This is internal
and doesn't change the function ABI.
This pass adds the 'aarch64_pstate_sm_body' attribute to functions via the passthrough mechanism [4].
This attribute is used because PSTATE.SM changes are kept internal to the function and the purpose of this pass is to enable SSVE for dispatch functions which are called by the IREE runtime. The AAPCS64 [5] states it is the caller's responsibility to ensure that PSTATE.SM has a valid value on entry to a callee, the 'aarch64_pstate_sm_enabled' attribute would change the function ABI forcing the caller (IREE runtime) to be responsible for managing PSTATE.SM before entry/exit. At present, the runtime doesn't know the details of dispatches such that it could emit these instructions.
The pass is enabled for AArch64 when SVE(2) and SME are enabled for the following lowering configurations:
* CPUBufferOpsTileAndVectorize
* CPUDoubleTilingPeelingExpert
* CPUConvTileAndDecomposeExpert
These configurations were chosen simply because they're used in one of our pipelines.
[1] https://developer.arm.com/documentation/ddi0616/aa
[2] https://llvm.org/docs/AArch64SME.html
[3] https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/SMSTART--Enables-access-to-Streaming-SVE-mode-and-SME-architectural-state--an-alias-of-MSR--immediate--
[4] https://mlir.llvm.org/docs/Dialects/LLVM/#attribute-pass-through
[5] https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#671pstatesm-interfacesIREE (Intermediate Representation Execution Environment, pronounced as “eerie”) is an MLIR-based end-to-end compiler and runtime that lowers Machine Learning (ML) models to a unified IR that scales up to meet the needs of the datacenter and down to satisfy the constraints and special considerations of mobile and edge deployments.
See our website for project details, user guides, and instructions on building from source.
IREE is still in its early phase. We have settled down on the overarching infrastructure and are actively improving various software components as well as project logistics. It is still quite far from ready for everyday use and is made available without any support at the moment. With that said, we welcome any kind of feedback on any communication channels!
See our website for more information.
IREE is licensed under the terms of the Apache 2.0 License with LLVM Exceptions. See LICENSE for more information.