)]}'
{
  "commit": "4e9b3bdb39dd7eb8d63b4fefa22d86d460261564",
  "tree": "86be44db5fc29c50be1b5a110148eebba2facde4",
  "parents": [
    "0b91c98ce58f34ba6098b591c9a5879f3a679f52"
  ],
  "author": {
    "name": "Cullen Rhodes",
    "email": "cullen.rhodes@arm.com",
    "time": "Wed Jun 07 18:23:57 2023 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Jun 07 10:23:57 2023 -0700"
  },
  "message": "[LLVMCPU] Add pass to enable Armv9 Streaming SVE mode (#13558)\n\nThis patch adds a pass \u0027iree-llvmcpu-enable-aarch64-ssve\u0027 that enables the Armv9 Scalable Matrix Extension (SME) Streaming SVE (SSVE) mode [1].\r\n\r\nSSVE is enabled in the LLVM backend at the function boundary by specifying one of the following attributes [2]:\r\n\r\n  aarch64_pstate_sm_enabled - calls to functions with this attribute are\r\n                              wrapped with \u0027smstart sm\u0027 / \u0027smstop sm\u0027 [3].\r\n                              Changes the function ABI.\r\n\r\n  aarch64_pstate_sm_body    - \u0027smstart sm\u0027 / \u0027smstop sm\u0027 are emitted in the\r\n                              function prologue / epilogue for functions\r\n                              marked with this attribute. This is internal\r\n                              and doesn\u0027t change the function ABI.\r\n\r\nThis pass adds the \u0027aarch64_pstate_sm_body\u0027 attribute to functions via the passthrough mechanism [4].\r\n\r\nThis attribute is used because PSTATE.SM changes are kept internal to the function and the purpose of this pass is to enable SSVE for dispatch functions which are called by the IREE runtime. The AAPCS64 [5] states it is the caller\u0027s responsibility to ensure that PSTATE.SM has a valid value on entry to a callee, the \u0027aarch64_pstate_sm_enabled\u0027 attribute would change the function ABI forcing the caller (IREE runtime) to be responsible for managing PSTATE.SM before entry/exit. At present, the runtime doesn\u0027t know the details of dispatches such that it could emit these instructions.\r\n\r\nThe pass is enabled for AArch64 when SVE(2) and SME are enabled for the following lowering configurations:\r\n\r\n  * CPUBufferOpsTileAndVectorize\r\n  * CPUDoubleTilingPeelingExpert\r\n  * CPUConvTileAndDecomposeExpert\r\n\r\nThese configurations were chosen simply because they\u0027re used in one of our pipelines.\r\n\r\n[1] https://developer.arm.com/documentation/ddi0616/aa\r\n[2] https://llvm.org/docs/AArch64SME.html\r\n[3] https://developer.arm.com/documentation/ddi0602/2023-03/Base-Instructions/SMSTART--Enables-access-to-Streaming-SVE-mode-and-SME-architectural-state--an-alias-of-MSR--immediate--\r\n[4] https://mlir.llvm.org/docs/Dialects/LLVM/#attribute-pass-through\r\n[5] https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#671pstatesm-interfaces",
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