Integrate LLVM to llvm/llvm-project@03ddfac14e84 (#25082) IREE has been adapted to the LLVM API changes (assisted by Claude Code, manually reviewed): Adaption in iree-tblgen source to definitions being a list of definitions after 80017ba18d8c TableGen: Store classes and defs in a StringMap (#231573). Adaption to new header for arith::populateCeilFloorDivExpandOpsPatterns after 076bd55e20d9 [mlir][Arith] Move ceil/floor div expansion to Conversion/ArithCommon. NFC (#231064). Support xnack on/off for ROCM gfx125x, following 05e432a8597f [AMDGPU] Support xnack on/off on gfx125x (#232080). Remove the workaround that always turns off XNACK for gfx1250. Signed-off-by: Stefan Schuermans <schuermans@roofline.ai>
diff --git a/compiler/plugins/target/ROCM/BUILD.bazel b/compiler/plugins/target/ROCM/BUILD.bazel index ce4981f..c1f8452 100644 --- a/compiler/plugins/target/ROCM/BUILD.bazel +++ b/compiler/plugins/target/ROCM/BUILD.bazel
@@ -51,7 +51,6 @@ "//runtime/src/iree/schemas:hip_executable_def_c_fbs", "@llvm-project//llvm:AMDGPUCodeGen", "@llvm-project//llvm:Analysis", - "@llvm-project//llvm:BinaryFormat", "@llvm-project//llvm:BitWriter", "@llvm-project//llvm:Core", "@llvm-project//llvm:FrontendOffloading",
diff --git a/compiler/plugins/target/ROCM/CMakeLists.txt b/compiler/plugins/target/ROCM/CMakeLists.txt index ccc7ac2..59e3107 100644 --- a/compiler/plugins/target/ROCM/CMakeLists.txt +++ b/compiler/plugins/target/ROCM/CMakeLists.txt
@@ -28,7 +28,6 @@ DEPS LLVMAMDGPUCodeGen LLVMAnalysis - LLVMBinaryFormat LLVMBitWriter LLVMCore LLVMFrontendOffloading
diff --git a/compiler/plugins/target/ROCM/ROCMTarget.cpp b/compiler/plugins/target/ROCM/ROCMTarget.cpp index f42fbb5..c8b1493 100644 --- a/compiler/plugins/target/ROCM/ROCMTarget.cpp +++ b/compiler/plugins/target/ROCM/ROCMTarget.cpp
@@ -38,7 +38,6 @@ #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/Analysis/TargetTransformInfo.h" -#include "llvm/BinaryFormat/ELF.h" #include "llvm/Bitcode/BitcodeWriter.h" #include "llvm/Frontend/Offloading/Utility.h" #include "llvm/IR/Constants.h" @@ -50,7 +49,6 @@ #include "llvm/Passes/PassBuilder.h" #include "llvm/Passes/StandardInstrumentations.h" #include "llvm/Support/CommandLine.h" -#include "llvm/Support/Endian.h" #include "llvm/Support/FormatVariadic.h" #include "llvm/Support/TargetSelect.h" #include "llvm/Target/TargetMachine.h" @@ -1133,19 +1131,6 @@ return failure(); } - // LLVM a86b58566a25 started encoding gfx1250's hardwired XNACK as - // XNACK_ON in ELF e_flags. ROCm then looks for a gfx1250:xnack+ - // target, which the runtime does not register. Keep the pre-existing - // encoding for this non-selectable feature until LLVM's ELF emission - // is corrected. This does not change the kernel's XNACK codegen. - if (targetArch == "gfx1250") { - char *flags = - targetHSACO.data() + offsetof(llvm::ELF::Elf64_Ehdr, e_flags); - llvm::support::endian::write32le( - flags, llvm::support::endian::read32le(flags) & - ~llvm::ELF::EF_AMDGPU_FEATURE_XNACK_V4); - } - if (targetOptions.enableRegSpillWarning) { checkRegisterSpilling(variantOp, targetObj); }
diff --git a/compiler/plugins/target/ROCM/test/default_subgroup_size.mlir b/compiler/plugins/target/ROCM/test/default_subgroup_size.mlir index ad3f03a..c7a65a8 100644 --- a/compiler/plugins/target/ROCM/test/default_subgroup_size.mlir +++ b/compiler/plugins/target/ROCM/test/default_subgroup_size.mlir
@@ -18,13 +18,12 @@ // export does not specify one. CDNA5 only supports wave32; asking LLVM for // wave64 silently produces an executable with no kernels. -// The ELF target ID must not require selectable XNACK on CDNA5. Check the -// little-endian e_flags at byte offset 48: gfx1250 (0x49), SRAMECC any -// (0x400), and XNACK unsupported (0x0). -// ELF: data = dense<"0x7F454C46{{([0-9A-F]{88})}}49040000 +// CDNA5 has selectable XNACK, so the ELF target ID keeps the XNACK feature +// bits. Check the little-endian e_flags at byte offset 48: gfx1250 (0x49), +// SRAMECC any (0x400), and XNACK any (0x100). +// ELF: data = dense<"0x7F454C46{{([0-9A-F]{88})}}49050000 -// Targets with selectable XNACK must retain their feature bits: gfx942 -// (0x4c), SRAMECC any (0x400), and XNACK any (0x100). +// Likewise for gfx942: (0x4c), SRAMECC any (0x400), and XNACK any (0x100). // RUN: iree-opt --iree-hal-transformation-pipeline --iree-hal-target-device=hip \ // RUN: --iree-rocm-target=gfx942 --iree-rocm-container-type=hsaco %s | FileCheck %s --check-prefix=ELF-CDNA3 // ELF-CDNA3: data = dense<"0x7F454C46{{([0-9A-F]{88})}}4C050000
diff --git a/compiler/plugins/target/ROCM/test/target_feature_serialization.mlir b/compiler/plugins/target/ROCM/test/target_feature_serialization.mlir index d5c1f9f..09db9f1 100644 --- a/compiler/plugins/target/ROCM/test/target_feature_serialization.mlir +++ b/compiler/plugins/target/ROCM/test/target_feature_serialization.mlir
@@ -54,13 +54,25 @@ // IR-ECCOFF-DAG: !{i32 1, !"amdgpu.sramecc", i32 0} // IR-ECCOFF-DAG: !{i32 1, !"amdgpu.xnack", i32 1} -// RUN: not iree-opt --iree-hal-transformation-pipeline --iree-hal-target-device=hip \ -// RUN: --iree-rocm-target=mi455x --iree-rocm-target-features=-xnack %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=CDNA5OFF -// CDNA5OFF: invalid ROCM target ID 'gfx1250:xnack-' +// gfx1250 supports selectable XNACK on/off modes (LLVM 05e432a8597f), so these +// target IDs are valid and the modes reach LLVM as module flags. +// RUN: rm -rf %t && mkdir -p %t +// RUN: iree-opt --iree-hal-transformation-pipeline --iree-hal-target-device=hip \ +// RUN: --iree-rocm-target=mi455x --iree-rocm-target-features=-xnack \ +// RUN: --iree-hal-dump-executable-intermediates-to=%t --iree-rocm-container-type=hsaco %s | FileCheck %s --check-prefix=ELF-CDNA5OFF +// RUN: cat %t/*.linked.ll | FileCheck %s --check-prefix=IR-CDNA5OFF +// ELF-CDNA5OFF: data = dense<"0x7F454C46{{([0-9A-F]{88})}}49060000 +// IR-CDNA5OFF: target triple = "amdgpu12.50-amd-amdhsa" +// IR-CDNA5OFF-DAG: !{i32 1, !"amdgpu.xnack", i32 0} -// RUN: not iree-opt --iree-hal-transformation-pipeline --iree-hal-target-device=hip \ -// RUN: --iree-rocm-target=cdna5 --iree-rocm-target-features=+xnack %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=CDNA5ON -// CDNA5ON: invalid ROCM target ID 'gfx1250:xnack+' +// RUN: rm -rf %t && mkdir -p %t +// RUN: iree-opt --iree-hal-transformation-pipeline --iree-hal-target-device=hip \ +// RUN: --iree-rocm-target=cdna5 --iree-rocm-target-features=+xnack \ +// RUN: --iree-hal-dump-executable-intermediates-to=%t --iree-rocm-container-type=hsaco %s | FileCheck %s --check-prefix=ELF-CDNA5ON +// RUN: cat %t/*.linked.ll | FileCheck %s --check-prefix=IR-CDNA5ON +// ELF-CDNA5ON: data = dense<"0x7F454C46{{([0-9A-F]{88})}}49070000 +// IR-CDNA5ON: target triple = "amdgpu12.50-amd-amdhsa" +// IR-CDNA5ON-DAG: !{i32 1, !"amdgpu.xnack", i32 1} // RUN: not iree-opt --iree-hal-transformation-pipeline --iree-hal-target-device=hip \ // RUN: --iree-rocm-target=gfx1100 --iree-rocm-target-features=+sramecc %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=INVALIDFEATURE
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/BUILD.bazel b/compiler/src/iree/compiler/Codegen/LLVMGPU/BUILD.bazel index dc6a9d4..3845321 100644 --- a/compiler/src/iree/compiler/Codegen/LLVMGPU/BUILD.bazel +++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/BUILD.bazel
@@ -202,6 +202,7 @@ "@llvm-project//mlir:AffineToStandard", "@llvm-project//mlir:AffineTransforms", "@llvm-project//mlir:Analysis", + "@llvm-project//mlir:ArithCommonConversion", "@llvm-project//mlir:ArithDialect", "@llvm-project//mlir:ArithToAMDGPU", "@llvm-project//mlir:ArithToLLVM",
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/CMakeLists.txt b/compiler/src/iree/compiler/Codegen/LLVMGPU/CMakeLists.txt index a389166..59d8522 100644 --- a/compiler/src/iree/compiler/Codegen/LLVMGPU/CMakeLists.txt +++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/CMakeLists.txt
@@ -138,6 +138,7 @@ MLIRAffineToStandard MLIRAffineTransforms MLIRAnalysis + MLIRArithCommonConversion MLIRArithDialect MLIRArithToAMDGPU MLIRArithToLLVM
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/ConvertToNVVM.cpp b/compiler/src/iree/compiler/Codegen/LLVMGPU/ConvertToNVVM.cpp index 6ccd0f6..b9d7982 100644 --- a/compiler/src/iree/compiler/Codegen/LLVMGPU/ConvertToNVVM.cpp +++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/ConvertToNVVM.cpp
@@ -11,6 +11,7 @@ #include "iree/compiler/Codegen/Dialect/GPU/IR/IREEGPUOps.h" #include "iree/compiler/Codegen/LLVMGPU/ConvertToLLVM.h" #include "iree/compiler/Codegen/Utils/GPUUtils.h" +#include "mlir/Conversion/ArithCommon/CeilFloorDivExpansion.h" #include "mlir/Conversion/ArithToLLVM/ArithToLLVM.h" #include "mlir/Conversion/ComplexToLLVM/ComplexToLLVM.h" #include "mlir/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.h"
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/ConvertToROCDL.cpp b/compiler/src/iree/compiler/Codegen/LLVMGPU/ConvertToROCDL.cpp index 7b62de0..329305b 100644 --- a/compiler/src/iree/compiler/Codegen/LLVMGPU/ConvertToROCDL.cpp +++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/ConvertToROCDL.cpp
@@ -15,6 +15,7 @@ #include "iree/compiler/Codegen/Utils/GPUUtils.h" #include "llvm/Support/DebugLog.h" #include "mlir/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.h" +#include "mlir/Conversion/ArithCommon/CeilFloorDivExpansion.h" #include "mlir/Conversion/ArithToAMDGPU/ArithToAMDGPU.h" #include "mlir/Conversion/ArithToLLVM/ArithToLLVM.h" #include "mlir/Conversion/ComplexToLLVM/ComplexToLLVM.h"
diff --git a/compiler/src/iree/compiler/Codegen/SPIRV/BUILD.bazel b/compiler/src/iree/compiler/Codegen/SPIRV/BUILD.bazel index 201158f..eae0c9d 100644 --- a/compiler/src/iree/compiler/Codegen/SPIRV/BUILD.bazel +++ b/compiler/src/iree/compiler/Codegen/SPIRV/BUILD.bazel
@@ -116,6 +116,7 @@ "@llvm-project//mlir:AffineToStandard", "@llvm-project//mlir:AffineUtils", "@llvm-project//mlir:Analysis", + "@llvm-project//mlir:ArithCommonConversion", "@llvm-project//mlir:ArithDialect", "@llvm-project//mlir:ArithToSPIRV", "@llvm-project//mlir:ArithTransforms",
diff --git a/compiler/src/iree/compiler/Codegen/SPIRV/CMakeLists.txt b/compiler/src/iree/compiler/Codegen/SPIRV/CMakeLists.txt index ec2e172..6dc446e 100644 --- a/compiler/src/iree/compiler/Codegen/SPIRV/CMakeLists.txt +++ b/compiler/src/iree/compiler/Codegen/SPIRV/CMakeLists.txt
@@ -85,6 +85,7 @@ MLIRAffineToStandard MLIRAffineUtils MLIRAnalysis + MLIRArithCommonConversion MLIRArithDialect MLIRArithToSPIRV MLIRArithTransforms
diff --git a/compiler/src/iree/compiler/Codegen/SPIRV/ConvertToSPIRV.cpp b/compiler/src/iree/compiler/Codegen/SPIRV/ConvertToSPIRV.cpp index bb8c85a..046be2b 100644 --- a/compiler/src/iree/compiler/Codegen/SPIRV/ConvertToSPIRV.cpp +++ b/compiler/src/iree/compiler/Codegen/SPIRV/ConvertToSPIRV.cpp
@@ -26,6 +26,7 @@ #include "llvm/ADT/DenseSet.h" #include "llvm/ADT/STLExtras.h" #include "llvm/Support/FormatVariadic.h" +#include "mlir/Conversion/ArithCommon/CeilFloorDivExpansion.h" #include "mlir/Conversion/ArithToSPIRV/ArithToSPIRV.h" #include "mlir/Conversion/ComplexToSPIRV/ComplexToSPIRV.h" #include "mlir/Conversion/ControlFlowToSPIRV/ControlFlowToSPIRVPass.h"
diff --git a/compiler/src/iree/compiler/Dialect/VM/Transforms/BUILD.bazel b/compiler/src/iree/compiler/Dialect/VM/Transforms/BUILD.bazel index c290963..87e3cdc 100644 --- a/compiler/src/iree/compiler/Dialect/VM/Transforms/BUILD.bazel +++ b/compiler/src/iree/compiler/Dialect/VM/Transforms/BUILD.bazel
@@ -64,6 +64,7 @@ "@llvm-project//mlir:AffineTransforms", "@llvm-project//mlir:AffineUtils", "@llvm-project//mlir:Analysis", + "@llvm-project//mlir:ArithCommonConversion", "@llvm-project//mlir:ArithTransforms", "@llvm-project//mlir:ControlFlowInterfaces", "@llvm-project//mlir:FuncDialect",
diff --git a/compiler/src/iree/compiler/Dialect/VM/Transforms/CMakeLists.txt b/compiler/src/iree/compiler/Dialect/VM/Transforms/CMakeLists.txt index 3dabab6..1fe9253 100644 --- a/compiler/src/iree/compiler/Dialect/VM/Transforms/CMakeLists.txt +++ b/compiler/src/iree/compiler/Dialect/VM/Transforms/CMakeLists.txt
@@ -40,6 +40,7 @@ MLIRAffineTransforms MLIRAffineUtils MLIRAnalysis + MLIRArithCommonConversion MLIRArithTransforms MLIRControlFlowInterfaces MLIRFuncDialect
diff --git a/compiler/src/iree/compiler/Dialect/VM/Transforms/Conversion.cpp b/compiler/src/iree/compiler/Dialect/VM/Transforms/Conversion.cpp index b259137..57202af 100644 --- a/compiler/src/iree/compiler/Dialect/VM/Transforms/Conversion.cpp +++ b/compiler/src/iree/compiler/Dialect/VM/Transforms/Conversion.cpp
@@ -18,6 +18,7 @@ #include "iree/compiler/Dialect/VM/Transforms/Passes.h" #include "llvm/ADT/STLExtras.h" #include "mlir/Conversion/AffineToStandard/AffineToStandard.h" +#include "mlir/Conversion/ArithCommon/CeilFloorDivExpansion.h" #include "mlir/Dialect/Affine/IR/AffineOps.h" #include "mlir/Dialect/Arith/Transforms/Passes.h" #include "mlir/Dialect/Func/IR/FuncOps.h"
diff --git a/third_party/llvm-project b/third_party/llvm-project index 6be0220..03ddfac 160000 --- a/third_party/llvm-project +++ b/third_party/llvm-project
@@ -1 +1 @@ -Subproject commit 6be022066fd2a5139fc094d90f1b59795b2fd00f +Subproject commit 03ddfac14e84ebaea0dc8a1a79ea28b09287fb5b
diff --git a/tools/iree-tblgen.cpp b/tools/iree-tblgen.cpp index 2f12773..299a92f 100644 --- a/tools/iree-tblgen.cpp +++ b/tools/iree-tblgen.cpp
@@ -418,8 +418,8 @@ std::vector<const Record*> defs; for (const auto& def : records.getDefs()) { - if (def.second->isSubClassOf(classDef)) { - defs.push_back(def.second.get()); + if (def->isSubClassOf(classDef)) { + defs.push_back(def); } } return defs; @@ -435,8 +435,8 @@ std::vector<const Record*> defs; for (const auto& def : records.getDefs()) { - if (def.second->isSubClassOf(classDef)) { - defs.push_back(def.second.get()); + if (def->isSubClassOf(classDef)) { + defs.push_back(def); } } return defs; @@ -452,8 +452,8 @@ std::vector<const Record*> defs; for (const auto& def : records.getDefs()) { - if (def.second->isSubClassOf(classDef)) { - defs.push_back(def.second.get()); + if (def->isSubClassOf(classDef)) { + defs.push_back(def); } } return defs; @@ -473,14 +473,14 @@ } for (const auto& def : records.getDefs()) { - if (def.second->isSubClassOf(classDef)) { + if (def->isSubClassOf(classDef)) { // Skip anonymous records generated by DeclareInterfaceMethods helpers. // These are implementation details that duplicate named interfaces. - StringRef name = def.second->getName(); + StringRef name = def->getName(); if (name.starts_with("anonymous_")) { continue; } - defs.push_back(def.second.get()); + defs.push_back(def); } } }