| ################################################################################ |
| # Autogenerated by build_tools/bazel_to_cmake/bazel_to_cmake.py from # |
| # tests/e2e/tosa_ops/BUILD.bazel # |
| # # |
| # Use iree_cmake_extra_content from iree/build_defs.oss.bzl to add arbitrary # |
| # CMake-only content. # |
| # # |
| # To disable autogeneration for this file entirely, delete this header. # |
| ################################################################################ |
| |
| iree_add_all_subdirs() |
| |
| iree_check_single_backend_test_suite( |
| NAME |
| check_llvm-cpu_local-task |
| SRCS |
| "abs.mlir" |
| "add.mlir" |
| "arithmetic_right_shift.mlir" |
| "bitwise_and.mlir" |
| "bitwise_or.mlir" |
| "bitwise_xor.mlir" |
| "ceil.mlir" |
| "clamp.mlir" |
| "clz.mlir" |
| "const.mlir" |
| "equal.mlir" |
| "exp.mlir" |
| "floor.mlir" |
| "fully_connected.mlir" |
| "gather.mlir" |
| "greater.mlir" |
| "greater_equal.mlir" |
| "if.mlir" |
| "log.mlir" |
| "logical_left_shift.mlir" |
| "logical_right_shift.mlir" |
| "logical_right_shift_16.mlir" |
| "matmul.mlir" |
| "max_pool.mlir" |
| "maximum.mlir" |
| "minimum.mlir" |
| "mul.mlir" |
| "mul_shift.mlir" |
| "negate.mlir" |
| "pad.mlir" |
| "reciprocal.mlir" |
| "reduce.mlir" |
| "reshape.mlir" |
| "rsqrt.mlir" |
| "select.mlir" |
| "sigmoid.mlir" |
| "sub.mlir" |
| "table.mlir" |
| "tanh.mlir" |
| "transpose.mlir" |
| "while.mlir" |
| TARGET_BACKEND |
| "llvm-cpu" |
| DRIVER |
| "local-task" |
| INPUT_TYPE |
| "tosa" |
| ) |
| |
| iree_check_single_backend_test_suite( |
| NAME |
| check_vmvx_local-task |
| SRCS |
| "abs.mlir" |
| "add.mlir" |
| "arithmetic_right_shift.mlir" |
| "bitwise_and.mlir" |
| "bitwise_or.mlir" |
| "bitwise_xor.mlir" |
| "ceil.mlir" |
| "clamp.mlir" |
| "clz.mlir" |
| "const.mlir" |
| "equal.mlir" |
| "exp.mlir" |
| "floor.mlir" |
| "fully_connected.mlir" |
| "gather.mlir" |
| "greater.mlir" |
| "greater_equal.mlir" |
| "if.mlir" |
| "log.mlir" |
| "logical_left_shift.mlir" |
| "logical_right_shift.mlir" |
| "logical_right_shift_16.mlir" |
| "matmul.mlir" |
| "max_pool.mlir" |
| "maximum.mlir" |
| "minimum.mlir" |
| "mul.mlir" |
| "mul_shift.mlir" |
| "negate.mlir" |
| "pad.mlir" |
| "reciprocal.mlir" |
| "reshape.mlir" |
| "rsqrt.mlir" |
| "select.mlir" |
| "sigmoid.mlir" |
| "sub.mlir" |
| "table.mlir" |
| "tanh.mlir" |
| "transpose.mlir" |
| "while.mlir" |
| TARGET_BACKEND |
| "vmvx" |
| DRIVER |
| "local-task" |
| INPUT_TYPE |
| "tosa" |
| ) |
| |
| iree_check_single_backend_test_suite( |
| NAME |
| check_vmvx_local-sync_microkernels |
| SRCS |
| "abs.mlir" |
| "add.mlir" |
| "arithmetic_right_shift.mlir" |
| "bitwise_and.mlir" |
| "bitwise_or.mlir" |
| "bitwise_xor.mlir" |
| "ceil.mlir" |
| "clamp.mlir" |
| "clz.mlir" |
| "const.mlir" |
| "equal.mlir" |
| "exp.mlir" |
| "floor.mlir" |
| "fully_connected.mlir" |
| "gather.mlir" |
| "greater.mlir" |
| "greater_equal.mlir" |
| "if.mlir" |
| "log.mlir" |
| "logical_left_shift.mlir" |
| "logical_right_shift.mlir" |
| "logical_right_shift_16.mlir" |
| "matmul.mlir" |
| "max_pool.mlir" |
| "maximum.mlir" |
| "minimum.mlir" |
| "mul.mlir" |
| "mul_shift.mlir" |
| "negate.mlir" |
| "pad.mlir" |
| "reciprocal.mlir" |
| "reduce.mlir" |
| "reshape.mlir" |
| "rsqrt.mlir" |
| "select.mlir" |
| "sigmoid.mlir" |
| "sub.mlir" |
| "table.mlir" |
| "tanh.mlir" |
| "transpose.mlir" |
| "while.mlir" |
| TARGET_BACKEND |
| "vmvx" |
| DRIVER |
| "local-sync" |
| COMPILER_FLAGS |
| "--iree-vmvx-enable-microkernels" |
| INPUT_TYPE |
| "tosa" |
| ) |
| |
| iree_check_single_backend_test_suite( |
| NAME |
| check_vulkan-spirv_vulkan |
| SRCS |
| "abs.mlir" |
| "add.mlir" |
| "arithmetic_right_shift.mlir" |
| "bitwise_and.mlir" |
| "bitwise_or.mlir" |
| "bitwise_xor.mlir" |
| "ceil.mlir" |
| "clamp.mlir" |
| "clz.mlir" |
| "const.mlir" |
| "equal.mlir" |
| "exp.mlir" |
| "floor.mlir" |
| "fully_connected.mlir" |
| "gather.mlir" |
| "greater.mlir" |
| "greater_equal.mlir" |
| "if.mlir" |
| "log.mlir" |
| "logical_left_shift.mlir" |
| "logical_right_shift.mlir" |
| "matmul.mlir" |
| "max_pool.mlir" |
| "maximum.mlir" |
| "minimum.mlir" |
| "mul.mlir" |
| "mul_shift.mlir" |
| "negate.mlir" |
| "pad.mlir" |
| "reciprocal.mlir" |
| "reduce.mlir" |
| "reshape.mlir" |
| "rsqrt.mlir" |
| "select.mlir" |
| "sigmoid.mlir" |
| "sub.mlir" |
| "table.mlir" |
| "tanh.mlir" |
| "transpose.mlir" |
| "while.mlir" |
| TARGET_BACKEND |
| "vulkan-spirv" |
| DRIVER |
| "vulkan" |
| INPUT_TYPE |
| "tosa" |
| ) |
| |
| ### BAZEL_TO_CMAKE_PRESERVES_ALL_CONTENT_BELOW_THIS_LINE ### |
| |
| iree_check_single_backend_test_suite( |
| NAME |
| check_webgpu |
| SRCS |
| "abs.mlir" |
| "add.mlir" |
| "arithmetic_right_shift.mlir" |
| "bitwise_and.mlir" |
| "bitwise_or.mlir" |
| "bitwise_xor.mlir" |
| "ceil.mlir" |
| "clamp.mlir" |
| "clz.mlir" |
| "const.mlir" |
| # "equal.mlir" # TODO(#10906): fix (i8/i16?) |
| "exp.mlir" |
| "floor.mlir" |
| "fully_connected.mlir" |
| "gather.mlir" |
| # "greater.mlir" # TODO(#10906): fix (i8/i16?) |
| # "greater_equal.mlir" # TODO(#10906): fix (i8/i16?) |
| "if.mlir" |
| "log.mlir" |
| "logical_left_shift.mlir" |
| "logical_right_shift.mlir" |
| "matmul.mlir" |
| # "max_pool.mlir" # TODO(#10906): fix (i8/i16?) |
| "maximum.mlir" |
| "minimum.mlir" |
| "mul.mlir" |
| "mul_shift.mlir" |
| "negate.mlir" |
| "pad.mlir" |
| "reciprocal.mlir" |
| "reduce.mlir" |
| "reshape.mlir" |
| "rsqrt.mlir" |
| "select.mlir" |
| "sigmoid.mlir" |
| "sub.mlir" |
| # "table.mlir" # TODO(#10906): fix (i8/i16?) |
| "tanh.mlir" |
| "transpose.mlir" |
| # "while.mlir" # TODO(#12509): WebGPU SPIR-V broken |
| TARGET_BACKEND |
| "webgpu" |
| # Only test compilation for now, the WebGPU driver is not stable/tested yet. |
| # DRIVER |
| # "webgpu" |
| COMPILER_FLAGS |
| "--iree-input-type=tosa" |
| "--iree-codegen-gpu-native-math-precision=true" # TODO(#11321): Infer/flip default |
| ) |
| |
| iree_check_single_backend_test_suite( |
| NAME |
| check_metal-spirv_metal |
| SRCS |
| "abs.mlir" |
| "add.mlir" |
| "arithmetic_right_shift.mlir" |
| "bitwise_and.mlir" |
| "bitwise_or.mlir" |
| "bitwise_xor.mlir" |
| "ceil.mlir" |
| "clamp.mlir" |
| "clz.mlir" |
| "const.mlir" |
| "equal.mlir" |
| "exp.mlir" |
| "floor.mlir" |
| "fully_connected.mlir" |
| "gather.mlir" |
| "greater.mlir" |
| "greater_equal.mlir" |
| "if.mlir" |
| "log.mlir" |
| "logical_left_shift.mlir" |
| "logical_right_shift.mlir" |
| "logical_right_shift_16.mlir" |
| "matmul.mlir" |
| "max_pool.mlir" |
| "maximum.mlir" |
| "minimum.mlir" |
| "mul.mlir" |
| "mul_shift.mlir" |
| "negate.mlir" |
| "pad.mlir" |
| "reciprocal.mlir" |
| "reduce.mlir" |
| "reshape.mlir" |
| "rsqrt.mlir" |
| "select.mlir" |
| "sigmoid.mlir" |
| "sub.mlir" |
| "table.mlir" |
| "tanh.mlir" |
| "transpose.mlir" |
| "while.mlir" |
| TARGET_BACKEND |
| "metal-spirv" |
| DRIVER |
| "metal" |
| COMPILER_FLAGS |
| "--iree-input-type=tosa" |
| ) |
| |
| iree_check_single_backend_test_suite( |
| NAME |
| check_rocm-rocm |
| SRCS |
| "abs.mlir" |
| "add.mlir" |
| "arithmetic_right_shift.mlir" |
| "bitwise_and.mlir" |
| "bitwise_or.mlir" |
| "bitwise_xor.mlir" |
| "ceil.mlir" |
| "clamp.mlir" |
| "clz.mlir" |
| "const.mlir" |
| "equal.mlir" |
| "exp.mlir" |
| "floor.mlir" |
| "fully_connected.mlir" |
| "gather.mlir" |
| "greater.mlir" |
| "greater_equal.mlir" |
| "if.mlir" |
| "log.mlir" |
| "logical_left_shift.mlir" |
| "logical_right_shift.mlir" |
| "logical_right_shift_16.mlir" |
| "matmul.mlir" |
| "max_pool.mlir" |
| "maximum.mlir" |
| "minimum.mlir" |
| "mul.mlir" |
| # "mul_shift.mlir" # missing `LLVMTranslationDialectInterface` registration for dialect for op: tosa.apply_scale |
| "negate.mlir" |
| "pad.mlir" |
| "reciprocal.mlir" |
| "reduce.mlir" |
| "reshape.mlir" |
| "rsqrt.mlir" |
| "select.mlir" |
| "sigmoid.mlir" |
| "sub.mlir" |
| "table.mlir" |
| "tanh.mlir" |
| "transpose.mlir" |
| "while.mlir" |
| TARGET_BACKEND |
| "rocm" |
| # Only test compilation for now, the ROCm driver is experimental. |
| # DRIVER |
| # "rocm" |
| COMPILER_FLAGS |
| "--iree-input-type=tosa" |
| ) |
