[LLVMCPU] Fix scalable vectorization fallback on SME-only (no `+sve`) targets (#24693)

**Stacked** on #24656.  Follow-up to #24661 / #24660.

This PR aims to removes the TODO introduced in #24656.

#24661 fixed the ArmSME lowering pipeline to not require classic `+sve`
when SME tiling is used. This PR fixes the same underlying problem for
the *fallback* path, which is what's used when the matmul falls back to
it (e.g., `--iree-llvmcpu-disable-arm-sme-tiling`, or op types SME
doesn't support): compiling a scalable-vectorized matmul on a
`+sme`-only target with SME tiling disabled crashed LLVM instruction
selection with `Cannot select: vscale`.

The fix is scoped to a single function:
`getMatmulVectorSizesUsingFillRegisterFileHeuristic` only checked
`hasAnySVEFeature`, so on a `+sme`-only target it always fell back to
non-scalable NEON tiles. It now also picks scalable tiles when `+sme` is
present *and* the user has explicitly passed
`--iree-llvmcpu-force-arm-streaming`.

Net effect: 
1. Non-matmul ops: always Peeling.
4. `linalg.matmul`, `+sme-only`, `disable-arm-sme-tiling=true`, and
`force-arm-streaming=true`: still reaches SSVE (that's the actual fix),
but now goes through `Peeling + masked tail` instead of masking-only (as
in #24661).

Unrelated to #24689

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Signed-off-by: Federico Bruzzone <federico.bruzzone.i@gmail.com>