)]}'
{
  "commit": "16396e421e8a58e0a95bb406f17683aefe699cee",
  "tree": "8076b7d7d7b0d99bad26f6baacb897d36903266b",
  "parents": [
    "35b2070788e70693b3c04ecfd96b282c03a4bf26"
  ],
  "author": {
    "name": "Federico Bruzzone",
    "email": "federico.bruzzone.i@gmail.com",
    "time": "Fri Jul 24 08:44:38 2026 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri Jul 24 08:44:38 2026 +0200"
  },
  "message": "[LLVMCPU] Fix scalable vectorization fallback on SME-only (no `+sve`) targets (#24693)\n\n**Stacked** on #24656.  Follow-up to #24661 / #24660.\n\nThis PR aims to removes the TODO introduced in #24656.\n\n#24661 fixed the ArmSME lowering pipeline to not require classic `+sve`\nwhen SME tiling is used. This PR fixes the same underlying problem for\nthe *fallback* path, which is what\u0027s used when the matmul falls back to\nit (e.g., `--iree-llvmcpu-disable-arm-sme-tiling`, or op types SME\ndoesn\u0027t support): compiling a scalable-vectorized matmul on a\n`+sme`-only target with SME tiling disabled crashed LLVM instruction\nselection with `Cannot select: vscale`.\n\nThe fix is scoped to a single function:\n`getMatmulVectorSizesUsingFillRegisterFileHeuristic` only checked\n`hasAnySVEFeature`, so on a `+sme`-only target it always fell back to\nnon-scalable NEON tiles. It now also picks scalable tiles when `+sme` is\npresent *and* the user has explicitly passed\n`--iree-llvmcpu-force-arm-streaming`.\n\nNet effect: \n1. Non-matmul ops: always Peeling.\n4. `linalg.matmul`, `+sme-only`, `disable-arm-sme-tiling\u003dtrue`, and\n`force-arm-streaming\u003dtrue`: still reaches SSVE (that\u0027s the actual fix),\nbut now goes through `Peeling + masked tail` instead of masking-only (as\nin #24661).\n\nUnrelated to #24689\n\n---------\n\nSigned-off-by: Federico Bruzzone \u003cfederico.bruzzone.i@gmail.com\u003e",
  "tree_diff": [
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