| # Common interfaces | |
| ## Overview | |
| In this directory, we provide commonly used interfaces to construct testbenches for DV. | |
| They are described in detail below. | |
| ### clk_rst_if | |
| This interface provides the ability to drive / sample clock and reset signal. | |
| ### pins_if | |
| This interface provides the ability to drive / sample any signal in the DUT. |