doc/ug/system_list.md

# List of Top-Level Designs

This page lists all top-level designs and their targets that are contained within this repository.
Click on the design name to get more information about the design.

<table>
  <thead>
    <tr>
      <th>Design</th>
      <th>Internal Name</th>
      <th>Simulation Targets</th>
      <th>FPGA Targets</th>
      <th>ASIC Targets</th>
      <th>Description</th>
    </tr>
  </thead>
  <tr>
    <td><a href="/hw/top_earlgrey/doc/top_earlgrey.html">Earl Grey</a></td>
    <td><pre>top_earlgrey</pre></td>
    <td>
      <ul>
        <li>Verilator</li>
        <li>?</li>
      </ul>
    </td>
    <td>
      <ul>
        <li>Nexys Video*</li>
      </ul>
    </td>
    <td>
      <i>None yet.</i>
    </td>
    <td>
      0.1 release
    </td>
  </tr>
</table>

A `*` behind an FPGA board indicates it can be used with a free EDA tool license.