| # OpenTitan General Documentation |
| * [Project]({{< relref "doc/project" >}}) |
| * How the OpenTitan project is organized |
| * Hardware development stages |
| * Hardware signoff checklist |
| * [User Guides]({{< relref "doc/ug" >}}) |
| * How to get started with the repo |
| * How to emulate on an FPGA |
| * How hardware design is done in OpenTitan |
| * How verification is done in OpenTitan |
| * [Reference Manuals]({{< relref "doc/rm" >}}) |
| * Defining comportable IP peripherals |
| * Coding style guides for Verilog, Python, Hjson, C/C++ and Markdown |
| * [Security Docs]({{< relref "doc/security" >}}) |
| * Logical security documents |
