1. 5329a41 [syn] Rename INTERACTIVE to RUN_INTERACTIVE by Eli Kim · 2 years, 1 month ago
  2. 0bda971 [dvsim] Move empty pattern list to common by Eli Kim · 2 years, 2 months ago
  3. 8e586da [fpv] Support build_pass_pattern in OneShotCfg by Cindy Chen · 2 years, 2 months ago
  4. 84f6910 [dvsim] Remove support for email report by Michael Schaffner · 2 years, 5 months ago
  5. 543793f [lint] Fix shellcheck errors in hw by Miles Dai · 2 years, 7 months ago
  6. 74ac920 [dvsim] Fix pass/fail status for synthesis regression by Michael Schaffner · 2 years, 11 months ago
  7. b9d1c04 [syn] Add an elaboration-only synthesis target by Michael Schaffner · 2 years, 11 months ago
  8. 685e80f [syn] Extend synthesis parsing script for partial synthesis flows by Michael Schaffner · 2 years, 11 months ago
  9. 15cfb8f [syn] Enable full compilation in GTECH synthesis flow by Michael Schaffner · 3 years, 1 month ago
  10. e97ff3f [syn/cdc] Minor flow fixes in CDC and syn scripts by Michael Schaffner · 3 years, 2 months ago
  11. 5133bb5 [aes] Add gtech synthesis setup by Michael Schaffner · 3 years, 2 months ago
  12. 1cb4185 [syn] Minor scripting alignment with CDC flow by Michael Schaffner · 3 years, 3 months ago
  13. 16392ef [dv] Add sv_flist_gen_flags HJson var for FuseSoc by Srikrishna Iyer · 3 years, 5 months ago
  14. f9564de [top] update constraints for passthrough by Timothy Chen · 3 years, 9 months ago
  15. eb47586 [syn] Add additional instructions by Timothy Chen · 3 years, 9 months ago
  16. 4dfb18b [syn] Correct power report regexp by Michael Schaffner · 3 years, 9 months ago
  17. 9e29aed [syn] Correct report parser script by Michael Schaffner · 3 years, 9 months ago
  18. 9dc0070 [syn] Add some more example commands to the readme by Michael Schaffner · 3 years, 9 months ago
  19. 4c583de [top] Connect RomCtrlSkipCheck by Timothy Chen · 3 years, 9 months ago
  20. d5c17cc [sdc] Correct the clock group constraint by Michael Schaffner · 3 years, 9 months ago
  21. e489c4a [tools] simple instructions for interactive synth by Timothy Chen · 3 years, 9 months ago
  22. 93fe50c [top/chip] Rename chip-level tops by Michael Schaffner · 3 years, 10 months ago
  23. 5b6f9d6 [dvsim] Added common build fail patterns by Srikrishna Iyer · 3 years, 10 months ago
  24. 00a064a [dvsim] Use bash when running make underneath by Srikrishna Iyer · 3 years, 11 months ago
  25. b403834 [dvsim/syn] Update parsing script and area reporting by Michael Schaffner · 4 years ago
  26. 736bbce [syn] Add chip level SDC and synthesis config by Michael Schaffner · 4 years ago
  27. b5b8eba [padring/top] Carry over pinout from bronze and align sim and FPGA tops by Michael Schaffner · 4 years ago
  28. c4f3c7f [syn] Minor updates by Srikrishna Iyer · 4 years ago
  29. cce6094 [cleanup] Mass replace tabs with spaces by Srikrishna Iyer · 4 years, 1 month ago
  30. 498deab [vendor/ibex] Remove duplicate check tool requirements files by Michael Schaffner · 4 years, 1 month ago
  31. 981c36b [dvsim] Logic to copy repo to scratch area by Srikrishna Iyer · 4 years, 1 month ago
  32. a23dfec [util] Rejig how we load hjson configurations for dvsim.py by Rupert Swarbrick · 4 years, 5 months ago
  33. ce93b99 [asic] Enable Masking for KMAC by Eunchan Kim · 4 years, 3 months ago
  34. b3e4dcd [syn/otbn/aes] Add block-level OTBN synthesis and fix AES synthesis by Michael Schaffner · 4 years, 3 months ago
  35. a8fb05e [dvsim] Fix HJson bugs by Srikrishna Iyer · 4 years, 3 months ago
  36. a0f1ab9 [dv/common] Move testplan from tools directory to data by Weicai Yang · 4 years, 4 months ago
  37. 6bf8540 [syn] Minor fix to test synthesis script by Michael Schaffner · 4 years, 4 months ago
  38. eb333ec [syn] Carry over synthesis flow updates from bronze by Michael Schaffner · 4 years, 6 months ago
  39. ea90aac [dvsim] Change cores-root to avoid conflicts with autogen'd core files by Michael Schaffner · 4 years, 6 months ago
  40. be47dd7 [flows] Various updates to tools and documents to suppose top/ip select by Timothy Chen · 4 years, 6 months ago
  41. 0697e5f [syn] Minor updates to align flow with foundry setup scripts by Michael Schaffner · 4 years, 6 months ago
  42. 75105e0 [syn] Fix an error in the DC synthesis setup by Michael Schaffner · 4 years, 6 months ago
  43. 5e6812b [dvsim/syn] Update flow to copy over new lib-setup.tcl file by Michael Schaffner · 4 years, 6 months ago
  44. 9b2c3d2 [syn] Add CONSTRAINT environment in synthesis script by Eunchan Kim · 4 years, 6 months ago
  45. a7bba81 [syn] Add gitignore file to dc folder by Michael Schaffner · 4 years, 6 months ago
  46. fe79c4b switch to host, primary, or over-arching as appropriate by Scott Johnson · 4 years, 7 months ago
  47. 8194488 [syn] Fix behavior of parsing script in a few error cases by Michael Schaffner · 4 years, 6 months ago
  48. 37324a7 [tool/script] delete clean section in make files by Cindy Chen · 4 years, 7 months ago
  49. 373f6d1 [dvsim/syn/lint] Add options to selectively sanitize reports by Michael Schaffner · 4 years, 7 months ago
  50. 25f451a [syn] Minor refactorings in parse-syn-report.py by Rupert Swarbrick · 4 years, 7 months ago
  51. 9827e00 [syn] Update AT plot script by Michael Schaffner · 4 years, 7 months ago
  52. 5f4f602 [syn] Minor updates to synthesis script by Michael Schaffner · 4 years, 7 months ago
  53. 8fc927c [syn] Print detailed messages to .md if publication is disabled by Michael Schaffner · 4 years, 7 months ago
  54. 5c581d8 [syn] Minor updates to synthesis scripts by Michael Schaffner · 4 years, 8 months ago
  55. e9c94b9 [syn] Revise constraints by Eunchan Kim · 4 years, 8 months ago
  56. eeef3df [lint] Add Verible configuration file and update parsing script by Michael Schaffner · 4 years, 9 months ago
  57. 4204a8d [dvsim] Initial verible lint integration by Michael Schaffner · 4 years, 10 months ago
  58. f342ba2 [syn] Add testsynthesis and sweep scripts for experiments by Michael Schaffner · 4 years, 10 months ago
  59. 6b714a0 [syn/lint] Small scripting fixes in synthesis/lint flows by Michael Schaffner · 4 years, 10 months ago
  60. d95b2a1 [syn] Split SDC file into per IP file and add AES example by Michael Schaffner · 4 years, 10 months ago
  61. 3d16099 [dvsim] Synthesis target integration by Michael Schaffner · 4 years, 10 months ago
  62. 17df5a2 [syn] This adds a simple testsynthesis flow for DC by Michael Schaffner · 4 years, 11 months ago