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opensecura / 3p / lowrisc / opentitan / 5a1c665a50f3c920862f9eb4aa4d2c8b8038ab52 / hw / ip / prim / rtl / prim_clock_div.sv
  1. 6745e6f [ast] Lint fixes and waiver updates by Michael Schaffner · 2 years, 11 months ago
  2. 87a8f51 [prim_clock_div] Fix minor Verilator lint warning by Michael Schaffner · 3 years, 3 months ago
  3. a1af4ec [clkmgr] Fix dft issues by Timothy Chen · 4 years ago
  4. 33c9078 [clkmgr / top] Add clock divider step down to support lc_ctrl transition by Timothy Chen · 4 years, 2 months ago
  5. 11c848e [prim] update clock_mux prim to avoid using BUFG by Timothy Chen · 4 years, 4 months ago
  6. 1366af7 [clkmgr] Add divider bypass during test mode by Timothy Chen · 4 years, 4 months ago
  7. f851850 [prim] Add clock buffer primitive for Xilinx FPGAs by Pirmin Vogel · 4 years, 5 months ago
  8. ee8ffc2 [prim] Add primitive clock divider by Timothy Chen · 4 years, 7 months ago