[edn/dv] Add UNR file
Signed-off-by: Steve Nelson <steve.nelson@wdc.com>
diff --git a/hw/ip/edn/dv/cov/edn_UNR.vRefine b/hw/ip/edn/dv/cov/edn_UNR.vRefine
new file mode 100644
index 0000000..583ce3e
--- /dev/null
+++ b/hw/ip/edn/dv/cov/edn_UNR.vRefine
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<refinement-file-root>
+ <information comment-version="1" creation-time="Tue 19 Apr 2022 11:20:45 PDT" creator="steve.nelson" csCheck="false" save-ref-method="seq" tool-version="Cadence vManager21.03" rules-signature-c="eab6e59351bdab55e59fab1bcd11cfc0">
+ <ucm-files>
+ <ucm-file domain="icc" modelCheckSum="423110909" path="/wdc/proj/cto/top/work/steve.nelson/opentitan/scratch/edn_dv_unr/edn-sim-xcelium/cov_merge/__jg_coverage_unr_merge_tmp_unr/icc_193828fd_5344384b.ucm"></ucm-file>
+ </ucm-files>
+ <ccf-files>
+ <ccf-file content="// Copyright lowRISC contributors.;// Licensed under the Apache License, Version 2.0, see LICENSE for details.;// SPDX-License-Identifier: Apache-2.0;;// Include our common coverage CCF.;include_ccf ${dv_root}/tools/xcelium/common.ccf; /wdc/proj/cto/top/work/steve.nelson/opentitan/hw/dv/tools/xcelium/common.ccf; // Copyright lowRISC contributors.; // Licensed under the Apache License, Version 2.0, see LICENSE for details.; // SPDX-License-Identifier: Apache-2.0; ; // Common coverage commands that apply to all DUTs.; //; // This coverge config file is provided by Xcelium and is located at:; // ${XCELIUM_HOME}/tools/icc/include/all_coverage.ccf; // Xcelium recommends including it, since it bundles together the common set of commands that enable; // coverage collection on various design elements, that are otherwise turned off by default. We; // maintain it locally with minor amends.; ; // Enables expression coverage of various Verilog operators.; set_expr_coverable_operators -all -event_or; ; // Enables expression coverage of operators in various conditions and assignments.; set_expr_coverable_statements -all; ; // Enables scoring of Verilog modules compiled with -v/-y or -libcell option but continues to; // disable the scoring of Verilog modules defined with the 'celldefine compiler directive.; set_libcell_scoring; ; // Enables scoring of block and expression coverage for functions and tasks defined directly inside; // SystemVerilog packages.; set_subprogram_scoring -svpackage; ; // Enables scoring of SystemVerilog continuous assignments, which is by disabled by default.; set_assign_scoring; ; // Scores branches together with block coverage.; set_branch_scoring; ; // Scores statements within a block.; set_statement_scoring; ; // Enables expression coverage for expression containing structs (packed and unpacked).; set_expr_scoring -struct; ; // Enables Toggle scoring and reporting of SystemVerilog enumerations and multidimensional static; // arrays , vectors, packed union, modport and generate blocks.; set_toggle_scoring -sv_enum enable_mda -sv_struct_with_enum -sv_modport -sv_mda 16 -sv_mda_of_struct -sv_generate -sv_packed_union; ; // Enables scoring of reset states and transitions for identified FSMs.; set_fsm_reset_scoring; ; // Enables scoring of immediate assertions inside a class in a package and assertions inside AMS; // modules.; select_functional -ams_control -imm_asrt_class_package; ; // Improve the scoping and naming of covergroup instances.; set_covergroup -new_instance_reporting; ; // Enable toggle coverage only on ports.; set_toggle_portsonly; ; // Enable scoring of FSM arcs (state transitions).; set_fsm_arc_scoring; ; // Include X->1|0 for toggle coverage collection. #10332; set_toggle_includex;;// Black-box pre-verified IPs from coverage collection.;deselect_coverage -betfs -module pins_if;deselect_coverage -betfs -module clk_rst_if;deselect_coverage -betfs -module prim_alert_sender...;deselect_coverage -betfs -module prim_alert_receiver...;deselect_coverage -betfs -module prim_esc_sender...;deselect_coverage -betfs -module prim_esc_receiver...;deselect_coverage -betfs -module prim_prince...;deselect_coverage -betfs -module prim_lfsr...;// csr_assert_fpv is an auto-generated csr read assertion module. So only assertion coverage is;// meaningful to collect.;deselect_coverage -betf -module *csr_assert_fpv...;;// Only collect toggle coverage on the DUT and the black-boxed IP (above) ports.;deselect_coverage -toggle -module ${DUT_TOP}...;select_coverage -toggle -module ${DUT_TOP};select_coverage -toggle -module prim_alert_sender;select_coverage -toggle -module prim_alert_receiver;select_coverage -toggle -module prim_esc_sender;select_coverage -toggle -module prim_esc_receiver;select_coverage -toggle -module prim_prince;select_coverage -toggle -module prim_lfsr;;// These three assertions in prim_lc_sync and prim_mubi* check when `lc_ctrl_pkg::lc_tx_t` or;// `mubi*_t` input are neither `On` or `Off`, it is interrupted to the correct `On` or `Off`;// after one clock cycle. This behavior is implemented outside of IP level design thus these;// assertions are not covered in IP level testbenchs.;// TODO: check these assertions in top-level or FPV.;deselect_coverage -assertion *.PrimLcSyncCheckTransients_A;deselect_coverage -assertion *.PrimLcSyncCheckTransients0_A;deselect_coverage -assertion *.PrimLcSyncCheckTransients1_A;;deselect_coverage -assertion *.PrimMubi4SyncCheckTransients_A;deselect_coverage -assertion *.PrimMubi4SyncCheckTransients0_A;deselect_coverage -assertion *.PrimMubi4SyncCheckTransients1_A;;deselect_coverage -assertion PrimMubi8SyncCheckTransients_A;deselect_coverage -assertion PrimMubi8SyncCheckTransients0_A;deselect_coverage -assertion PrimMubi8SyncCheckTransients1_A;;deselect_coverage -assertion PrimMubi12SyncCheckTransients_A;deselect_coverage -assertion PrimMubi12SyncCheckTransients0_A;deselect_coverage -assertion PrimMubi12SyncCheckTransients1_A;;deselect_coverage -assertion PrimMubi16SyncCheckTransients_A;deselect_coverage -assertion PrimMubi16SyncCheckTransients0_A;deselect_coverage -assertion PrimMubi16SyncCheckTransients1_A;" path="/wdc/proj/cto/top/work/steve.nelson/opentitan/hw/dv/tools/xcelium/cover.ccf"></ccf-file>
+ </ccf-files>
+ </information>
+ <rules></rules>
+ <cache-map></cache-map>
+</refinement-file-root>
diff --git a/hw/ip/edn/dv/edn_sim_cfg.hjson b/hw/ip/edn/dv/edn_sim_cfg.hjson
index cf71222..2aba49e 100644
--- a/hw/ip/edn/dv/edn_sim_cfg.hjson
+++ b/hw/ip/edn/dv/edn_sim_cfg.hjson
@@ -37,6 +37,9 @@
// Add additional tops for simulation.
sim_tops: ["edn_bind", "edn_cov_bind"]
+ // TODO: Redo for V2S
+ xcelium_cov_refine_files: ["{proj_root}/hw/ip/edn/dv/cov/edn_UNR.vRefine"]
+
// Default iterations for all tests - each test entry can override this.
reseed: 50
