[hw] Add additional I/O ports to Ibex
This commit adds the new `core_sleep_o` output and the `instr_err_i`
input to Ibex.
diff --git a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
index c9660c9..8982350 100644
--- a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
+++ b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
@@ -44,7 +44,8 @@
input logic debug_req_i,
// CPU Control Signals
- input logic fetch_enable_i
+ input logic fetch_enable_i,
+ output logic core_sleep_o
);
import top_pkg::*;
@@ -55,6 +56,7 @@
logic instr_rvalid_i;
logic [31:0] instr_addr_o;
logic [31:0] instr_rdata_i;
+ logic instr_err_i;
logic data_req_o;
logic data_gnt_i;
@@ -111,6 +113,7 @@
.instr_rvalid_i,
.instr_addr_o,
.instr_rdata_i,
+ .instr_err_i,
.data_req_o,
.data_gnt_i,
@@ -154,8 +157,8 @@
.rvfi_mem_wdata,
`endif
- .fetch_enable_i
-
+ .fetch_enable_i,
+ .core_sleep_o
);
//
@@ -193,7 +196,7 @@
assign instr_gnt_i = tl_i_i.a_ready & tl_i_o.a_valid;
assign instr_rvalid_i = tl_i_i.d_valid;
assign instr_rdata_i = tl_i_i.d_data;
- // TODO: add error response
+ assign instr_err_i = tl_i_i.d_error;
// For core data interface, calculate a_size from data_be_o
logic [2:0] data_be_countones;
diff --git a/hw/top_earlgrey/doc/top_earlgrey.tpl.sv b/hw/top_earlgrey/doc/top_earlgrey.tpl.sv
index dc95882..8a7bc52 100644
--- a/hw/top_earlgrey/doc/top_earlgrey.tpl.sv
+++ b/hw/top_earlgrey/doc/top_earlgrey.tpl.sv
@@ -132,7 +132,8 @@
// debug interface
.debug_req_i (debug_req),
// CPU control signals
- .fetch_enable_i (1'b1)
+ .fetch_enable_i (1'b1),
+ .core_sleep_o ()
);
// Debug Module (RISC-V Debug Spec 0.13)
diff --git a/hw/top_earlgrey/rtl/top_earlgrey.sv b/hw/top_earlgrey/rtl/top_earlgrey.sv
index a3dbde1..61d9a46 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey.sv
@@ -142,7 +142,8 @@
// debug interface
.debug_req_i (debug_req),
// CPU control signals
- .fetch_enable_i (1'b1)
+ .fetch_enable_i (1'b1),
+ .core_sleep_o ()
);
// Debug Module (RISC-V Debug Spec 0.13)
