[top_earlgrey/rtl] adding csrng and edn blocks
Most connections for entropy complex blocks add been made.
Added csrng and edn to the lint list, plus the verilator files.
Amended a typo in csrng.hjson.
Regenerated the top_earlgrey verilog file.
Fixed the default statements to entropy_src and csrng packages.
Fixed the edn hjson file and rerun make.
Added and adjusted multibit statement in csrng.core.
Fixed entropy_src ports to match in the hjson file.
Removed unneeded xbar connections in top_earlgrey hjson file.
Restricted csrng_cmd to only one i/f since ENV does not support more.
Changed csrng and edn hjson and rtl core files to get chip reg test to pass.
Removed CI whitespace on hjson files.
Added cntl and status tags to edn.hjson to prevent hw actions during reg testing.
Added alert connection to entropy_src because dv alert class needs a fix.
Removed executable permissions on various files.
Removed TODOs because support for multiple block instance support for dv was added.
Updated the memory map for the main xbar for edn0, edn1, and some reserved space.
Signed-off-by: Mark Branstad <mark.branstad@wdc.com>
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
old mode 100644
new mode 100755
index bb81dbc..28f46ac
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -271,7 +271,7 @@
clock_srcs: {clk_i: "main"},
clock_group: "secure",
reset_connections: {rst_ni: "sys"},
- base_addr: "0x40130000",
+ base_addr: "0x411b0000",
generated: "true" // Indicate this module is generated in the topgen
localparam: {
EscCntDw: 32,
@@ -316,7 +316,7 @@
clock_srcs: {clk_i: "main"},
clock_group: "secure",
reset_connections: {rst_ni: "sys"},
- base_addr: "0x40140000",
+ base_addr: "0x411c0000",
}
{ name: "usbdev",
type: "usbdev",
@@ -351,6 +351,34 @@
reset_connections: {rst_ni: "lc_io_div4"},
base_addr: "0x401b0000",
},
+ { name: "csrng",
+ type: "csrng",
+ clock_srcs: {clk_i: "main"},
+ clock_group: "secure",
+ reset_connections: {rst_ni: "sys"},
+ base_addr: "0x41150000",
+ },
+ { name: "entropy_src",
+ type: "entropy_src",
+ clock_srcs: {clk_i: "main"},
+ clock_group: "secure",
+ reset_connections: {rst_ni: "sys"},
+ base_addr: "0x41160000",
+ },
+ { name: "edn0",
+ type: "edn",
+ clock_srcs: {clk_i: "main"},
+ clock_group: "secure",
+ reset_connections: {rst_ni: "sys"},
+ base_addr: "0x41170000",
+ },
+ { name: "edn1",
+ type: "edn",
+ clock_srcs: {clk_i: "main"},
+ clock_group: "secure",
+ reset_connections: {rst_ni: "sys"},
+ base_addr: "0x41180000",
+ },
{ name: "otbn",
type: "otbn",
clock_srcs: {clk_i: "main"},
@@ -472,6 +500,7 @@
// e.g flash_ctrl0.flash: [flash_phy0.flash_ctrl]
inter_module: {
'connect': {
+ 'csrng.csrng_cmd' : ['edn0.csrng_cmd', 'edn1.csrng_cmd'],
'flash_ctrl.flash' : ['eflash.flash_ctrl'],
'pwrmgr.pwr_flash' : ['flash_ctrl.pwrmgr'],
'pwrmgr.pwr_rst' : ['rstmgr.pwr'],
@@ -479,6 +508,7 @@
'pwrmgr.pwr_otp' : ['otp_ctrl.pwr_otp'],
'flash_ctrl.keymgr': ['keymgr.flash'],
'alert_handler.crashdump': ['rstmgr.alert_dump'],
+ 'csrng.entropy_src_hw_if' : ['entropy_src.entropy_src_hw_if'],
// KeyMgr Sideload & KDF function
'keymgr.kmac_key' : ['kmac.keymgr_key']
@@ -497,7 +527,6 @@
// Xbars
'main.tl_corei', 'main.tl_cored', 'main.tl_dm_sba', 'main.tl_debug_mem'
-
],
// ext is to create port in the top.
@@ -562,7 +591,7 @@
// ===== ALERT HANDLER ======================================================
// list all modules that expose alerts
// first item goes to LSB of the alert source
- alert_module: [ "aes", "otbn", "sensor_ctrl", "keymgr", "otp_ctrl" ]
+ alert_module: [ "aes", "otbn", "sensor_ctrl", "keymgr", "otp_ctrl", "entropy_src" ]
// generated list of alerts:
alert: [
