| commit | eaee39701d7570e73107bcfa361f6be18cb6ba49 | [log] [tgz] |
|---|---|---|
| author | Eunchan Kim <eunchan@opentitan.org> | Tue Mar 09 09:55:01 2021 -0800 |
| committer | Eunchan Kim <eunchan@opentitan.org> | Wed Mar 10 10:23:01 2021 -0800 |
| tree | 09e3367a5866ec8be3808e657bf258869ab3f61c | |
| parent | da341bfe385c6aca906ead47ba7110bd9a8273f6 [diff] |
[spi_device] Adding clock mux for DPSRAM The DPSRAM requires to be asynchronous to support FlashMode and PassThrough mode. This commit changes the DPSRAM type to prim_ram_2p_async_adv and add clock mux for sram B port. As SPI_CLK does not toggle when it is in idle, glitch-free clock mux can't be put in. SW is required additional cautions when it changes the sram clock. Suggested programming sequence is added in the newly introduced register field `sram_clk_en` Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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