| commit | ff1a7be3ff4827cb8419b0d07c00000978d1198f | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Thu Aug 20 15:10:32 2020 +0100 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Wed Aug 26 16:05:33 2020 +0100 |
| tree | dd035c3f1f69d6e4a6020349d9e3929375cfce2c | |
| parent | f9ca661dc16f136b4eedd38767d7cbc4a43e7799 [diff] |
[otbn] Move shift information from encoding to operand
Some operands get encoded with a "shift". For example, the following
line of assembly
bn.mulqacc w30.1, w25.0, 64
has an acc_shift_imm operand of 64. This is actually encoded as 1: the
operand is shifted down by 6 bits before encoding.
This sort of thing is supported by the RISC-V instruction set too, and
their ISA specifies these shifts as part of the list of encoding
schemes. Until now, we did the same thing (copying them!)
In general, there are two jobs that need doing when converting from
the string representation in the assembly file to a number that can be
put in the encoding.
- 2's complement encoding for signed immediates
- Shifting down appropriately
Before this commit, the signedness information for an operand was
stored on the OperandType object and the shift was stored on the
EncSchemeField object. This is a bit silly: surely it would make more
sense to put them together! In fact, it's worse: we could specify a
register operand with a shift. With a shift of 1, you'd be able to
write x0, x2, x4 and x62(!) but not x1 or x3.
So this commit moves the shift to the OperandType object. Now our
OperandType.read_index function does both of the jobs above, and it is
the inverse operation of OperandType.render_val. Much nicer!
As a bonus, this now means it's easy for an operand's type to be more
precise about the range of values it supports. So acc_shift_imm used
to say "Valid range: 0..3". Now it says "Valid range: 0..196 in steps
of 64".
While writing this patch, I noticed that OperandType.read_index also
didn't support signed operands correctly, which this also fixes.
As a sanity check, I compared the assembled (and disassembled) code
snippet examples before and after this patch. The assembled snippets
are identical. The differences in the objdump disassembly are exactly
from fixing the rendering of shifted operands as in the example above.
Similarly, the only differences in generated documentation are from
the fixed ranges described above and a fixed text string for mulqacc's
acc_shift_imm operand.
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
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