switch to host, primary, or over-arching as appropriate
Signed-off-by: Scott Johnson <scottdj@google.com>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 5cc4dae..c509d11 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -442,7 +442,7 @@
type: input
}
{
- name: mosi
+ name: sdi
width: 1
type: input
}
@@ -450,7 +450,7 @@
available_output_list:
[
{
- name: miso
+ name: sdo
width: 1
type: output
}
@@ -3360,7 +3360,7 @@
]
}
{
- name: spi_device_mosi
+ name: spi_device_sdi
width: 1
type: input
module_name: spi_device
@@ -3373,7 +3373,7 @@
]
}
{
- name: spi_device_miso
+ name: spi_device_sdo
width: 1
type: output
module_name: spi_device
@@ -4084,4 +4084,4 @@
}
]
}
-}
\ No newline at end of file
+}
diff --git a/hw/top_earlgrey/data/pins_artys7.xdc b/hw/top_earlgrey/data/pins_artys7.xdc
index cc6e9c3..3f2663f 100644
--- a/hw/top_earlgrey/data/pins_artys7.xdc
+++ b/hw/top_earlgrey/data/pins_artys7.xdc
@@ -101,8 +101,8 @@
## ChipKit SPI Header
## NOTE: The ChipKit SPI header ports can also be used as digital I/O and share FPGA pins with ck_io10-13. Do not use both at the same time.
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { ck_io10_ss }]; #IO_L22P_T3_A17_15 Sch=ck_io10_ss
-#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ck_io11_mosi }]; #IO_L22N_T3_A16_15 Sch=ck_io11_mosi
-#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ck_io12_miso }]; #IO_L23P_T3_FOE_B_15 Sch=ck_io12_miso
+#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ck_io11_sdi }]; #IO_L22N_T3_A16_15 Sch=ck_io11_sdi
+#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ck_io12_sdo }]; #IO_L23P_T3_FOE_B_15 Sch=ck_io12_sdo
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { ck_io13_sck }]; #IO_L14P_T2_SRCC_15 Sch=ck_io13_sck
## ChipKit Inner Digital Header
@@ -182,7 +182,7 @@
## Quad SPI Flash
## Note: the SCK clock signal can be driven using the STARTUPE2 primitive
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
-#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_SDI_14 Sch=qspi_dq[0]
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
diff --git a/hw/top_earlgrey/data/pins_nexysvideo.xdc b/hw/top_earlgrey/data/pins_nexysvideo.xdc
index 5149178..b1848dc 100644
--- a/hw/top_earlgrey/data/pins_nexysvideo.xdc
+++ b/hw/top_earlgrey/data/pins_nexysvideo.xdc
@@ -141,8 +141,8 @@
## Pmod header JC
#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { IO_SDCK }]; #IO_L18P_T2_34 Sch=jc_p[1]
#set_property -dict { PACKAGE_PIN AA6 IOSTANDARD LVCMOS33 } [get_ports { IO_SDCSB }]; #IO_L18N_T2_34 Sch=jc_n[1]
-#set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS33 } [get_ports { IO_SDMOSI }]; #IO_L22P_T3_34 Sch=jc_p[2]
-#set_property -dict { PACKAGE_PIN AB8 IOSTANDARD LVCMOS33 } [get_ports { IO_SDMISO }]; #IO_L22N_T3_34 Sch=jc_n[2]
+#set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS33 } [get_ports { IO_SDSDI }]; #IO_L22P_T3_34 Sch=jc_p[2]
+#set_property -dict { PACKAGE_PIN AB8 IOSTANDARD LVCMOS33 } [get_ports { IO_SDSDO }]; #IO_L22N_T3_34 Sch=jc_n[2]
#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { IO_OBS }]; #IO_L18P_T2_34 Sch=jc_p[1]
#set_property -dict { PACKAGE_PIN AA6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L18N_T2_34 Sch=jc_n[1]
#set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22P_T3_34 Sch=jc_p[2]
@@ -196,8 +196,8 @@
## DPTI/DSPI
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { prog_clko }]; #IO_L13P_T2_MRCC_14 Sch=prog_clko
set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS0 }]; #IO_L11P_T1_SRCC_14 Sch=prog_d0/sck
-set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS1 }]; #IO_L19P_T3_A10_D26_14 Sch=prog_d1/mosi
-set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS2 }]; #IO_L22P_T3_A05_D21_14 Sch=prog_d2/miso
+set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS1 }]; #IO_L19P_T3_A10_D26_14 Sch=prog_d1/sdi
+set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS2 }]; #IO_L22P_T3_A05_D21_14 Sch=prog_d2/sdo
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS3 }]; #IO_L18P_T2_A12_D28_14 Sch=prog_d3/ss
set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS4 }]; #IO_L24N_T3_A00_D16_14 Sch=prog_d[4]
set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 PULLTYPE PULLUP } [get_ports { IO_DPS5 }]; #IO_L24P_T3_A01_D17_14 Sch=prog_d[5]
@@ -219,7 +219,7 @@
## QSPI
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
-#set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_SDI_14 Sch=qspi_dq[0]
#set_property -dict { PACKAGE_PIN R22 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
#set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
#set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
diff --git a/hw/top_earlgrey/doc/_index.md b/hw/top_earlgrey/doc/_index.md
index a89f8ae..c76c8b9 100644
--- a/hw/top_earlgrey/doc/_index.md
+++ b/hw/top_earlgrey/doc/_index.md
@@ -104,9 +104,9 @@
| `jtag_trst_ni` | input | JTAG Test Reset |
| `dio_spi_device_sck_i` | input | SPI device clock |
| `dio_spi_device_csb_i` | input | SPI device chip select |
-| `dio_spi_device_mosi_i` | input | SPI device input data |
-| `dio_spi_device_miso_o` | output | SPI device output data |
-| `dio_spi_device_miso_en_o` | output | SPI device output enable |
+| `dio_spi_device_sdi_i` | input | SPI device input data |
+| `dio_spi_device_sdo_o` | output | SPI device output data |
+| `dio_spi_device_sdo_en_o` | output | SPI device output enable |
| `dio_uart_rx_i` | input | UART input receive data |
| `dio_uart_tx_o` | output | UART output transmit data |
| `dio_uart_tx_en_o` | output | UART output transmit output enable |
@@ -121,8 +121,8 @@
| `IO_CLK` | input | Chip level functional clock |
| `IO_RST_N` | input | Chip level reset, active low |
| `IO_DPS0` | input | Muxed functionality: JTAG `TCK` and `spi_device_sck_i` |
-| `IO_DPS1` | input | Muxed functionality: JTAG `TDI` and `spi_device_mosi_i` |
-| `IO_DPS2` | output | Muxed functionality: JTAG `TDO` and `spi_device_miso_o` |
+| `IO_DPS1` | input | Muxed functionality: JTAG `TDI` and `spi_device_sdi_i` |
+| `IO_DPS2` | output | Muxed functionality: JTAG `TDO` and `spi_device_sdo_o` |
| `IO_DPS3` | input | Muxed functionality: JTAG `TMS` and `spi_device_csb_i` |
| `IO_DPS4` | input | JTAG `TRST_N` |
| `IO_DPS5` | input | JTAG `SRST_N` |
diff --git a/hw/top_earlgrey/dv/tb/tb.sv b/hw/top_earlgrey/dv/tb/tb.sv
index dadbd43..cb70f9a 100644
--- a/hw/top_earlgrey/dv/tb/tb.sv
+++ b/hw/top_earlgrey/dv/tb/tb.sv
@@ -30,8 +30,8 @@
wire spi_device_sck;
wire spi_device_csb;
- wire spi_device_miso_o;
- wire spi_device_mosi_i;
+ wire spi_device_sdo_o;
+ wire spi_device_sdi_i;
wire srst_n;
wire jtag_spi_n;
@@ -136,14 +136,14 @@
// connect signals
assign io_dps[0] = jtag_spi_n ? jtag_tck : spi_device_sck;
- assign io_dps[1] = jtag_spi_n ? jtag_tdi : spi_device_mosi_i;
+ assign io_dps[1] = jtag_spi_n ? jtag_tdi : spi_device_sdi_i;
assign io_dps[3] = jtag_spi_n ? jtag_tms : spi_device_csb;
assign io_dps[4] = jtag_trst_n;
assign io_dps[5] = srst_n;
assign io_dps[6] = jtag_spi_n;
assign io_dps[7] = bootstrap;
- assign spi_device_miso_o = jtag_spi_n ? 1'b0 : io_dps[2];
- assign jtag_tdo = jtag_spi_n ? io_dps[2] : 1'b0;
+ assign spi_device_sdo_o = jtag_spi_n ? 1'b0 : io_dps[2];
+ assign jtag_tdo = jtag_spi_n ? io_dps[2] : 1'b0;
assign jtag_tck = jtag_if.tck;
assign jtag_tms = jtag_if.tms;
@@ -153,8 +153,8 @@
assign spi_device_sck = spi_if.sck;
assign spi_device_csb = spi_if.csb;
- assign spi_device_mosi_i = spi_if.mosi;
- assign spi_if.miso = spi_device_miso_o;
+ assign spi_device_sdi_i = spi_if.sdi;
+ assign spi_if.sdo = spi_device_sdo_o;
assign uart_rx = uart_if.uart_rx;
assign uart_if.uart_tx = uart_tx;
diff --git a/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson b/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
index a848785..2e652aa 100644
--- a/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
+++ b/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
@@ -2,7 +2,7 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
- // This is the master cfg hjson for DV simulations. It imports ALL individual DV sim
+ // This is a cfg hjson group for DV simulations. It includes ALL individual DV simulation
// cfgs of the IPs and the full chip used in top_earlgrey. This enables the common
// regression sets to be run in one shot.
name: top_earlgrey_batch_sim
diff --git a/hw/top_earlgrey/fpv/top_earlgrey_fpv_cfgs.hjson b/hw/top_earlgrey/fpv/top_earlgrey_fpv_cfgs.hjson
index 57521e0..c0f114c 100644
--- a/hw/top_earlgrey/fpv/top_earlgrey_fpv_cfgs.hjson
+++ b/hw/top_earlgrey/fpv/top_earlgrey_fpv_cfgs.hjson
@@ -3,7 +3,7 @@
// SPDX-License-Identifier: Apache-2.0
{
- // This is the master cfg hjson for FPV. It imports ALL individual FPV
+ // This is the primary cfg hjson for FPV. It imports ALL individual FPV
// cfgs of the IPs and the full chip used in top_earlgrey. This enables to run
// them all as a regression in one shot.
name: top_earlgrey_batch_fpv
diff --git a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson
index 974bb04..4aee36a 100644
--- a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson
+++ b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson
@@ -3,7 +3,7 @@
// SPDX-License-Identifier: Apache-2.0
{
- // This is the master cfg hjson for RTL linting. It imports ALL individual lint
+ // This is the primary cfg hjson for RTL linting. It imports ALL individual lint
// cfgs of the IPs and the full chip used in top_earlgrey. This enables to run
// them all as a regression in one shot.
name: top_earlgrey_batch
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index ba0d345..5d78507 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -134,9 +134,9 @@
// spi_device
logic cio_spi_device_sck_p2d;
logic cio_spi_device_csb_p2d;
- logic cio_spi_device_mosi_p2d;
- logic cio_spi_device_miso_d2p;
- logic cio_spi_device_miso_en_d2p;
+ logic cio_spi_device_sdi_p2d;
+ logic cio_spi_device_sdo_d2p;
+ logic cio_spi_device_sdo_en_d2p;
// flash_ctrl
// rv_timer
// aes
@@ -586,11 +586,11 @@
// Input
.cio_sck_i (cio_spi_device_sck_p2d),
.cio_csb_i (cio_spi_device_csb_p2d),
- .cio_mosi_i (cio_spi_device_mosi_p2d),
+ .cio_sdi_i (cio_spi_device_sdi_p2d),
// Output
- .cio_miso_o (cio_spi_device_miso_d2p),
- .cio_miso_en_o (cio_spi_device_miso_en_d2p),
+ .cio_sdo_o (cio_spi_device_sdo_d2p),
+ .cio_sdo_en_o (cio_spi_device_sdo_en_d2p),
// Interrupt
.intr_rxf_o (intr_spi_device_rxf),
@@ -1040,8 +1040,8 @@
assign dio_d2p = {
1'b0, // DIO14: cio_spi_device_sck
1'b0, // DIO13: cio_spi_device_csb
- 1'b0, // DIO12: cio_spi_device_mosi
- cio_spi_device_miso_d2p, // DIO11
+ 1'b0, // DIO12: cio_spi_device_sdi
+ cio_spi_device_sdo_d2p, // DIO11
1'b0, // DIO10: cio_uart_rx
cio_uart_tx_d2p, // DIO9
1'b0, // DIO8: cio_usbdev_sense
@@ -1058,8 +1058,8 @@
assign dio_d2p_en = {
1'b0, // DIO14: cio_spi_device_sck
1'b0, // DIO13: cio_spi_device_csb
- 1'b0, // DIO12: cio_spi_device_mosi
- cio_spi_device_miso_en_d2p, // DIO11
+ 1'b0, // DIO12: cio_spi_device_sdi
+ cio_spi_device_sdo_en_d2p, // DIO11
1'b0, // DIO10: cio_uart_rx
cio_uart_tx_en_d2p, // DIO9
1'b0, // DIO8: cio_usbdev_sense
@@ -1076,8 +1076,8 @@
// Output-only DIOs have no p2d signal
assign cio_spi_device_sck_p2d = dio_p2d[14]; // DIO14
assign cio_spi_device_csb_p2d = dio_p2d[13]; // DIO13
- assign cio_spi_device_mosi_p2d = dio_p2d[12]; // DIO12
- // DIO11: cio_spi_device_miso
+ assign cio_spi_device_sdi_p2d = dio_p2d[12]; // DIO12
+ // DIO11: cio_spi_device_sdo
assign cio_uart_rx_p2d = dio_p2d[10]; // DIO10
// DIO9: cio_uart_tx
assign cio_usbdev_sense_p2d = dio_p2d[8]; // DIO8
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
index 8d8004c..bf5b017 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
@@ -36,8 +36,8 @@
TopEarlgreyDioPinUsbdevSense = 8,
TopEarlgreyDioPinUartTx = 9,
TopEarlgreyDioPinUartRx = 10,
- TopEarlgreyDioPinSpiDeviceMiso = 11,
- TopEarlgreyDioPinSpiDeviceMosi = 12,
+ TopEarlgreyDioPinSpiDeviceSdo = 11,
+ TopEarlgreyDioPinSpiDeviceSdi = 12,
TopEarlgreyDioPinSpiDeviceCsb = 13,
TopEarlgreyDioPinSpiDeviceSck = 14,
TopEarlgreyDioPinCount = 15
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv b/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv
index fc3a897..8352fc3 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv
@@ -13,10 +13,10 @@
// JTAG interface -- not hooked up at the moment
// inout IO_DPS0, // IO_JTCK, IO_SDCK
// inout IO_DPS3, // IO_JTMS, IO_SDCSB
- // inout IO_DPS1, // IO_JTDI, IO_SDMOSI
+ // inout IO_DPS1, // IO_JTDI, IO_SDSDI
// inout IO_DPS4, // IO_JTRST_N,
// inout IO_DPS5, // IO_JSRST_N,
- // inout IO_DPS2, // IO_JTDO, IO_MISO
+ // inout IO_DPS2, // IO_JTDO, IO_SDO
// inout IO_DPS6, // JTAG=1, SPI=0
// inout IO_DPS7, // BOOTSTRAP=1
// UART interface
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
index aa2c121..20c4203 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
@@ -10,10 +10,10 @@
// JTAG interface
inout IO_DPS0, // IO_JTCK, IO_SDCK
inout IO_DPS3, // IO_JTMS, IO_SDCSB
- inout IO_DPS1, // IO_JTDI, IO_SDMOSI
+ inout IO_DPS1, // IO_JTDI, IO_SDSDI
inout IO_DPS4, // IO_JTRST_N,
inout IO_DPS5, // IO_JSRST_N,
- inout IO_DPS2, // IO_JTDO, IO_MISO
+ inout IO_DPS2, // IO_JTDO, IO_SDO
inout IO_DPS6, // JTAG=1, SPI=0
inout IO_DPS7, // BOOTSTRAP=1
// UART interface
@@ -105,8 +105,8 @@
// DIO Pads
.dio_pad_io ( { IO_DPS0, // SCK, JTAG_TCK
IO_DPS3, // CSB, JTAG_TMS
- IO_DPS1, // MOSI, JTAG_TDI
- IO_DPS2, // MISO, JTAG_TDO
+ IO_DPS1, // SDI, JTAG_TDI
+ IO_DPS2, // SDO, JTAG_TDO
IO_URX,
IO_UTX,
IO_USB_SENSE0,
@@ -162,9 +162,9 @@
.TrstIdx ( 18 ), // MIO 18
.SrstIdx ( 19 ), // MIO 19
.TdiIdx ( padctrl_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceMosi ),
+ top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSdi ),
.TdoIdx ( padctrl_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceMiso )
+ top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSdo )
) jtag_mux (
// To JTAG inside core
.jtag_tck_o ( jtag_tck ),
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv b/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv
index c219b3c..ced92de 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv
@@ -13,10 +13,10 @@
// JTAG interface
inout IO_DPS0, // IO_JTCK, IO_SDCK
inout IO_DPS3, // IO_JTMS, IO_SDCSB
- inout IO_DPS1, // IO_JTDI, IO_SDMOSI
+ inout IO_DPS1, // IO_JTDI, IO_SDSDI
inout IO_DPS4, // IO_JTRST_N,
inout IO_DPS5, // IO_JSRST_N,
- inout IO_DPS2, // IO_JTDO, IO_MISO
+ inout IO_DPS2, // IO_JTDO, IO_SDO
inout IO_DPS6, // JTAG=1, SPI=0
inout IO_DPS7, // BOOTSTRAP=1
// UART interface
@@ -127,8 +127,8 @@
// DIO Pads
.dio_pad_io ( { IO_DPS0, // SCK, JTAG_TCK
IO_DPS3, // CSB, JTAG_TMS
- IO_DPS1, // MOSI, JTAG_TDI
- IO_DPS2, // MISO, JTAG_TDO
+ IO_DPS1, // SDI, JTAG_TDI
+ IO_DPS2, // SDO, JTAG_TDO
IO_URX,
IO_UTX,
IO_USB_SENSE0,
@@ -184,9 +184,9 @@
.TrstIdx ( 18 ), // MIO 18
.SrstIdx ( 19 ), // MIO 19
.TdiIdx ( padctrl_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceMosi ),
+ top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSdi ),
.TdoIdx ( padctrl_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceMiso )
+ top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSdo )
) jtag_mux (
// To JTAG inside core
.jtag_tck_o ( jtag_tck ),
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
index 084c916..72329fe 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
@@ -13,10 +13,10 @@
// JTAG interface
inout IO_DPS0, // IO_JTCK, IO_SDCK
inout IO_DPS3, // IO_JTMS, IO_SDCSB
- inout IO_DPS1, // IO_JTDI, IO_SDMOSI
+ inout IO_DPS1, // IO_JTDI, IO_SDSDI
inout IO_DPS4, // IO_JTRST_N,
inout IO_DPS5, // IO_JSRST_N,
- inout IO_DPS2, // IO_JTDO, IO_MISO
+ inout IO_DPS2, // IO_JTDO, IO_SDO
inout IO_DPS6, // JTAG=1, SPI=0
inout IO_DPS7, // BOOTSTRAP=1
// UART interface
@@ -109,8 +109,8 @@
// DIO Pads
.dio_pad_io ( { IO_DPS0, // SCK, JTAG_TCK
IO_DPS3, // CSB, JTAG_TMS
- IO_DPS1, // MOSI, JTAG_TDI
- IO_DPS2, // MISO, JTAG_TDO
+ IO_DPS1, // SDI, JTAG_TDI
+ IO_DPS2, // SDO, JTAG_TDO
IO_URX,
IO_UTX,
IO_USB_SENSE0,
@@ -166,9 +166,9 @@
.TrstIdx ( 18 ), // MIO 18
.SrstIdx ( 19 ), // MIO 19
.TdiIdx ( padctrl_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceMosi ),
+ top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSdi ),
.TdoIdx ( padctrl_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceMiso )
+ top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSdo )
) jtag_mux (
// To JTAG inside core
.jtag_tck_o ( jtag_tck ),
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv b/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
index 189e5a0..b17bd86 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
@@ -15,8 +15,8 @@
logic cio_uart_rx_p2d, cio_uart_tx_d2p, cio_uart_tx_en_d2p;
logic cio_spi_device_sck_p2d, cio_spi_device_csb_p2d;
- logic cio_spi_device_mosi_p2d;
- logic cio_spi_device_miso_d2p, cio_spi_device_miso_en_d2p;
+ logic cio_spi_device_sdi_p2d;
+ logic cio_spi_device_sdo_d2p, cio_spi_device_sdo_en_d2p;
logic cio_usbdev_sense_p2d;
logic cio_usbdev_se0_d2p, cio_usbdev_se0_en_d2p;
@@ -37,7 +37,7 @@
assign dio_in = {cio_spi_device_sck_p2d,
cio_spi_device_csb_p2d,
- cio_spi_device_mosi_p2d,
+ cio_spi_device_sdi_p2d,
1'b0,
cio_uart_rx_p2d,
1'b0,
@@ -60,7 +60,7 @@
assign cio_usbdev_dp_pullup_d2p = dio_out[6];
assign cio_usbdev_se0_d2p = dio_out[7];
assign cio_uart_tx_d2p = dio_out[9];
- assign cio_spi_device_miso_d2p = dio_out[11];
+ assign cio_spi_device_sdo_d2p = dio_out[11];
assign cio_usbdev_dn_en_d2p = dio_oe[0];
assign cio_usbdev_dp_en_d2p = dio_oe[1];
@@ -71,7 +71,7 @@
assign cio_usbdev_dp_pullup_en_d2p = dio_oe[6];
assign cio_usbdev_se0_en_d2p = dio_oe[7];
assign cio_uart_tx_en_d2p = dio_oe[9];
- assign cio_spi_device_miso_en_d2p = dio_oe[11];
+ assign cio_spi_device_sdo_en_d2p = dio_oe[11];
// Top-level design
top_earlgrey top_earlgrey (
@@ -167,9 +167,9 @@
.rst_ni (rst_ni),
.spi_device_sck_o (cio_spi_device_sck_p2d),
.spi_device_csb_o (cio_spi_device_csb_p2d),
- .spi_device_mosi_o (cio_spi_device_mosi_p2d),
- .spi_device_miso_i (cio_spi_device_miso_d2p),
- .spi_device_miso_en_i (cio_spi_device_miso_en_d2p)
+ .spi_device_sdi_o (cio_spi_device_sdi_p2d),
+ .spi_device_sdo_i (cio_spi_device_sdo_d2p),
+ .spi_device_sdo_en_i (cio_spi_device_sdo_en_d2p)
);
// USB DPI
diff --git a/hw/top_earlgrey/syn/constraints.sdc b/hw/top_earlgrey/syn/constraints.sdc
index c5db867..3e496d5 100644
--- a/hw/top_earlgrey/syn/constraints.sdc
+++ b/hw/top_earlgrey/syn/constraints.sdc
@@ -17,8 +17,8 @@
#####################
set PORT_SPI_DEVICE_SCK 14
set PORT_SPI_DEVICE_CSB 13
-set PORT_SPI_DEVICE_MOSI 12
-set PORT_SPI_DEVICE_MISO 11
+set PORT_SPI_DEVICE_SDI 12
+set PORT_SPI_DEVICE_SDO 11
set PORT_UART_RX 10
set PORT_UART_TX 9
@@ -160,11 +160,11 @@
set IN_DEL 6.0
set OUT_DEL 6.0
-set_input_delay ${IN_DEL} [get_ports dio_in_i[$PORT_SPI_DEVICE_CSB]] -clock SPID_CLK
-set_input_delay ${IN_DEL} [get_ports dio_in_i[$PORT_SPI_DEVICE_MOSI]] -clock SPID_CLK
+set_input_delay ${IN_DEL} [get_ports dio_in_i[$PORT_SPI_DEVICE_CSB]] -clock SPID_CLK
+set_input_delay ${IN_DEL} [get_ports dio_in_i[$PORT_SPI_DEVICE_SDI]] -clock SPID_CLK
-set_output_delay ${OUT_DEL} [get_ports dio_out_o[$PORT_SPI_DEVICE_MISO]] -clock SPID_CLK
-set_output_delay ${OUT_DEL} [get_ports dio_oe_o[$PORT_SPI_DEVICE_MISO]] -clock SPID_CLK
+set_output_delay ${OUT_DEL} [get_ports dio_out_o[$PORT_SPI_DEVICE_SDO]] -clock SPID_CLK
+set_output_delay ${OUT_DEL} [get_ports dio_oe_o[$PORT_SPI_DEVICE_SDO]] -clock SPID_CLK
#####################
# CDC #
