switch to host, primary, or over-arching as appropriate
Signed-off-by: Scott Johnson <scottdj@google.com>
diff --git a/doc/ug/design.md b/doc/ug/design.md
index 4e64015..a845bd0 100644
--- a/doc/ug/design.md
+++ b/doc/ug/design.md
@@ -174,11 +174,11 @@
But our first goal is to take full advantage of the language as much as possible, and only resort to generated code where necessary.
At the moment, all generated code is checked in with the source files.
-The pros and cons of this decision are still being discussed, and the decision may be reversed, to be replaced with a master build-all script to prepare a final design as source files changed.
+The pros and cons of this decision are still being discussed, and the decision may be reversed, to be replaced with an over-arching build-all script to prepare a final design as source files changed.
Until that time, all generated files (see for example the output files from the
[register generation tool]({{< relref "doc/rm/register_tool" >}}))
are checked in.
-There is a master build file in the repository under `hw/Makefile` that builds all of the `regtool` content.
+There is an over-arching build file in the repository under `hw/Makefile` that builds all of the `regtool` content.
This is used by an Azure Pipelines pre-submit check script to ensure that the source files produce a generated file that is identical to the one being submitted.
## Getting Started with a Design
diff --git a/doc/ug/dv_methodology.md b/doc/ug/dv_methodology.md
index 3353f0e..f8c5a83 100644
--- a/doc/ug/dv_methodology.md
+++ b/doc/ug/dv_methodology.md
@@ -22,7 +22,7 @@
For professional tooling, the team has chosen [Synopsys' VCS](https://www.synopsys.com/verification/simulation/vcs.html) as the simulator of choice with respect to the tracking of verification completeness and [JasperGold](https://www.cadence.com/content/cadence-www/global/en_US/home/tools/system-design-and-verification/formal-and-static-verification/jasper-gold-verification-platform.html) for FPV.
Wherever possible we attempt to remain tool-agnostic, but we must choose a simulator as our ground truth for our own confidence of signoff-level assurances.
-Likewise, for FPV, [Synopsys VC Formal](https://www.synopsys.com/verification/static-and-formal-verification/vc-formal.html) is also supported within the same flow, and can be used by those with access to VC Formal licenses.
+Likewise, for FPV, [Synopsys VC Formal](https://www.synopsys.com/verification/static-and-formal-verification/vc-formal.html) is also supported within the same flow, and can be used by those with access to VC Formal licenses.
At this time there is also some support for Cadence's Xcelium, for those organizations which have few Synopsys VCS licenses.
However support is not as mature as for VCS, which remains the tool for signoff.
Furthermore, as a project we promote other open source verification methodologies - Verilator, Yosys, cocoTB, etc - and work towards a future where these are signoff-grade.
@@ -272,7 +272,7 @@
Categorizing such tests into a sanity suite provides a quick path for users who touch common / shared piece of code to run those tests for all DUTs and ensure no breakages occur.
If the DUT testbench has more than one compile-time configuration, there needs to be at least 1 sanity test per configuration.
-Ideally, the sanity regression is run as a part of the CI check whenever a PR is submitted. Due to use of proprietary tools for running DV simulations, this cannot be accomplished. Instead, we run a daily cron job locally on the up-to-date master branch to identify such breakages and deploy fixes quickly.
+Ideally, the sanity regression is run as a part of the CI check whenever a PR is submitted. Due to use of proprietary tools for running DV simulations, this cannot be accomplished. Instead, we run a daily cron job locally on the up-to-date `master` branch to identify such breakages and deploy fixes quickly.
### Nightly
diff --git a/doc/ug/getting_started_verilator.md b/doc/ug/getting_started_verilator.md
index 264c6fb..8d09d42 100644
--- a/doc/ug/getting_started_verilator.md
+++ b/doc/ug/getting_started_verilator.md
@@ -135,7 +135,7 @@
## SPI device test interface
-The simulation contains code to monitor the SPI bus and provide a master interface to allow interaction with the `spi_device`.
+The simulation contains code to monitor the SPI bus and provide a host interface to allow interaction with the `spi_device`.
When starting the simulation you should see a message like
```console
diff --git a/doc/ug/github_notes.md b/doc/ug/github_notes.md
index 30f8db2..22d2b00 100644
--- a/doc/ug/github_notes.md
+++ b/doc/ug/github_notes.md
@@ -79,9 +79,9 @@
## Working in your local repo
The repository that you have created locally will initially be on the
-**master** branch. In general you should not make changes on this
+`master` branch. In general you should not make changes on this
branch, just use it to track your GitHub repository and synchronize with the
-lowRISC master repo.
+main lowRISC repository.
The typical workflow is to make your own branch which it is
conventional to name based on the change you are making:
@@ -196,7 +196,7 @@
## Update your repository with changes in the lowRISC repo
There is a little work to do to keep everything in sync. Normally you
-want to first get your local repository master branch up to date with the
+want to first get your local repository `master` branch up to date with the
lowRISC repository (**upstream**) and then you use that to update your GitHub
copy (**origin**).
@@ -208,9 +208,9 @@
If you do this while you have changes on some other branch then before
a Pull Request will work you need to be sure your branch merges
-cleanly into the new lowRISC repo. Assuming you got the local master
+cleanly into the new lowRISC repo. Assuming you got the local `master`
branch up to date with the procedure above you can now **rebase** your
-changes on the new master. Assuming you have your changes on the local
+changes on the new `master`. Assuming you have your changes on the local
branch `forchange`:
```console
@@ -219,7 +219,7 @@
```
If you are lucky this will just work, it unwinds your changes, gets
-the updated master and replays your changes. If there are conflicts
+the updated `master` and replays your changes. If there are conflicts
then you need a big pot of coffee and patience (see next section).
Once everything has rebased properly you can do
@@ -230,7 +230,7 @@
```
And see that the changes you commited on the branch are at the top of
-the log followed by the latest changes on the master branch.
+the log followed by the latest changes on the `master` branch.
## Dealing with conflicts after a rebase
@@ -301,16 +301,20 @@
```
-In this case the master tree (between `<<<<<<< HEAD` and `=======`)
-was modified to import `docgen.generate` rather than just `docgen` and
-the local tree (between `=======` and `>>>>>>>` followed by the first
-line of the commit message) had been changed to re-order the
-imports. These lines have to be edited to get the correct merged
+In this case, the upstream repository's copy of `util/build_docs.py`
+was modified to import `docgen.generate` rather than just `docgen`.
+Because git couldn't automatically merge that change with the one
+we made, it gave up. The code between `<<<<<<< HEAD` and `=======`
+represents the change in the upstream repository and the code between
+`=======` and `>>>>>>>` represents the change in our copy.
+
+These lines have to be edited to get the correct merged
result and the diff markers removed. There may be multiple points in
the file where fixes are needed. Once all conflicts have been
addressed the file can be `git add`ed and once all files addressed the
rebase continued.
+
After the fix a status report will remind you where you are.
```console
@@ -350,7 +354,7 @@
You can check the rebase worked as expected by looking at the log to
see your branch is one commit (or more if there were more) ahead of
-the master branch.
+the `master` branch.
```console
$ git log
@@ -372,7 +376,7 @@
This shows the new commit (`HEAD` of the branch `sastyle`) and the
preceding commit is at the `master` branch (and at the same point as
`master` on both `origin` and `upstream` so everything is in sync at
-master).
+`master`).
At this point the conflicts have been cleared and the local repository can
be used as expected.
diff --git a/doc/ug/rust_for_c.md b/doc/ug/rust_for_c.md
index 4c4bfa1..52bc64a 100644
--- a/doc/ug/rust_for_c.md
+++ b/doc/ug/rust_for_c.md
@@ -54,7 +54,7 @@
* `std` and `core`, the standard libraries.
The Rust toolchain is on a six-week release cycle, similar to Chrome's: every six weeks, a release branch is cut as the next beta, and after six weeks it becomes the next stable.
-Nightly Rust is cut from master every day; it is on nightly that unstable features can be enabled.
+Nightly Rust is cut from `master` every day; it is on nightly that unstable features can be enabled.
Some unstable features[^5] are very useful for embedded, so it is not uncommon for embedded Rust projects to use a nightly compiler.
`rustup` is used for managing Rust installations.
@@ -572,7 +572,7 @@
``` rust
extern "C" {
fn malloc(bytes: usize) -> *mut u8;
- static mut errno: i32;
+ static mut errno: i32;
}
```
When the ABI specified is `"C"`, it can be left off; `extern {}` is implicitly `extern "C" {}`.
@@ -1879,7 +1879,7 @@
* `iter.enumerate()`.
Changes the `Item` type from `T` into `(usize, T)`, tracking the current index in the sequence along with the value.
* `iter.step_by(n)`.
- Changes the iterator to return every `n`th element.
+ Changes the iterator to return every `n`th element.
* `iter.take(n)`.
Shortens the iterator to return `n` elements before fusing.
* `iter.map(|x| /* ... */)`.
diff --git a/doc/ug/vendor_hw.md b/doc/ug/vendor_hw.md
index 21ddd60..ba29437 100644
--- a/doc/ug/vendor_hw.md
+++ b/doc/ug/vendor_hw.md
@@ -84,7 +84,7 @@
This description file essentially says:
We vendor a component called "lowrisc_ibex" and place the code into the "lowrisc_ibex" directory (relative to the description file).
-The code comes from the master branch of the Git repository found at https://github.com/lowRISC/ibex.git.
+The code comes from the `master` branch of the Git repository found at https://github.com/lowRISC/ibex.git.
With this description file written, the `util/vendor` tool can do its job.
diff --git a/hw/dv/dpi/spidpi/monitor_spi.c b/hw/dv/dpi/spidpi/monitor_spi.c
index e04b00e..9a63fb7 100644
--- a/hw/dv/dpi/spidpi/monitor_spi.c
+++ b/hw/dv/dpi/spidpi/monitor_spi.c
@@ -110,9 +110,9 @@
fprintf(mon_file, "%8d SPI: ", tick);
fprintf(mon_file, "%s ", vertical_bit(p2d, mon->prev_p2d, P2D_CSB, 0));
fprintf(mon_file, "%s ", vertical_bit(p2d, mon->prev_p2d, P2D_SCK, 0));
- fprintf(mon_file, "%s ", vertical_bit(p2d, mon->prev_p2d, P2D_MOSI, 0));
+ fprintf(mon_file, "%s ", vertical_bit(p2d, mon->prev_p2d, P2D_SDI, 0));
fprintf(mon_file, "%s ",
- vertical_bit(d2p, mon->prev_d2p, D2P_MISO, D2P_MISO_EN));
+ vertical_bit(d2p, mon->prev_d2p, D2P_SDO, D2P_SDO_EN));
}
static void log_packet(struct mon_ctx *mon, FILE *mon_file) {
@@ -130,14 +130,14 @@
static void capture_bit(struct mon_ctx *mon, FILE *mon_file, int p2d, int d2p) {
if (((mon->cpol == mon->cpha) && (p2d & P2D_SCK)) ||
((mon->cpol != mon->cpha) && !(p2d & P2D_SCK))) {
- uint32_t new_mobit = (p2d & P2D_MOSI) ? mon->bpos : 0;
- uint32_t new_sobit = (d2p & D2P_MISO) ? mon->bpos : 0;
+ uint32_t new_mobit = (p2d & P2D_SDI) ? mon->bpos : 0;
+ uint32_t new_sobit = (d2p & D2P_SDO) ? mon->bpos : 0;
// check for setup time
- if ((p2d & P2D_MOSI) != (mon->prev_p2d & P2D_MOSI)) {
- fprintf(mon_file, "Check MOSI tSU ");
+ if ((p2d & P2D_SDI) != (mon->prev_p2d & P2D_SDI)) {
+ fprintf(mon_file, "Check SDI tSU ");
}
- if ((d2p & D2P_MISO) != (mon->prev_d2p & D2P_MISO)) {
- fprintf(mon_file, "Check MISO tSU ");
+ if ((d2p & D2P_SDO) != (mon->prev_d2p & D2P_SDO)) {
+ fprintf(mon_file, "Check SDO tSU ");
}
mon->mobuf[mon->poff] |= new_mobit;
mon->sobuf[mon->poff] |= new_sobit;
diff --git a/hw/dv/dpi/spidpi/spidpi.c b/hw/dv/dpi/spidpi/spidpi.c
index 08a80d7..3827635 100644
--- a/hw/dv/dpi/spidpi/spidpi.c
+++ b/hw/dv/dpi/spidpi/spidpi.c
@@ -58,15 +58,15 @@
struct termios tty;
cfmakeraw(&tty);
- rv = openpty(&ctx->master, &ctx->slave, 0, &tty, 0);
+ rv = openpty(&ctx->host, &ctx->device, 0, &tty, 0);
assert(rv != -1);
- rv = ttyname_r(ctx->slave, ctx->ptyname, 64);
+ rv = ttyname_r(ctx->device, ctx->ptyname, 64);
assert(rv == 0 && "ttyname_r failed");
- int cur_flags = fcntl(ctx->master, F_GETFL, 0);
+ int cur_flags = fcntl(ctx->host, F_GETFL, 0);
assert(cur_flags != -1 && "Unable to read current flags.");
- int new_flags = fcntl(ctx->master, F_SETFL, cur_flags | O_NONBLOCK);
+ int new_flags = fcntl(ctx->host, F_SETFL, cur_flags | O_NONBLOCK);
assert(new_flags != -1 && "Unable to set FD flags");
printf(
@@ -99,7 +99,7 @@
assert(ctx);
int d2p = d2p_data->aval;
- // Will tick at the master clock
+ // Will tick at the host clock
ctx->tick++;
#ifdef CONTROL_TRACE
@@ -112,7 +112,7 @@
d2p);
if (ctx->state == SP_IDLE) {
- int n = read(ctx->master, &(ctx->buf[ctx->nin]), ctx->nmax - ctx->nin);
+ int n = read(ctx->host, &(ctx->buf[ctx->nin]), ctx->nmax - ctx->nin);
if (n == -1) {
if (errno != EAGAIN) {
fprintf(stderr, "Read on SPI FIFO gave %s\n", strerror(errno));
@@ -132,7 +132,7 @@
}
}
}
- // SPI clock toggles every 4th tick (i.e. freq=master/8)
+ // SPI clock toggles every 4th tick (i.e. freq=primary_frequency/8)
if ((ctx->tick & 3) || (ctx->state == SP_IDLE)) {
return ctx->driving;
}
@@ -145,12 +145,12 @@
}
if (internal_sck == ctx->cpha) {
- // master driving edge (falling for mode 0)
+ // host driving edge (falling for mode 0)
switch (ctx->state) {
case SP_DMOVE:
// SCLK low, CSB low
ctx->driving =
- set_sck | (ctx->buf[ctx->nout] & ctx->bout) ? P2D_MOSI : 0;
+ set_sck | (ctx->buf[ctx->nout] & ctx->bout) ? P2D_SDI : 0;
ctx->bout = (ctx->msbfirst) ? ctx->bout >> 1 : ctx->bout << 1;
if ((ctx->bout & 0xff) == 0) {
ctx->bout = ctx->msbfirst ? 0x80 : 0x01;
@@ -168,16 +168,16 @@
break;
}
} else {
- // master other edge (rising for mode 0)
+ // host other edge (rising for mode 0)
switch (ctx->state) {
// Read input data (opposite edge to sending)
// both DMOVE and LASTBIT states are data moving ones!
case SP_DMOVE:
case SP_LASTBIT:
- ctx->din = ctx->din | ((d2p & D2P_MISO) ? ctx->bin : 0);
+ ctx->din = ctx->din | ((d2p & D2P_SDO) ? ctx->bin : 0);
ctx->bin = (ctx->msbfirst) ? ctx->bin >> 1 : ctx->bin << 1;
if (ctx->bin == 0) {
- int rv = write(ctx->master, &(ctx->din), 1);
+ int rv = write(ctx->host, &(ctx->din), 1);
assert(rv == 1 && "write() failed.");
ctx->bin = (ctx->msbfirst) ? 0x80 : 0x01;
ctx->din = 0;
@@ -185,9 +185,9 @@
ctx->driving = set_sck | (ctx->driving & ~P2D_SCK);
break;
case SP_CSFALL:
- // CSB low, drive MOSI to first bit
+ // CSB low, drive SDI to first bit
ctx->driving =
- (set_sck | (ctx->buf[ctx->nout] & ctx->bout) ? P2D_MOSI : 0);
+ (set_sck | (ctx->buf[ctx->nout] & ctx->bout) ? P2D_SDI : 0);
ctx->state = SP_DMOVE;
break;
case SP_CSRISE:
diff --git a/hw/dv/dpi/spidpi/spidpi.h b/hw/dv/dpi/spidpi/spidpi.h
index a43184a..3bbe1b9 100644
--- a/hw/dv/dpi/spidpi/spidpi.h
+++ b/hw/dv/dpi/spidpi/spidpi.h
@@ -2,8 +2,8 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-#ifndef SPIDPI_H_
-#define SPIDPI_H_
+#ifndef OPENTITAN_HW_DV_DPI_SPIDPI_SPIDPI_H_
+#define OPENTITAN_HW_DV_DPI_SPIDPI_SPIDPI_H_
#include <limits.h>
#include <svdpi.h>
@@ -14,8 +14,8 @@
struct spidpi_ctx {
int loglevel;
char ptyname[64];
- int master;
- int slave;
+ int host;
+ int device;
FILE *mon_file;
char mon_pathname[PATH_MAX];
void *mon;
@@ -34,22 +34,22 @@
char buf[MAX_TRANSACTION];
};
-// SPI Master States
-#define SP_IDLE 0
-#define SP_CSFALL 1
-#define SP_DMOVE 2
+// SPI Host States
+#define SP_IDLE 0
+#define SP_CSFALL 1
+#define SP_DMOVE 2
#define SP_LASTBIT 3
-#define SP_CSRISE 4
-#define SP_FINISH 99
+#define SP_CSRISE 4
+#define SP_FINISH 99
// Bits in data to C
-#define D2P_MISO 0x2
-#define D2P_MISO_EN 0x1
+#define D2P_SDO 0x2
+#define D2P_SDO_EN 0x1
// Bits in char from C
-#define P2D_SCK 0x1
-#define P2D_CSB 0x2
-#define P2D_MOSI 0x4
+#define P2D_SCK 0x1
+#define P2D_CSB 0x2
+#define P2D_SDI 0x4
void *spidpi_create(const char *name, int mode, int loglevel);
char spidpi_tick(void *ctx_void, const svLogicVecVal *d2p_data);
@@ -60,4 +60,4 @@
int p2d, int d2p);
void *monitor_spi_init(int mode);
}
-#endif // SPIDPI_H_
+#endif // OPENTITAN_HW_DV_DPI_SPIDPI_SPIDPI_H_
diff --git a/hw/dv/dpi/spidpi/spidpi.sv b/hw/dv/dpi/spidpi/spidpi.sv
index fb4d959..68ca7bc 100644
--- a/hw/dv/dpi/spidpi/spidpi.sv
+++ b/hw/dv/dpi/spidpi/spidpi.sv
@@ -18,9 +18,9 @@
input logic rst_ni,
output logic spi_device_sck_o,
output logic spi_device_csb_o,
- output logic spi_device_mosi_o,
- input logic spi_device_miso_i,
- input logic spi_device_miso_en_i
+ output logic spi_device_sdi_o,
+ input logic spi_device_sdo_i,
+ input logic spi_device_sdo_en_i
);
import "DPI-C" function
@@ -46,12 +46,12 @@
logic [1:0] d2p;
logic unused_dummy;
- assign d2p = { spi_device_miso_i, spi_device_miso_en_i};
+ assign d2p = { spi_device_sdo_i, spi_device_sdo_en_i};
always_ff @(posedge clk_i) begin
automatic byte p2d = spidpi_tick(ctx, d2p);
spi_device_sck_o <= p2d[0];
spi_device_csb_o <= p2d[1];
- spi_device_mosi_o <= p2d[2];
+ spi_device_sdi_o <= p2d[2];
// stop verilator warning
unused_dummy <= |p2d[7:3];
end
diff --git a/hw/dv/dpi/uartdpi/uartdpi.c b/hw/dv/dpi/uartdpi/uartdpi.c
index 2d7784b..eecd0c1 100644
--- a/hw/dv/dpi/uartdpi/uartdpi.c
+++ b/hw/dv/dpi/uartdpi/uartdpi.c
@@ -26,15 +26,15 @@
struct termios tty;
cfmakeraw(&tty);
- rv = openpty(&ctx->master, &ctx->slave, 0, &tty, 0);
+ rv = openpty(&ctx->host, &ctx->device, 0, &tty, 0);
assert(rv != -1);
- rv = ttyname_r(ctx->slave, ctx->ptyname, 64);
+ rv = ttyname_r(ctx->device, ctx->ptyname, 64);
assert(rv == 0 && "ttyname_r failed");
- int cur_flags = fcntl(ctx->master, F_GETFL, 0);
+ int cur_flags = fcntl(ctx->host, F_GETFL, 0);
assert(cur_flags != -1 && "Unable to read current flags.");
- int new_flags = fcntl(ctx->master, F_SETFL, cur_flags | O_NONBLOCK);
+ int new_flags = fcntl(ctx->host, F_SETFL, cur_flags | O_NONBLOCK);
assert(new_flags != -1 && "Unable to set FD flags");
printf(
@@ -49,7 +49,7 @@
int uartdpi_can_read(void *ctx_void) {
struct uartdpi_ctx *ctx = (struct uartdpi_ctx *)ctx_void;
- int rv = read(ctx->master, &ctx->tmp_read, 1);
+ int rv = read(ctx->host, &ctx->tmp_read, 1);
return (rv == 1);
}
@@ -62,6 +62,6 @@
void uartdpi_write(void *ctx_void, char c) {
struct uartdpi_ctx *ctx = (struct uartdpi_ctx *)ctx_void;
- int rv = write(ctx->master, &c, 1);
+ int rv = write(ctx->host, &c, 1);
assert(rv == 1 && "write() failed.");
}
diff --git a/hw/dv/dpi/uartdpi/uartdpi.h b/hw/dv/dpi/uartdpi/uartdpi.h
index 286b05c..e4c6473 100644
--- a/hw/dv/dpi/uartdpi/uartdpi.h
+++ b/hw/dv/dpi/uartdpi/uartdpi.h
@@ -2,14 +2,14 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-#ifndef UARTDPI_H_
-#define UARTDPI_H_
+#ifndef OPENTITAN_HW_DV_DPI_UARTDPI_UARTDPI_H_
+#define OPENTITAN_HW_DV_DPI_UARTDPI_UARTDPI_H_
extern "C" {
struct uartdpi_ctx {
char ptyname[64];
- int master;
- int slave;
+ int host;
+ int device;
char tmp_read;
};
@@ -18,4 +18,4 @@
char uartdpi_read(void *ctx_void);
void uartdpi_write(void *ctx_void, char c);
}
-#endif // UARTDPI_H_
+#endif // OPENTITAN_HW_DV_DPI_UARTDPI_UARTDPI_H_
diff --git a/hw/dv/sv/spi_agent/spi_device_driver.sv b/hw/dv/sv/spi_agent/spi_device_driver.sv
index 69a0f2c..f1684f5 100644
--- a/hw/dv/sv/spi_agent/spi_device_driver.sv
+++ b/hw/dv/sv/spi_agent/spi_device_driver.sv
@@ -10,7 +10,7 @@
forever begin
@(negedge cfg.vif.rst_n);
under_reset = 1'b1;
- cfg.vif.miso <= 1'b0;
+ cfg.vif.sdo <= 1'b0;
@(posedge cfg.vif.rst_n);
under_reset = 1'b0;
end
diff --git a/hw/dv/sv/spi_agent/spi_host_driver.sv b/hw/dv/sv/spi_agent/spi_host_driver.sv
index e2985e1..e01f613 100644
--- a/hw/dv/sv/spi_agent/spi_host_driver.sv
+++ b/hw/dv/sv/spi_agent/spi_host_driver.sv
@@ -22,7 +22,7 @@
under_reset = 1'b1;
cfg.vif.sck <= cfg.sck_polarity;
cfg.vif.csb <= 1'b1;
- cfg.vif.mosi <= 1'bx;
+ cfg.vif.sdi <= 1'bx;
sck_pulses = 0;
@(posedge cfg.vif.rst_n);
under_reset = 1'b0;
@@ -93,13 +93,13 @@
int which_bit;
host_byte = req.data[i];
for (int j = 0; j < 8; j++) begin
- // drive mosi early so that it is stable at the sampling edge
+ // drive sdi early so that it is stable at the sampling edge
which_bit = cfg.host_bit_dir ? j : 7 - j;
- cfg.vif.mosi <= host_byte[which_bit];
- // wait for sampling edge to sample miso (half cycle)
+ cfg.vif.sdi <= host_byte[which_bit];
+ // wait for sampling edge to sample sdo (half cycle)
cfg.wait_sck_edge(SamplingEdge);
which_bit = cfg.device_bit_dir ? j : 7 - j;
- device_byte[which_bit] = cfg.vif.miso;
+ device_byte[which_bit] = cfg.vif.sdo;
// wait for driving edge to complete 1 cycle
if (i != req.data.size() - 1 || j != 7) cfg.wait_sck_edge(DrivingEdge);
end
@@ -108,7 +108,7 @@
wait(sck_pulses == 0);
cfg.vif.csb <= 1'b1;
- cfg.vif.mosi <= 1'bx;
+ cfg.vif.sdi <= 1'bx;
endtask
task drive_sck_no_csb_item();
diff --git a/hw/dv/sv/spi_agent/spi_if.sv b/hw/dv/sv/spi_agent/spi_if.sv
index 6ec134c..06a23b4 100755
--- a/hw/dv/sv/spi_agent/spi_if.sv
+++ b/hw/dv/sv/spi_agent/spi_if.sv
@@ -7,8 +7,8 @@
// standard spi interface pins
logic sck;
logic csb;
- logic miso;
- logic mosi;
+ logic sdo;
+ logic sdi;
// debug signals
logic [7:0] host_byte;
diff --git a/hw/dv/sv/spi_agent/spi_monitor.sv b/hw/dv/sv/spi_agent/spi_monitor.sv
index 77d89a9..8d47573 100755
--- a/hw/dv/sv/spi_agent/spi_monitor.sv
+++ b/hw/dv/sv/spi_agent/spi_monitor.sv
@@ -51,27 +51,27 @@
// for mode 1 and 3, get the leading edges out of the way
cfg.wait_sck_edge(LeadingEdge);
forever begin
- bit [7:0] host_byte; // from mosi
- bit [7:0] device_byte; // from miso
+ bit [7:0] host_byte; // from sdi
+ bit [7:0] device_byte; // from sdo
int which_bit;
for (int i = 0; i < 8; i++) begin
// wait for the sampling edge
cfg.wait_sck_edge(SamplingEdge);
- // check mosi/miso not x or z
+ // check sdi/sdo not x or z
if (cfg.en_monitor_checks) begin
- `DV_CHECK_CASE_NE(cfg.vif.mosi, 1'bx)
- `DV_CHECK_CASE_NE(cfg.vif.mosi, 1'bz)
- `DV_CHECK_CASE_NE(cfg.vif.miso, 1'bx)
- `DV_CHECK_CASE_NE(cfg.vif.miso, 1'bz)
+ `DV_CHECK_CASE_NE(cfg.vif.sdi, 1'bx)
+ `DV_CHECK_CASE_NE(cfg.vif.sdi, 1'bz)
+ `DV_CHECK_CASE_NE(cfg.vif.sdo, 1'bx)
+ `DV_CHECK_CASE_NE(cfg.vif.sdo, 1'bz)
end
- // sample mosi
+ // sample sdi
which_bit = cfg.host_bit_dir ? i : 7 - i;
- host_byte[which_bit] = cfg.vif.mosi;
+ host_byte[which_bit] = cfg.vif.sdi;
cfg.vif.host_bit = which_bit;
cfg.vif.host_byte = host_byte;
- // sample miso
+ // sample sdo
which_bit = cfg.device_bit_dir ? i : 7 - i;
- device_byte[which_bit] = cfg.vif.miso;
+ device_byte[which_bit] = cfg.vif.sdo;
cfg.vif.device_bit = which_bit;
cfg.vif.device_byte = device_byte;
end
diff --git a/hw/dv/sv/tl_agent/tl_agent_cfg.sv b/hw/dv/sv/tl_agent/tl_agent_cfg.sv
index 52898c1..9a37ac4 100644
--- a/hw/dv/sv/tl_agent/tl_agent_cfg.sv
+++ b/hw/dv/sv/tl_agent/tl_agent_cfg.sv
@@ -14,7 +14,7 @@
tl_level_e tl_level = kTLUL;
// Maximum outstanding transaction
- // 0: Unlimited from the master perspective, might be back-pressured by the slave
+ // 0: Unlimited from the host perspective, might be back-pressured by the device
// 1: Only single transaction at a time
// n: Number of maximum oustanding requests
diff --git a/hw/ip/entropy_src/data/entropy_src.hjson b/hw/ip/entropy_src/data/entropy_src.hjson
index 703ef4a..cb16588 100755
--- a/hw/ip/entropy_src/data/entropy_src.hjson
+++ b/hw/ip/entropy_src/data/entropy_src.hjson
@@ -97,8 +97,8 @@
fields: [
{ bits: "1:0",
name: "ENABLE",
- desc: '''Master enable for the ENTROPY_SRC entropy generation function.
- This two bit field determines what source will be used for health
+ desc: '''Primary enable for the ENTROPY_SRC entropy generation function.
+ This two bit field determines what source will be used for health
check processing:
0b00: Disabled
0b01: LFSR mode enabled
diff --git a/hw/ip/entropy_src/pre_dv/entropy_src_tb.sv b/hw/ip/entropy_src/pre_dv/entropy_src_tb.sv
index 9a3385d..c162776 100755
--- a/hw/ip/entropy_src/pre_dv/entropy_src_tb.sv
+++ b/hw/ip/entropy_src/pre_dv/entropy_src_tb.sv
@@ -3,12 +3,12 @@
// SPDX-License-Identifier: Apache-2.0
//
// Description: entropy_src system verilog unit test bench
-// The intent of this test bench is to get basics running,
+// The intent of this test bench is to get basics running,
// such as clocks and reset, basic register writes and reads,
// basic block operation. No configurable BFMs are included
// in this environment.
-module entropy_src_tb;
+module entropy_src_tb;
import tlul_pkg::*;
import entropy_src_reg_pkg::*;
@@ -19,7 +19,7 @@
bit lfsr_update_test = 0;
bit basic_entropy_test = 0;
bit stress_test = 1;
-
+
// options
bit msg_rd_data = 0;
@@ -27,7 +27,7 @@
localparam EsFifoDepth = 32;
localparam MAX_INTRP_CNT = 25;
localparam WD_DELAY = 1000*MAX_INTRP_CNT;
-
+
// general signals
logic clk;
logic rst_n;
@@ -37,10 +37,10 @@
// tlul signals
tlul_pkg::tl_h2d_t tl_i;
tlul_pkg::tl_d2h_t tl_o;
-
+
// imported register parameters (for reference)
-
+
// Register Address
// parameter ENTROPY_SRC_INTR_STATE_OFFSET = 6'h 0;
// parameter ENTROPY_SRC_INTR_ENABLE_OFFSET = 6'h 4;
@@ -73,15 +73,15 @@
tl_i.a_valid = 0;
tl_i.a_address = 0;
tl_i.a_opcode = PutFullData; // write as default
- tl_i.a_param = 3'h0;
- tl_i.a_size = 2'h0;
- tl_i.a_source = 8'h0;
- tl_i.a_user = 0;
+ tl_i.a_param = 3'h0;
+ tl_i.a_size = 2'h0;
+ tl_i.a_source = 8'h0;
+ tl_i.a_user = 0;
tl_i.a_mask = 0;
tl_i.a_data = 0;
tl_i.d_ready =1;
end
-
+
initial // clock generation
begin
clk = 0;
@@ -91,14 +91,14 @@
end
initial // reset generation
- begin
- repeat (4) @ (posedge clk);
+ begin
+ repeat (4) @ (posedge clk);
rst_n = 1;
end
initial // watchdog
- begin
- repeat (WD_DELAY) @ (posedge clk);
+ begin
+ repeat (WD_DELAY) @ (posedge clk);
$display("%t %c[1;31mEntropy_Src watchdog triggered - FAIL!!! %c[0m",$time,27,27);
$finish;
end
@@ -112,22 +112,22 @@
tl_i.a_valid =1;
tl_i.a_address = addr;
tl_i.a_opcode = PutFullData; // write = 0
- tl_i.a_param = 3'h0;
- tl_i.a_size = 2'h2;
- tl_i.a_source = 8'h0;
+ tl_i.a_param = 3'h0;
+ tl_i.a_size = 2'h2;
+ tl_i.a_source = 8'h0;
tl_i.a_mask = 4'hf;
tl_i.a_data = wdata;
repeat (1) @ (posedge clk); #1ps;
tl_i.a_valid = 0;
tl_i.a_address = 0;
tl_i.a_opcode = PutFullData; // write as default
- tl_i.a_param = 3'h0;
- tl_i.a_size = 2'h0;
- tl_i.a_source = 8'h0;
+ tl_i.a_param = 3'h0;
+ tl_i.a_size = 2'h0;
+ tl_i.a_source = 8'h0;
tl_i.a_mask = 0;
tl_i.a_data = 0;
repeat (1) @ (posedge clk); #1ps;
- endtask
+ endtask
task rd_reg(input logic [31:0] addr, output logic [31:0] rdata);
repeat (1) @ (posedge clk); #1ps;
@@ -138,9 +138,9 @@
tl_i.a_valid =1;
tl_i.a_address = addr;
tl_i.a_opcode = Get; // read = 4
- tl_i.a_param = 3'h0;
- tl_i.a_size = 2'h2;
- tl_i.a_source = 8'h0;
+ tl_i.a_param = 3'h0;
+ tl_i.a_size = 2'h2;
+ tl_i.a_source = 8'h0;
tl_i.a_mask = 4'hf;
while (tl_o.d_valid != 1) begin
repeat (1) @ (posedge clk); #1ps;
@@ -149,15 +149,15 @@
tl_i.d_ready = 1;
tl_i.a_address = 0;
tl_i.a_opcode = PutFullData; // write as default
- tl_i.a_param = 3'h0;
- tl_i.a_size = 2'h0;
- tl_i.a_source = 8'h0;
+ tl_i.a_param = 3'h0;
+ tl_i.a_size = 2'h0;
+ tl_i.a_source = 8'h0;
tl_i.a_mask = 0;
tl_i.a_data = 0;
rdata = tl_o.d_data;
if (msg_rd_data) $display("%t rdata = %h",$time,rdata);
repeat (1) @ (posedge clk); #1ps;
- endtask
+ endtask
task cmp_reg(input logic [31:0] addr, logic [31:0] cdata, logic [31:0] cmask);
logic [31:0] rdata;
@@ -171,9 +171,9 @@
$finish;
// errflag = 1;
end
- endtask
+ endtask
-
+
task test_end(input bit errflag);
cmp_reg(ENTROPY_SRC_ES_STATUS_OFFSET,32'h0000_0000,32'hffff_ffff);
if (errflag == 1) begin
@@ -182,20 +182,20 @@
$display("%t %c[1;32mEntropy_Src Test PASSED... %c[0m",$time,27,27);
end
$finish;
- endtask
+ endtask
-
+
always @ (posedge es_entropy_valid_o) // interrupt handler
begin
if (rst_n) begin // handle reset case
if (stress_test) begin
rd_data = 0;
for (int i=0; i < thresh_level; i=i+1) begin
- rd_reg({26'b0,ENTROPY_SRC_ES_ENTROPY_OFFSET},rd_data);
+ rd_reg({26'b0,ENTROPY_SRC_ES_ENTROPY_OFFSET},rd_data);
end
repeat (1) @ (posedge clk); #1ps;
// reset interrupt
- wr_reg({26'b0,ENTROPY_SRC_INTR_STATE_OFFSET},32'h0000_0001);
+ wr_reg({26'b0,ENTROPY_SRC_INTR_STATE_OFFSET},32'h0000_0001);
if (es_entropy_valid_o !== 0) begin
$display("%t %c[1;31mInterrupt did not reset FAIL!!! %c[0m",$time,27,27);
$finish;
@@ -225,10 +225,10 @@
//-----------------------------------------------------
if (sanity_test) begin
$display("%t Running sanity_test...",$time);
- cmp_reg({26'b0,ENTROPY_SRC_ES_SEED_OFFSET},32'h1234_5678,32'hffff_ffff);
+ cmp_reg({26'b0,ENTROPY_SRC_ES_SEED_OFFSET},32'h1234_5678,32'hffff_ffff);
wr_reg({26'b0,ENTROPY_SRC_ES_SEED_OFFSET},32'habdc_efab); // wr config reg
- cmp_reg({26'b0,ENTROPY_SRC_ES_SEED_OFFSET},32'habdc_efab,32'hffff_ffff);
- cmp_reg({26'b0,ENTROPY_SRC_ES_REV_OFFSET},32'h0001_0201,32'hffff_ffff);
+ cmp_reg({26'b0,ENTROPY_SRC_ES_SEED_OFFSET},32'habdc_efab,32'hffff_ffff);
+ cmp_reg({26'b0,ENTROPY_SRC_ES_REV_OFFSET},32'h0001_0201,32'hffff_ffff);
end
//-----------------------------------------------------
if (interrupt_test) begin
@@ -236,14 +236,14 @@
wr_reg({26'b0,ENTROPY_SRC_INTR_ENABLE_OFFSET},32'h0000_0003); // enable intrs
cmp_reg({26'b0,ENTROPY_SRC_INTR_STATE_OFFSET},32'h000000000,32'hffff_ffff); // check to see that interrupts are off
// test intrp 0
- wr_reg({26'b0,ENTROPY_SRC_INTR_TEST_OFFSET},32'h0000_0001);
+ wr_reg({26'b0,ENTROPY_SRC_INTR_TEST_OFFSET},32'h0000_0001);
cmp_reg({26'b0,ENTROPY_SRC_INTR_STATE_OFFSET},32'h000000001,32'hffff_ffff); // check interrupt state
- wr_reg({26'b0,ENTROPY_SRC_INTR_STATE_OFFSET},32'h0000_0001);
+ wr_reg({26'b0,ENTROPY_SRC_INTR_STATE_OFFSET},32'h0000_0001);
cmp_reg({26'b0,ENTROPY_SRC_INTR_STATE_OFFSET},32'h000000000,32'hffff_ffff); // check to see that interrupts are off
// test intrp 1
- wr_reg({26'b0,ENTROPY_SRC_INTR_TEST_OFFSET},32'h0000_0002);
+ wr_reg({26'b0,ENTROPY_SRC_INTR_TEST_OFFSET},32'h0000_0002);
cmp_reg({26'b0,ENTROPY_SRC_INTR_STATE_OFFSET},32'h000000002,32'hffff_ffff); // check interrupt state
- wr_reg({26'b0,ENTROPY_SRC_INTR_STATE_OFFSET},32'h0000_0002);
+ wr_reg({26'b0,ENTROPY_SRC_INTR_STATE_OFFSET},32'h0000_0002);
cmp_reg({26'b0,ENTROPY_SRC_INTR_STATE_OFFSET},32'h000000000,32'hffff_ffff); // check to see that interrupts are off
end
//-----------------------------------------------------
@@ -252,7 +252,7 @@
wr_reg({26'b0,ENTROPY_SRC_ES_RATE_OFFSET},32'h0000_0001); // rate
wr_reg({26'b0,ENTROPY_SRC_ES_THRESH_OFFSET},32'h0000_0001); // thresh level
wr_reg({26'b0,ENTROPY_SRC_ES_SEED_OFFSET},32'h1111_1111); // seed
- wr_reg({26'b0,ENTROPY_SRC_ES_CONF_OFFSET},32'h0000_0001); // master enable
+ wr_reg({26'b0,ENTROPY_SRC_ES_CONF_OFFSET},32'h0000_0001); // primary enable
repeat (10) @ (posedge clk);
wr_reg({26'b0,ENTROPY_SRC_ES_SEED_OFFSET},32'h2222_2222); // change seed, should not write since fifo is not full
wr_reg({26'b0,ENTROPY_SRC_ES_CTRL_OFFSET},32'h0000_0001); // init bit on
@@ -273,10 +273,10 @@
wr_reg({26'b0,ENTROPY_SRC_ES_RATE_OFFSET},32'h0000_0000); // rate turned off
// drain the fifo
for (int i=0; i < 32; i=i+1) begin
- rd_reg({26'b0,ENTROPY_SRC_ES_ENTROPY_OFFSET},rd_data);
+ rd_reg({26'b0,ENTROPY_SRC_ES_ENTROPY_OFFSET},rd_data);
end
// clear any interrupts
- wr_reg({26'b0,ENTROPY_SRC_INTR_STATE_OFFSET},32'h0000_0003);
+ wr_reg({26'b0,ENTROPY_SRC_INTR_STATE_OFFSET},32'h0000_0003);
end
//-----------------------------------------------------
if (basic_entropy_test) begin
@@ -286,7 +286,7 @@
wr_reg({26'b0,ENTROPY_SRC_ES_SEED_OFFSET},32'h2345_3456); // seed
wr_reg({26'b0,ENTROPY_SRC_ES_RATE_OFFSET},32'h0000_0008); // rate
wr_reg({26'b0,ENTROPY_SRC_ES_THRESH_OFFSET},thresh_level); // thresh level
- wr_reg({26'b0,ENTROPY_SRC_ES_CONF_OFFSET},32'h0000_0001); // master enable
+ wr_reg({26'b0,ENTROPY_SRC_ES_CONF_OFFSET},32'h0000_0001); // primary enable
// read out entropy
rd_data = 0;
repeat (20) @ (posedge clk);
@@ -296,12 +296,12 @@
// set entropy to super slow
wr_reg({26'b0,ENTROPY_SRC_ES_RATE_OFFSET},32'h0000_ffff); // rate
for (int i=0; i < thresh_level; i=i+1) begin
- rd_reg({26'b0,ENTROPY_SRC_ES_ENTROPY_OFFSET},rd_data);
+ rd_reg({26'b0,ENTROPY_SRC_ES_ENTROPY_OFFSET},rd_data);
end
rd_reg({26'b0,ENTROPY_SRC_ES_FDEPTHST_OFFSET},fifo_depth);
// drain the rest of the fifo
for (int i=0; i < fifo_depth; i=i+1) begin
- rd_reg({26'b0,ENTROPY_SRC_ES_ENTROPY_OFFSET},rd_data);
+ rd_reg({26'b0,ENTROPY_SRC_ES_ENTROPY_OFFSET},rd_data);
end
repeat (10) @ (posedge clk);
end
@@ -313,7 +313,7 @@
wr_reg({26'b0,ENTROPY_SRC_ES_SEED_OFFSET},32'h2345_3456); // seed
wr_reg({26'b0,ENTROPY_SRC_ES_RATE_OFFSET},32'h0000_0006); // rate
wr_reg({26'b0,ENTROPY_SRC_ES_THRESH_OFFSET},thresh_level); // thresh level
- wr_reg({26'b0,ENTROPY_SRC_ES_CONF_OFFSET},32'h0000_0001); // master enable
+ wr_reg({26'b0,ENTROPY_SRC_ES_CONF_OFFSET},32'h0000_0001); // primary enable
// wait for interrupts to process
while (intrp_cnt < MAX_INTRP_CNT) begin
repeat (20) @ (posedge clk);
@@ -324,7 +324,7 @@
test_end(errflag);
end
-
+
//-------------------------------------
// entropy_src instantiation
//-------------------------------------
@@ -339,6 +339,6 @@
.es_entropy_valid_o(es_entropy_valid_o),
.es_entropy_fifo_err_o(es_entropy_fifo_err_o)
);
-
+
endmodule
diff --git a/hw/ip/i2c/data/i2c.hjson b/hw/ip/i2c/data/i2c.hjson
index ce1efe2..2ca317a 100644
--- a/hw/ip/i2c/data/i2c.hjson
+++ b/hw/ip/i2c/data/i2c.hjson
@@ -32,7 +32,7 @@
desc: "raised if the SCL line drops early (not supported without clock synchronization)."
}
{ name: "sda_interference"
- desc: "raised if the SDA line goes low when master is trying to assert high"
+ desc: "raised if the SDA line goes low when host is trying to assert high"
}
{ name: "stretch_timeout"
desc: "raised if target stretches the clock beyond the allowed timeout period"
diff --git a/hw/ip/i2c/doc/_index.md b/hw/ip/i2c/doc/_index.md
index dccf56f..2b6f5d0 100644
--- a/hw/ip/i2c/doc/_index.md
+++ b/hw/ip/i2c/doc/_index.md
@@ -4,20 +4,20 @@
---
-# Overview
+# Overview
This document specifies I2C hardware IP functionality.
This module conforms to the [Comportable guideline for peripheral functionality.]({{< relref "doc/rm/comportability_specification/index.md" >}})
See that document for integration overview within the broader top level system.
-## Features
+## Features
-- Two-pin clock-data parallel bidirectional external interface
+- Two-pin clock-data parallel bidirectional external interface
- The initial revision only supports I2C as a Host ("I2C Master"<sup>1</sup>).
- Support for standard (100 kbaud), fast (400 kbaud) and fast-plus (1 Mbaud) modes
- Bandwidth up to 1 Mbaud
-- Support for all "Mandatory" features as specified for I2C Hosts (as listed in Table 2 of the [I2C specification](https://www.nxp.com/docs/en/user-guide/UM10204.pdf)):
+- Support for all "Mandatory" features as specified for I2C Hosts (as listed in Table 2 of the [I2C specification](https://www.nxp.com/docs/en/user-guide/UM10204.pdf)):
- Start Condition
- Stop Condition
- Acknowledge
@@ -29,17 +29,17 @@
- *No support at this time* for any of the features related to multi-host control:
- No support for host-host clock synchronization
- No support for host bus arbitration.
-- Byte-formatted register interface with two separate queues, one for holding read data, the other for holding bytes to be transmitted (addresses or write data)
+- Byte-formatted register interface with two separate queues, one for holding read data, the other for holding bytes to be transmitted (addresses or write data)
- Direct SCL and SDA control in "Override mode" (for debugging)
- SCL and SDA ports mapped to I/O via the pinmux.
- Interrupts for FIFO overflow, target NACK, SCL/SDA signal interference, timeout, unstable SDA signal levels, and transaction complete.
<sup>1</sup> lowRISC is avoiding the fraught terms master/slave and defaulting to host/target where applicable.
-## Description
+## Description
This IP block implements the [I2C specification](https://www.nxp.com/docs/en/user-guide/UM10204.pdf), though with some variation in nomenclature.
-For the purposes of this document, a "I2C Host" meets the specifications put forth for a "Master" device.
+For the purposes of this document, a "I2C Host" meets the specifications put forth for a "Master" device.
Furthermore, a device which meets the specifications put forward for an I2C "Slave" device is here referred to as an "I2C Target" or "I2C Target Device".
At a high-level, the I2C protocol is a clock-parallel serial protocol, with at least one host issuing transactions to a number of targets on the same bus.
@@ -51,14 +51,14 @@
1. A START signal, issued by host.
1. An address, issued by host, encoded as 7 or 10 bits.
1. A R/W bit indicating whether the transaction is a read from the target device, or a write to the target device.
-The R/W bit is encoded along with the address.
-1. An Acknowledge signal (ACK) sent by the target device.
+The R/W bit is encoded along with the address.
+1. An Acknowledge signal (ACK) sent by the target device.
1. Data bytes, where the number of bytes required is indicated by the host,
in a manner which differs between reads and writes.
- For write transactions, the target device sends an ACK signal after every byte received.
The host indicates the end of a transaction by sending a STOP or RESTART signal.
- For read transactions, the target device continues to send data as long as the host acknowledges the target-issued data by sending an ACK signal.
- Once the host has received all the required data it indicates that no more data is needed by explicitly de-asserting the ACK signal (this is called a NACK signal) just before sending a STOP or RESTART signal.
+ Once the host has received all the required data it indicates that no more data is needed by explicitly de-asserting the ACK signal (this is called a NACK signal) just before sending a STOP or RESTART signal.
1. A STOP signal or a RESTART signal.
This protocol is generally quite flexible with respect to timing constraints, and slow enough to be managed by a software microcontroller, however such an implementation requires frequent activity on the part of the microcontroller.
@@ -71,7 +71,7 @@
(It remains the obligation of system designers to ensure that devices which cannot support 10-bit encoding remain in a 7-bit address space.)
This IP also supports clock-stretching, should that be required by target devices.
-# Theory of Operations
+# Theory of Operations
## Block Diagram
@@ -81,7 +81,7 @@
{{< hwcfg "hw/ip/i2c/data/i2c.hjson" >}}
-## Design Details
+## Design Details
### Virtual Open Drain
@@ -107,7 +107,7 @@
When {{< regref OVRD.SCLVAL >}} and {{< regref OVRD.SDAVAL >}} are set high, the virtual open drain configuration will leave the output resistively pulled high, and controllable by remote targets.
In this state, with SCL or SDA asserted high, the register fields {{< regref VAL.SCL_RX >}} and {{< regref VAL.SDA_RX >}} can be used to receive inputs (including remote acknowledgments) from target devices.
-### Byte-Formatted Programming Mode
+### Byte-Formatted Programming Mode
The state machine-controlled mode allows for higher-speed operation with less frequent software interaction.
In this mode, the I2C pins are controlled by the I2C state machine, which in turn is controlled by a sequence of formatting indicators.
@@ -140,7 +140,7 @@
- NAKOK (corresponds to {{< regref FDATA.NAKOK >}}, Not compatible with READ):
Typically every byte transmitted must also receive an ACK signal, and the IP will raise an exception if no ACK is received.
However, there are some I2C commands which do not require an ACK.
-In those cases this flag should be asserted with FBYTE indicating no ACK is expected and no interrupt should be raised if the ACK is not received.
+In those cases this flag should be asserted with FBYTE indicating no ACK is expected and no interrupt should be raised if the ACK is not received.
### Timing Control Registers
@@ -149,9 +149,9 @@
Furthermore, depending on the actual capacitance of the bus, even a bus with all Fast-mode Plus capable targets may have to operate at slower speeds than 1Mbaud.
For example, the host may need to run at lower frequencies, as discussed in Section 5.2 of the specification, but the computation of the nominal frequency will depend on timing specifications in Table 10, in this case particularly, the limits on t<sub>LOW</sub>, t<sub>HIGH</sub>, t<sub>r</sub>, and t<sub>f</sub>.
Assuming no clock stretching, for a given set of these four parameters the baud rate is then given to be:
-$$ 1/f\_{SCL}=t\_{LOW}+t\_{HIGH}+t\_{r}+t\_{f}. $$
+$$ 1/f\_{SCL}=t\_{LOW}+t\_{HIGH}+t\_{r}+t\_{f}. $$
-Thus in order to ensure compliance with the spec in any particular configuration, software will program the I2C host IP with explicit values for each of the following timing parameters, as defined in Figure 38 of the specification.
+Thus in order to ensure compliance with the spec in any particular configuration, software will program the I2C host IP with explicit values for each of the following timing parameters, as defined in Figure 38 of the specification.
- t<sub>LOW</sub>: set in register {{< regref TIMING0.TLOW >}}.
- t<sub>HIGH</sub>: set in register {{< regref TIMING0.THIGH >}}.
- t<sub>r</sub>: set in register {{< regref TIMING1.T_R >}}.
@@ -160,11 +160,11 @@
- t<sub>f</sub>: set in register {{< regref TIMING1.T_F >}}.
(Note: The fall time cannot be explicitly controlled by internal hardware, and is a function of the pin driver.
Thus this parameter is also budgetary.
-Given that the actual fall time cannot be controlled to stay above the minimum values set in Table 10 of the specification, and so this in this regard this module currently is not strictly compliant to the I2C spec.)
+Given that the actual fall time cannot be controlled to stay above the minimum values set in Table 10 of the specification, and so this in this regard this module currently is not strictly compliant to the I2C spec.)
- t<sub>SU,STA</sub>: set in register {{< regref TIMING2.TSU_STA >}}
- t<sub>HD,STA</sub>: set in register {{< regref TIMING2.THD_STA >}}
- t<sub>SU,DAT</sub>: set in register {{< regref TIMING3.TSU_DAT >}}.
-Taken to be synonymous with T<sub>SU,ACK</sub>
+Taken to be synonymous with T<sub>SU,ACK</sub>
- t<sub>HD,DAT</sub>: set in register {{< regref TIMING3.THD_DAT >}}.
Taken to be synonymous with T<sub>HD,ACK</sub>.
Moreover, since the pin driver fall time is likely to be less then one clock cycle, this parameter is also taken to be synonymous with the parameters T<sub>VD,DAT</sub> and T<sub>VD,ACK</sub>
@@ -181,7 +181,7 @@
### Timeout Control
A malfunctioning (or otherwise very slow) target device can hold SCL low indefinitely, stalling the bus.
For this reason {{< regref TIMEOUT_CTRL >}} provides a clock-stretching timeout mechanism to notify firmware of this sort of condition.
-If {{< regref TIMEOUT_CTRL.EN >}} is asserted, an interrupt will be asserted when the IP detects that another device (a target or, in possible future revisions, an alternate master) has been holding SCL low for more than {{< regref TIMEOUT_CTRL.VAL >}} clock ticks.
+If {{< regref TIMEOUT_CTRL.EN >}} is asserted, an interrupt will be asserted when the IP detects that another device (a target or, in possible future revisions, an alternate host) has been holding SCL low for more than {{< regref TIMEOUT_CTRL.VAL >}} clock ticks.
This feature is added as a utility, though it is not required by the I2C specification.
@@ -289,7 +289,7 @@
- The expected signal rise time, t<sub>r</sub>, in ns.
- This is not a firmware-controlled parameter.
Rather, it is a function of the capacitance and physical design of the bus.
-The specification provides detailed guidelines on how to manage capacitance in an I2C system:
+The specification provides detailed guidelines on how to manage capacitance in an I2C system:
- Section 5.2 of the I2C specification indicates that Fast-mode plus devices may operate at reduced clock speeds if the bus capacitance drives signal rise times (t<sub>r</sub>) outside the nominal 120ns limit.
Excess capacitance can also be compensated for by reducing the size of the bus pullup resistor, so long as the total open-drain current does not exceed 20mA for fast-mode plus devices (as described in section 7.1 of the I2C specificaion).
However the specification places a hard limit on rise times capping them at 1000ns.
@@ -315,7 +315,7 @@
$$ \textrm{TSU_DAT_MIN}= \lceil{t\_{HD,DAT,min}/t\_{clk}}\rceil $$
$$ \textrm{T_BUF_MIN}= \lceil{t\_{BUF,min}/t\_{clk}}\rceil $$
$$ \textrm{T_STO_MIN}= \lceil{t\_{STO,min}/t\_{clk}}\rceil $$
-
+
1. Input the integer timing parameters, THD_STA_MIN, TSU_STA_MIN, THD_DAT_MIN, TSU_DAT_MIN, T_BUF_MIN and T_STO_MIN into their corresponding registers (`TIMING2.THD_STA`, `TIMING2.TSU_STA`, `TIMING3.THD_DAT`, `TIMING3.TSU_DAT`, `TIMING4.T_BUF`, `TIMING4.T_STO`)
- This step allows the firmware to manage SDA signal delays to ensure that the SDA outputs are compliant with the specification.
- The registers `TIMING0.THIGH` and `TIMING0.TLOW` will be taken care of in a later step.
@@ -350,7 +350,7 @@
|-----------------|------------------|------------|----------------|-----------------------------------------------|
| TIMING0.THIGH | 260 | 120 | 360 | Chosen to satisfy SCL Period Minimum |
| TIMING0.TLOW | 500 | 167 | 501 | Spec. t<sub>LOW</sub> Minimum |
-| TIMING1.T_F | 20ns * (VDD/5.5V)| 7 | 21 | Signal slew-rate should be controlled |
+| TIMING1.T_F | 20ns * (VDD/5.5V)| 7 | 21 | Signal slew-rate should be controlled |
| TIMING1.T_R | 0 | 40 | 120 | Based on pull-up resistance, line capacitance |
| SCL Period | 1000 | N/A | 1002 | Constraint on THIGH+TLOW+T_R+T_F |
| TIMING2.THD_STA | 260 | 87 | 261 | Spec. Minimum |
@@ -362,13 +362,13 @@
This next example shows how the first SCL timing registers: `TIMING0` and `TIMING1` are altered in a high-capacitance Fast-mode Plus bus, where the physical value of t<sub>r</sub> driven to an atypical value of 400ns.
As in the previous example the integer register values are determined based on a system clock period, t<sub>clk</sub>, of 3ns.
-All other parameters in registers `TIMING2`, `TIMING3`, `TIMING4` are unchanged from the previous example.
+All other parameters in registers `TIMING2`, `TIMING3`, `TIMING4` are unchanged from the previous example.
| Parameter | Spec. Min. (ns) | Reg. Val. | Phys. Val (ns) | Comment |
|-----------------|------------------|------------|----------------|-----------------------------------------------|
| TIMING0.THIGH | 260 | 87 | 261 | Spec. t<sub>HIGH</sub> Minimum |
| TIMING0.TLOW | 500 | 167 | 501 | Spec. t<sub>LOW</sub> Minimum |
-| TIMING1.T_F | 20ns * (VDD/5.5V)| 7 | 21 | Signal slew-rate should be controlled |
+| TIMING1.T_F | 20ns * (VDD/5.5V)| 7 | 21 | Signal slew-rate should be controlled |
| TIMING1.T_R | 0 | 134 | 402 | Atypicallly high line capacitance |
| SCL Period | 1000 | N/A | 395 | Forced longer than minimum by long T_R |
@@ -376,6 +376,6 @@
{{< dif_listing "sw/device/lib/dif/dif_i2c.h" >}}
-## Register Table
+## Register Table
{{<registers "hw/ip/i2c/data/i2c.hjson" >}}
diff --git a/hw/ip/i2c/doc/dv_plan/index.md b/hw/ip/i2c/doc/dv_plan/index.md
index aee5caa..8a0b17f 100644
--- a/hw/ip/i2c/doc/dv_plan/index.md
+++ b/hw/ip/i2c/doc/dv_plan/index.md
@@ -54,7 +54,7 @@
TL host interface into I2C device.
### I2C agent
-I2C agent is configured to work device mode and implemented as [reactive slave](https://www.verilab.com/files/mastering_reactive_slaves.pdf)
+I2C agent is configured to work device mode and implemented as [reactive agent](https://www.verilab.com/files/mastering_reactive_slaves.pdf)
### UVM RAL Model
The I2C RAL model is created with the [`ralgen`]({{< relref "hw/dv/tools/ralgen/README.md" >}}) FuseSoC generator script automatically when the simulation is at the build stage.
diff --git a/hw/ip/pinmux/rtl/pinmux.sv b/hw/ip/pinmux/rtl/pinmux.sv
index 1786153..92da2e8 100644
--- a/hw/ip/pinmux/rtl/pinmux.sv
+++ b/hw/ip/pinmux/rtl/pinmux.sv
@@ -308,7 +308,7 @@
`ASSERT_KNOWN(DioOeKnownO_A, dio_oe_o)
`ASSERT_KNOWN(LcPinmuxStrapKnownO_A, lc_pinmux_strap_o)
- // TODO: need to check why some outputs are not valid (e.g. SPI device MISO)
+ // TODO: need to check why some outputs are not valid (e.g. SPI device SDO)
// for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_known_if
// `ASSERT_KNOWN_IF(MioOutKnownO_A, mio_out_o[k], mio_oe_o[k])
// end
diff --git a/hw/ip/rv_dm/rtl/rv_dm.sv b/hw/ip/rv_dm/rtl/rv_dm.sv
index 5214e88..5ab8858 100644
--- a/hw/ip/rv_dm/rtl/rv_dm.sv
+++ b/hw/ip/rv_dm/rtl/rv_dm.sv
@@ -155,29 +155,29 @@
.sberror_i ( sberror )
);
- logic master_req;
- logic [BusWidth-1:0] master_add;
- logic master_we;
- logic [BusWidth-1:0] master_wdata;
- logic [BusWidth/8-1:0] master_be;
- logic master_gnt;
- logic master_r_valid;
- logic [BusWidth-1:0] master_r_rdata;
- logic master_r_err;
+ logic host_req;
+ logic [BusWidth-1:0] host_add;
+ logic host_we;
+ logic [BusWidth-1:0] host_wdata;
+ logic [BusWidth/8-1:0] host_be;
+ logic host_gnt;
+ logic host_r_valid;
+ logic [BusWidth-1:0] host_r_rdata;
+ logic host_r_err;
dm_sba #(
.BusWidth(BusWidth)
) i_dm_sba (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
- .master_req_o ( master_req ),
- .master_add_o ( master_add ),
- .master_we_o ( master_we ),
- .master_wdata_o ( master_wdata ),
- .master_be_o ( master_be ),
- .master_gnt_i ( master_gnt ),
- .master_r_valid_i ( master_r_valid ),
- .master_r_rdata_i ( master_r_rdata ),
+ .master_req_o ( host_req ),
+ .master_add_o ( host_add ),
+ .master_we_o ( host_we ),
+ .master_wdata_o ( host_wdata ),
+ .master_be_o ( host_be ),
+ .master_gnt_i ( host_gnt ),
+ .master_r_valid_i ( host_r_valid ),
+ .master_r_rdata_i ( host_r_rdata ),
.dmactive_i ( dmactive_o ),
.sbaddress_i ( sbaddress_csrs_sba ),
.sbaddress_o ( sbaddress_sba_csrs ),
@@ -201,21 +201,21 @@
) tl_adapter_host_sba (
.clk_i,
.rst_ni,
- .req_i (master_req),
- .gnt_o (master_gnt),
- .addr_i (master_add),
- .we_i (master_we),
- .wdata_i (master_wdata),
- .be_i (master_be),
- .valid_o (master_r_valid),
- .rdata_o (master_r_rdata),
- .err_o (master_r_err),
+ .req_i (host_req),
+ .gnt_o (host_gnt),
+ .addr_i (host_add),
+ .we_i (host_we),
+ .wdata_i (host_wdata),
+ .be_i (host_be),
+ .valid_o (host_r_valid),
+ .rdata_o (host_r_rdata),
+ .err_o (host_r_err),
.tl_o (tl_h_o),
.tl_i (tl_h_i)
);
// DBG doesn't handle error responses so raise assertion if we see one
- `ASSERT(dbgNoErrorResponse, master_r_valid |-> !master_r_err)
+ `ASSERT(dbgNoErrorResponse, host_r_valid |-> !host_r_err)
localparam int unsigned AddressWidthWords = BusWidth - $clog2(BusWidth/8);
diff --git a/hw/ip/spi_device/data/spi_device.hjson b/hw/ip/spi_device/data/spi_device.hjson
index deedbc9..2aa675f 100644
--- a/hw/ip/spi_device/data/spi_device.hjson
+++ b/hw/ip/spi_device/data/spi_device.hjson
@@ -7,16 +7,16 @@
available_input_list: [
{ name: "sck", desc: "SPI Clock" },
{ name: "csb", desc: "Chip Enable#" },
- { name: "mosi", desc: "SPI Input" },
+ { name: "sdi", desc: "SPI Input" },
],
available_output_list: [
- { name: "miso", desc: "SPI Output" },
+ { name: "sdo", desc: "SPI Output" },
],
interrupt_list: [
{ name: "rxf", desc: "RX SRAM FIFO Full" },
{ name: "rxlvl", desc: "RX SRAM FIFO is above the level" },
{ name: "txlvl", desc: "TX SRAM FIFO is under the level" },
- { name: "rxerr", desc: "MOSI in FwMode has error" },
+ { name: "rxerr", desc: "SDI in FwMode has error" },
{ name: "rxoverflow", desc: "RX Async FIFO overflow" },
{ name: "txunderflow", desc: "TX Async FIFO underflow" },
],
@@ -46,7 +46,7 @@
FW operation mode.
HW just dumps incoming data to SRAM and reads from SRAM and
- sends to MISO. This mode doesn't support Dual or Quad mode
+ sends to SDO. This mode doesn't support Dual or Quad mode
'''
},
]
@@ -96,12 +96,12 @@
},
{ bits: "2",
name: "tx_order",
- desc: "TX bit order on MISO. 0 for MSB to LSB, 1 for LSB to MSB",
+ desc: "TX bit order on SDO. 0 for MSB to LSB, 1 for LSB to MSB",
resval: "0",
},
{ bits: "3",
name: "rx_order",
- desc: "RX bit order on MOSI. Module stores bitstream from MSB to LSB if value is 0.",
+ desc: "RX bit order on SDI. Module stores bitstream from MSB to LSB if value is 0.",
resval: "0",
},
{ bits: "15:8",
diff --git a/hw/ip/spi_device/doc/_index.md b/hw/ip/spi_device/doc/_index.md
index 530c9cc..6faef31 100644
--- a/hw/ip/spi_device/doc/_index.md
+++ b/hw/ip/spi_device/doc/_index.md
@@ -24,9 +24,9 @@
The SPI device module is a serial-to-parallel receive (RX) and
parallel-to-serial transmit (TX) full duplex design (single line mode) used to communicate
with an outside host. This first version of the module supports operations
-controlled by firmware to dump incoming single-line RX data (MOSI) to an
+controlled by firmware to dump incoming single-line RX data (SDI) to an
internal RX buffer, and send data from a transmit buffer to single-line TX
-output (MISO). The clock for the peripheral data transfer uses the SPI
+output (SDO). The clock for the peripheral data transfer uses the SPI
peripheral pin SCK. In this design the SCK is directly used to drive the
interface logic as its primary clock, which has performance benefits, but incurs
design complications described later.
@@ -42,7 +42,7 @@
The block diagram above shows how the SPI Device IP converts incoming
-bit-serialized MOSI data into a valid byte, where the data bit is valid when the
+bit-serialized SDI data into a valid byte, where the data bit is valid when the
chip select signal (CSB) is 0 (active low) and SCK is at positive or negative
edge (configurable, henceforth called the "active edge"). The bit order within
the byte is determined by {{< regref "CFG.rx_order" >}} configuration register field. After a
@@ -52,14 +52,14 @@
an error condition and the interface module discards the byte.
The interface module also serializes data from the small transmit FIFO
-("TXFIFO") and shifts it out on the MISO pin when CSB is 0 and SCK is at the
+("TXFIFO") and shifts it out on the SDO pin when CSB is 0 and SCK is at the
active edge. The bit order within the byte can be configured with configuration
register field {{< regref "CFG.tx_order" >}}. It is expected that software has prepared TX data
based on the description in the "Defining
Firmware Operation Mode" section below. Since SCK is not under the control of
software or the device (it is driven by the external SPI host), it is possible
that there is no data ready in the TXFIFO when chip select becomes active and
-the interface needs to send data on the MISO pin. Either software has not
+the interface needs to send data on the SDO pin. Either software has not
prepared TX data or software does not care about the contents of the TX data -
then the hardware will send whatever lingering data is in the empty TXFIFO. If
this is a functional issue, then software should at least soft-reset the contents
@@ -74,12 +74,12 @@
## General Data Transfer on Pins
Data transfers with the SPI device module involve four peripheral SPI pins: SCK,
-CSB, MOSI, MISO. SCK is the SPI clock driven by an external SPI host. CSB (chip
+CSB, SDI, SDO. SCK is the SPI clock driven by an external SPI host. CSB (chip
select bar) is an active low enable signal that frames a transfer, driven by the
external host. Transfers with active SCK edges but inactive (high) CSB are
-ignored. Data is driven into the SPI device on the MOSI pin ("Master Out Slave
+ignored. Data is driven into the SPI device on the SDI pin ("Serial Data
In", though we're otherwise using host/device terminology) and driven out on
-MISO. Any transfer length is legal, though higher level protocols typically
+SDO. Any transfer length is legal, though higher level protocols typically
assume word width boundaries. See details on protocols and transfers that
follow. The diagram below shows a typical transfer, here for 8 bytes (64 cycles,
showing the beginning and end of the transfer). Configurability for active
@@ -89,10 +89,10 @@
{ signal: [
{ name: 'CSB', wave: '10.........|....1.'},
{ name: 'SCK', wave: '0.p........|....l.'},
- { name: 'MOSI', wave: 'z.=..=.=.=.=.=.=.=.=.=|=.=.=.=.z....',
+ { name: 'SDI', wave: 'z.=..=.=.=.=.=.=.=.=.=|=.=.=.=.z....',
data:['R07','R06','R05','R04','R03','R02','R01','R00','R17',
'','R73','R72','R71','R70'], period:0.5, },
- { name: 'MISO', wave: 'z.=..=.=.=.=.=.=.=.=.=|=.=.=.=.z....',
+ { name: 'SDO', wave: 'z.=..=.=.=.=.=.=.=.=.=|=.=.=.=.z....',
data:['T07','T06','T05','T04','T03','T02','T01','T00','T17',
'','T73','T72','T71','T70'], period:0.5}],
head:{
@@ -118,7 +118,7 @@
of TX data is sent out of the peripheral. If transfers only require
unidirectional movement of data, the other direction can be ignored but will
still be active. For instance, if only receive data is needed in the transfer,
-the device will still be transmitting data out on the TX ("MISO") pin.
+the device will still be transmitting data out on the TX ("SDO") pin.
## SPI Generic Protocol
@@ -169,8 +169,8 @@
### Firmware Operation Mode
Taking this example as a guide, we can see the general method of the SPI
-Firmware Operation Mode. On every active SCK clock edge, data is received from the MOSI
-pin into the SPI device, and data is transmitted on the MISO pin. Received data
+Firmware Operation Mode. On every active SCK clock edge, data is received from the SDI
+pin into the SPI device, and data is transmitted on the SDO pin. Received data
is gathered into bytes and written into the RX circular buffer in the SPI Device
SRAM as it is accumulated. Whatever data exists in the TX circular buffer is
serialized and transmitted. Transfers are framed using the active low chip
@@ -197,7 +197,7 @@
of the two-clock-edges normally required for asynchronous handshaking protocols.
The RXFIFO and TXFIFO exist to facilitate this situation.
-In the receive direction, data gathered from the MOSI pin is written into the
+In the receive direction, data gathered from the SDI pin is written into the
RXFIFO (see details below) at appropriate size boundaries. This data is
handshake-received on the core clock side, gathered into byte or word quantity,
and written into the RX circular buffer of the dual-port SRAM. On each write,
@@ -235,7 +235,7 @@
SRAM and prefilling the TXFIFO until it is full or until all valid TXF data has
been read. This prepares the TXFIFO with the desired data for when the next SCK
data arrives. As the SCK domain logic pulls data out of the TXFIFO to transmit
-on the MISO pin, that TXFIFO read is detected (after synchronization to the core
+on the SDO pin, that TXFIFO read is detected (after synchronization to the core
clock domain) and potentially another word of data is read from the SRAM and
written into the TXFIFO. Each time the SRAM is read the hardware increments the
TXF read pointer making the space available to software. Like above, though
@@ -266,15 +266,15 @@
It is important that the data path inside the block should meet the timing that
is a half cycle of SCK. As SCK clock is shut off right after the last bit of the
-last byte is received, the hardware module cannot register the MOSI signal. The
-module registers bits [7:1] and combines them with the MOSI signal directly to
+last byte is received, the hardware module cannot register the SDI signal. The
+module registers bits [7:1] and combines them with the SDI signal directly to
form the input to RXFIFO. This is detailed in the waveform below.
{{< wavejson >}}
{ signal: [
{ name: 'CSB', wave: '10.||...|..1'},
{ name: 'SCK', wave: '0.p||...|..l', node:'......b' },
- { name: 'MOSI', wave: '0.=..=|=|=.=.=.=|=.=.z..', data:['7','6','5','1','0','7','6','1','0'], period:0.5, },
+ { name: 'SDI', wave: '0.=..=|=|=.=.=.=|=.=.z..', data:['7','6','5','1','0','7','6','1','0'], period:0.5, },
{ name: 'BitCount', wave: '=...=.=|=|=.=.=.=|=.=...', data:['7','6','5','1','0','7','6','1','0','7'], period:0.5},
{ name: 'RX_WEN', wave: '0....|....1.0.|...1.0...' , period:0.5},
{ name: 'RXFIFO_D', wave:'x.=.=================.x.', node: '...........a',period:0.5},
@@ -291,19 +291,19 @@
for the next round. RXFIFO input data changes on the half clock cycle. RXFIFO
latches WEN at the positive edge of SCK. When BitCount is 0h, bit 0 of FIFO data
shows the bit 1 value for the first half clock cycle then shows correct value
-once the incoming MOSI value is updated.
+once the incoming SDI value is updated.
TXFIFO is similar. TX_REN is asserted when Tx BitCount reaches 1, and the
current entry of TXFIFO is popped at the negative edge of SCK. It results in a
-change of MISO value at the negative edge of SCK. MISO_OE is controlled by the
-CSB signal. If CSB goes to high, MISO is returned to High-Z state.
+change of SDO value at the negative edge of SCK. SDO_OE is controlled by the
+CSB signal. If CSB goes to high, SDO is returned to High-Z state.
{{< wavejson >}}
{ signal: [
{ name: 'CSB', wave:'10.||...|..1'},
{ name: 'SCK', wave:'0...p.|.|...|l' , node:'.............a', period:0.5},
- { name: 'MISO', wave:'x.=..=|=|=.=.=.=|=.=.x..', data:['7','6','5','1','0','7','6','1','0'], period:0.5, },
- { name: 'MISO_OE', wave:'0.1...................0.', period:0.5},
+ { name: 'SDO', wave:'x.=..=|=|=.=.=.=|=.=.x..', data:['7','6','5','1','0','7','6','1','0'], period:0.5, },
+ { name: 'SDO_OE', wave:'0.1...................0.', period:0.5},
{ name: 'BitCount', wave:'=....=.=|=|=.=.=.=|=.=..', data:['7','6','5','1','0','7','6','1','0','7'], period:0.5},
{ name: 'TX_REN', wave:'0.....|..1.0...|.1.0....' , node:'..........c',period:0.5},
{ name: 'TX_DATA_i',wave:'=.....|....=.......=....',data:['D0','Dn','Dn+1'], node:'...........b', period:0.5},
diff --git a/hw/ip/spi_device/dv/env/seq_lib/spi_device_base_vseq.sv b/hw/ip/spi_device/dv/env/seq_lib/spi_device_base_vseq.sv
index 3689c36..987f437 100644
--- a/hw/ip/spi_device/dv/env/seq_lib/spi_device_base_vseq.sv
+++ b/hw/ip/spi_device/dv/env/seq_lib/spi_device_base_vseq.sv
@@ -105,8 +105,8 @@
endtask
// NOTE on terminology
- // from spi_device IP perspective, tx is data sent out over miso (device traffic from the IP),
- // rx is data received over mosi (host traffic from SPI agent)
+ // from spi_device IP perspective, tx is data sent out over sdo (device traffic from the IP),
+ // rx is data received over sdi (host traffic from SPI agent)
// TODO: use spi_device_pkg spi_mode enum instead
virtual task spi_device_init();
diff --git a/hw/ip/spi_device/dv/env/seq_lib/spi_device_fifo_underflow_overflow_vseq.sv b/hw/ip/spi_device/dv/env/seq_lib/spi_device_fifo_underflow_overflow_vseq.sv
index 369a90a..2c99f9d 100644
--- a/hw/ip/spi_device/dv/env/seq_lib/spi_device_fifo_underflow_overflow_vseq.sv
+++ b/hw/ip/spi_device/dv/env/seq_lib/spi_device_fifo_underflow_overflow_vseq.sv
@@ -10,7 +10,7 @@
virtual task body();
allow_underflow_overflow = 1;
- // when underflow, miso may be unknown, disable checking it
+ // when underflow, sdo may be unknown, disable checking it
cfg.m_spi_agent_cfg.en_monitor_checks = 0;
super.body();
cfg.m_spi_agent_cfg.en_monitor_checks = 1;
diff --git a/hw/ip/spi_device/dv/tb/tb.sv b/hw/ip/spi_device/dv/tb/tb.sv
index 49a26f7..8d0cbea 100644
--- a/hw/ip/spi_device/dv/tb/tb.sv
+++ b/hw/ip/spi_device/dv/tb/tb.sv
@@ -20,9 +20,9 @@
wire sck;
wire csb;
- wire miso_o;
- wire miso_en;
- wire mosi_i;
+ wire sdo_o;
+ wire sdo_en;
+ wire sdi_i;
wire intr_rxf;
wire intr_rxlvl;
@@ -48,9 +48,9 @@
.cio_sck_i (sck ),
.cio_csb_i (csb ),
- .cio_miso_o (miso_o ),
- .cio_miso_en_o (miso_en ),
- .cio_mosi_i (mosi_i ),
+ .cio_sdo_o (sdo_o ),
+ .cio_sdo_en_o (sdo_en ),
+ .cio_sdi_i (sdi_i ),
.intr_rxf_o (intr_rxf ),
.intr_rxlvl_o (intr_rxlvl),
@@ -63,8 +63,8 @@
assign sck = spi_if.sck;
assign csb = spi_if.csb;
- assign mosi_i = spi_if.mosi;
- assign spi_if.miso = miso_en ? miso_o : 1'bz;
+ assign sdi_i = spi_if.sdi;
+ assign spi_if.sdo = sdo_en ? sdo_o : 1'bz;
assign interrupts[RxFifoFull] = intr_rxf;
assign interrupts[RxFifoGeLevel] = intr_rxlvl;
diff --git a/hw/ip/spi_device/lint/spi_device.waiver b/hw/ip/spi_device/lint/spi_device.waiver
index 8176322..717e8d4 100644
--- a/hw/ip/spi_device/lint/spi_device.waiver
+++ b/hw/ip/spi_device/lint/spi_device.waiver
@@ -44,7 +44,7 @@
waive -rules CONST_OUTPUT -location {spi_fwm_*xf_ctrl.sv} -regexp {Output 'depth.*} \
-comment "Based on the SRAM size 2kB, it cannot hit the case"
-waive -rules CONST_FF -location {spi_fwmode.sv} -regexp {Flip-flop 'miso_shift\[0\]' is driven} \
+waive -rules CONST_FF -location {spi_fwmode.sv} -regexp {Flip-flop 'sdo_shift\[0\]' is driven} \
-comment "Intended behavior"
waive -rules CONST_FF -location {spi_device.sv} -regexp {fwm_rerr_q} \
-comment "Will implement the interrupt later. Waive for now"
diff --git a/hw/ip/spi_device/rtl/spi_device.sv b/hw/ip/spi_device/rtl/spi_device.sv
index 93c7522..0ecc49b 100644
--- a/hw/ip/spi_device/rtl/spi_device.sv
+++ b/hw/ip/spi_device/rtl/spi_device.sv
@@ -22,9 +22,9 @@
// SPI Interface
input cio_sck_i,
input cio_csb_i,
- output logic cio_miso_o,
- output logic cio_miso_en_o,
- input cio_mosi_i,
+ output logic cio_sdo_o,
+ output logic cio_sdo_en_o,
+ input cio_sdi_i,
// Interrupts
output logic intr_rxf_o, // RX FIFO Full
@@ -46,8 +46,8 @@
localparam int PtrW = SramAw + 1 + SDW;
localparam int AsFifoDepthW = $clog2(FifoDepth+1);
- logic clk_spi_in; // clock for latch MOSI
- logic clk_spi_out; // clock for driving MISO
+ logic clk_spi_in; // clock for latch SDI
+ logic clk_spi_out; // clock for driving SDO
spi_device_reg2hw_t reg2hw;
spi_device_hw2reg_t hw2reg;
@@ -310,7 +310,7 @@
//////////////////////////////
// clk_spi cannot use glitch-free clock mux as clock switching in glitch-free
// requires two clocks to propagate clock selection and enable but SPI clock
- // doesn't exist until it transmits data through MOSI
+ // doesn't exist until it transmits data through SDI
logic sck_n;
logic rst_spi_n;
@@ -353,9 +353,9 @@
// SPI signal
.csb_i (cio_csb_i),
- .mosi (cio_mosi_i),
- .miso (cio_miso_o),
- .miso_oe (cio_miso_en_o)
+ .sdi (cio_sdi_i),
+ .sdo (cio_sdo_o),
+ .sdo_oe (cio_sdo_en_o)
);
// FIFO: Connecting FwMode to SRAM CTRLs
@@ -571,7 +571,7 @@
// make sure scanmode_i is never X (including during reset)
`ASSERT_KNOWN(scanmodeKnown, scanmode_i, clk_i, 0)
- `ASSERT_KNOWN(CioMisoEnOKnown, cio_miso_en_o)
+ `ASSERT_KNOWN(CioSdoEnOKnown, cio_sdo_en_o)
`ASSERT_KNOWN(IntrRxfOKnown, intr_rxf_o )
`ASSERT_KNOWN(IntrRxlvlOKnown, intr_rxlvl_o )
diff --git a/hw/ip/spi_device/rtl/spi_fwmode.sv b/hw/ip/spi_device/rtl/spi_fwmode.sv
index 666078e..f28c22c 100644
--- a/hw/ip/spi_device/rtl/spi_fwmode.sv
+++ b/hw/ip/spi_device/rtl/spi_fwmode.sv
@@ -6,11 +6,11 @@
//
module spi_fwmode (
- // MOSI
+ // SDI
input clk_in_i,
input rst_in_ni,
- // MISO
+ // SDO
input clk_out_i,
input rst_out_ni,
@@ -35,9 +35,9 @@
// SPI Interface: clock is given (ckl_in_i, clk_out_i)
input csb_i,
- input mosi,
- output logic miso,
- output logic miso_oe
+ input sdi,
+ output logic sdo,
+ output logic sdo_oe
);
import spi_device_pkg::*;
@@ -58,9 +58,9 @@
// Serial to Parallel
always_comb begin
if (cfg_rxorder_i) begin
- rx_data_d = {mosi, rx_data_q[BITS-1:1]};
+ rx_data_d = {sdi, rx_data_q[BITS-1:1]};
end else begin
- rx_data_d = {rx_data_q[BITS-2:0], mosi};
+ rx_data_d = {rx_data_q[BITS-2:0], sdi};
end
end
@@ -69,7 +69,7 @@
end
// As SCK shut off right after bytes are transferred,
- // HW should give current MOSI and latched version of rx_data
+ // HW should give current SDI and latched version of rx_data
// if not, FIFO request should be generated next cycle but it cannot be (as no clock exist)
// It means RX_FIFO should latch the write request at negedge of clk_in_i
assign rx_data_o = rx_data_d;
@@ -92,7 +92,7 @@
// TX Serialize
logic [BITWIDTH-1:0] tx_bitcount;
logic first_bit, last_bit;
- spi_byte_t miso_shift;
+ spi_byte_t sdo_shift;
assign first_bit = (tx_bitcount == BITWIDTH'(BITS-1)) ? 1'b1 : 1'b0;
assign last_bit = (tx_bitcount == '0) ? 1'b1 : 1'b0;
@@ -121,25 +121,25 @@
end
end
- assign miso = (cfg_txorder_i) ? ((~first_bit) ? miso_shift[0] : tx_data_i[0]) :
- (~first_bit) ? miso_shift[7] : tx_data_i[7] ;
- assign miso_oe = ~csb_i;
+ assign sdo = (cfg_txorder_i) ? ((~first_bit) ? sdo_shift[0] : tx_data_i[0]) :
+ (~first_bit) ? sdo_shift[7] : tx_data_i[7] ;
+ assign sdo_oe = ~csb_i;
always_ff @(posedge clk_out_i) begin
if (cfg_txorder_i) begin
if (first_bit) begin
- miso_shift <= {1'b0, tx_data_i[7:1]};
+ sdo_shift <= {1'b0, tx_data_i[7:1]};
end else begin
- miso_shift <= {1'b0, miso_shift[7:1]};
+ sdo_shift <= {1'b0, sdo_shift[7:1]};
end
end else begin
if (first_bit) begin
// Dummy byte cannot be used. empty signal could be delayed two clocks to cross
// async clock domain. It means even FW writes value to FIFO, empty signal deasserts
// after two negative edge of SCK. HW module already in the middle of sending DUMMY.
- miso_shift <= {tx_data_i[6:0], 1'b0};
+ sdo_shift <= {tx_data_i[6:0], 1'b0};
end else begin
- miso_shift <= {miso_shift[6:0], 1'b0};
+ sdo_shift <= {sdo_shift[6:0], 1'b0};
end
end
end
diff --git a/hw/ip/tlul/rtl/tlul_adapter_sram.sv b/hw/ip/tlul/rtl/tlul_adapter_sram.sv
index 9458784..35e6fe3 100644
--- a/hw/ip/tlul/rtl/tlul_adapter_sram.sv
+++ b/hw/ip/tlul/rtl/tlul_adapter_sram.sv
@@ -8,7 +8,7 @@
* Tile-Link UL adapter for SRAM-like devices
*
* - Intentionally omitted BaseAddr in case of multiple memory maps are used in a SoC,
- * it means that aliasing can happen if target slave size in TL-UL crossbar is bigger
+ * it means that aliasing can happen if target device size in TL-UL crossbar is bigger
* than SRAM size
*/
module tlul_adapter_sram #(
diff --git a/hw/ip/tlul/rtl/tlul_socket_1n.sv b/hw/ip/tlul/rtl/tlul_socket_1n.sv
index a7f7177..c9d8094 100644
--- a/hw/ip/tlul/rtl/tlul_socket_1n.sv
+++ b/hw/ip/tlul/rtl/tlul_socket_1n.sv
@@ -23,9 +23,9 @@
// DRspDepth: (one per device_count) Depth of device i response FIFO,
// default 2
//
-// Requests must stall to one slave until all responses from other slaves
+// Requests must stall to one device until all responses from other devices
// have returned. Need to keep a counter of all outstanding requests and
-// wait until that counter is zero before switching slaves.
+// wait until that counter is zero before switching devices.
//
// This module will return a request error if the input value of 'dev_select'
// is not within the range 0..N-1. Thus the instantiator of the socket
@@ -142,7 +142,7 @@
tlul_pkg::tl_d2h_t tl_t_p ;
- // for the returning reqready, only look at the slave we're addressing
+ // for the returning reqready, only look at the device we're addressing
logic hfifo_reqready;
always_comb begin
hfifo_reqready = tl_u_i[N].a_ready; // default to error
diff --git a/hw/lint/doc/README.md b/hw/lint/doc/README.md
index e62401f..61a07db 100644
--- a/hw/lint/doc/README.md
+++ b/hw/lint/doc/README.md
@@ -100,7 +100,7 @@
where the `top_earlgrey_lint_cfgs.hjson` file contains all the lint targets to be run in that regression (currently all available comportable IPs and the top-level are run).
The `purge` option ensures that the scratch directory is fully erased before starting the build, and `mp 1` sets the number of parallel workers to one (should be set depending on your licensing situation).
-The batch regression is regularly run on the master branch at eight-hour intervals, and the results are published on a public dashboard such that everybody can inspect the current lint status of all IPs on the project website.
+The batch regression is regularly run on the `master` branch at eight-hour intervals, and the results are published on a public dashboard such that everybody can inspect the current lint status of all IPs on the project website.
The dashboard can be found by following the appropriate link on the [hardware IP overview page](https://docs.opentitan.org/hw).
# CDC Linting
diff --git a/hw/syn/tools/dc/parse-syn-report.py b/hw/syn/tools/dc/parse-syn-report.py
index 19fe593..4b53ff3 100755
--- a/hw/syn/tools/dc/parse-syn-report.py
+++ b/hw/syn/tools/dc/parse-syn-report.py
@@ -206,12 +206,13 @@
# get TNS and WNS in that group
for k, g in enumerate(groups):
if g.strip() not in results[key]:
- results[key].update(
- {g.strip(): {
- "tns": 0.0,
- "wns": 0.0,
- "period": float("nan")
- }})
+ results[key].update({
+ g.strip(): {
+ "tns": 0.0,
+ "wns": 0.0,
+ "period": float("nan")
+ }
+ })
value = float(slack[k]) if float(slack[k]) < 0.0 else 0.0
results[key][g]["wns"] = min(results[key][g]["wns"], value)
results[key][g]["tns"] += value
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 5cc4dae..c509d11 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -442,7 +442,7 @@
type: input
}
{
- name: mosi
+ name: sdi
width: 1
type: input
}
@@ -450,7 +450,7 @@
available_output_list:
[
{
- name: miso
+ name: sdo
width: 1
type: output
}
@@ -3360,7 +3360,7 @@
]
}
{
- name: spi_device_mosi
+ name: spi_device_sdi
width: 1
type: input
module_name: spi_device
@@ -3373,7 +3373,7 @@
]
}
{
- name: spi_device_miso
+ name: spi_device_sdo
width: 1
type: output
module_name: spi_device
@@ -4084,4 +4084,4 @@
}
]
}
-}
\ No newline at end of file
+}
diff --git a/hw/top_earlgrey/data/pins_artys7.xdc b/hw/top_earlgrey/data/pins_artys7.xdc
index cc6e9c3..3f2663f 100644
--- a/hw/top_earlgrey/data/pins_artys7.xdc
+++ b/hw/top_earlgrey/data/pins_artys7.xdc
@@ -101,8 +101,8 @@
## ChipKit SPI Header
## NOTE: The ChipKit SPI header ports can also be used as digital I/O and share FPGA pins with ck_io10-13. Do not use both at the same time.
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { ck_io10_ss }]; #IO_L22P_T3_A17_15 Sch=ck_io10_ss
-#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ck_io11_mosi }]; #IO_L22N_T3_A16_15 Sch=ck_io11_mosi
-#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ck_io12_miso }]; #IO_L23P_T3_FOE_B_15 Sch=ck_io12_miso
+#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ck_io11_sdi }]; #IO_L22N_T3_A16_15 Sch=ck_io11_sdi
+#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ck_io12_sdo }]; #IO_L23P_T3_FOE_B_15 Sch=ck_io12_sdo
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { ck_io13_sck }]; #IO_L14P_T2_SRCC_15 Sch=ck_io13_sck
## ChipKit Inner Digital Header
@@ -182,7 +182,7 @@
## Quad SPI Flash
## Note: the SCK clock signal can be driven using the STARTUPE2 primitive
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
-#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_SDI_14 Sch=qspi_dq[0]
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
diff --git a/hw/top_earlgrey/data/pins_nexysvideo.xdc b/hw/top_earlgrey/data/pins_nexysvideo.xdc
index 5149178..b1848dc 100644
--- a/hw/top_earlgrey/data/pins_nexysvideo.xdc
+++ b/hw/top_earlgrey/data/pins_nexysvideo.xdc
@@ -141,8 +141,8 @@
## Pmod header JC
#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { IO_SDCK }]; #IO_L18P_T2_34 Sch=jc_p[1]
#set_property -dict { PACKAGE_PIN AA6 IOSTANDARD LVCMOS33 } [get_ports { IO_SDCSB }]; #IO_L18N_T2_34 Sch=jc_n[1]
-#set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS33 } [get_ports { IO_SDMOSI }]; #IO_L22P_T3_34 Sch=jc_p[2]
-#set_property -dict { PACKAGE_PIN AB8 IOSTANDARD LVCMOS33 } [get_ports { IO_SDMISO }]; #IO_L22N_T3_34 Sch=jc_n[2]
+#set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS33 } [get_ports { IO_SDSDI }]; #IO_L22P_T3_34 Sch=jc_p[2]
+#set_property -dict { PACKAGE_PIN AB8 IOSTANDARD LVCMOS33 } [get_ports { IO_SDSDO }]; #IO_L22N_T3_34 Sch=jc_n[2]
#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { IO_OBS }]; #IO_L18P_T2_34 Sch=jc_p[1]
#set_property -dict { PACKAGE_PIN AA6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L18N_T2_34 Sch=jc_n[1]
#set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22P_T3_34 Sch=jc_p[2]
@@ -196,8 +196,8 @@
## DPTI/DSPI
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { prog_clko }]; #IO_L13P_T2_MRCC_14 Sch=prog_clko
set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS0 }]; #IO_L11P_T1_SRCC_14 Sch=prog_d0/sck
-set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS1 }]; #IO_L19P_T3_A10_D26_14 Sch=prog_d1/mosi
-set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS2 }]; #IO_L22P_T3_A05_D21_14 Sch=prog_d2/miso
+set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS1 }]; #IO_L19P_T3_A10_D26_14 Sch=prog_d1/sdi
+set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS2 }]; #IO_L22P_T3_A05_D21_14 Sch=prog_d2/sdo
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS3 }]; #IO_L18P_T2_A12_D28_14 Sch=prog_d3/ss
set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS4 }]; #IO_L24N_T3_A00_D16_14 Sch=prog_d[4]
set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 PULLTYPE PULLUP } [get_ports { IO_DPS5 }]; #IO_L24P_T3_A01_D17_14 Sch=prog_d[5]
@@ -219,7 +219,7 @@
## QSPI
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
-#set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_SDI_14 Sch=qspi_dq[0]
#set_property -dict { PACKAGE_PIN R22 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
#set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
#set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
diff --git a/hw/top_earlgrey/doc/_index.md b/hw/top_earlgrey/doc/_index.md
index a89f8ae..c76c8b9 100644
--- a/hw/top_earlgrey/doc/_index.md
+++ b/hw/top_earlgrey/doc/_index.md
@@ -104,9 +104,9 @@
| `jtag_trst_ni` | input | JTAG Test Reset |
| `dio_spi_device_sck_i` | input | SPI device clock |
| `dio_spi_device_csb_i` | input | SPI device chip select |
-| `dio_spi_device_mosi_i` | input | SPI device input data |
-| `dio_spi_device_miso_o` | output | SPI device output data |
-| `dio_spi_device_miso_en_o` | output | SPI device output enable |
+| `dio_spi_device_sdi_i` | input | SPI device input data |
+| `dio_spi_device_sdo_o` | output | SPI device output data |
+| `dio_spi_device_sdo_en_o` | output | SPI device output enable |
| `dio_uart_rx_i` | input | UART input receive data |
| `dio_uart_tx_o` | output | UART output transmit data |
| `dio_uart_tx_en_o` | output | UART output transmit output enable |
@@ -121,8 +121,8 @@
| `IO_CLK` | input | Chip level functional clock |
| `IO_RST_N` | input | Chip level reset, active low |
| `IO_DPS0` | input | Muxed functionality: JTAG `TCK` and `spi_device_sck_i` |
-| `IO_DPS1` | input | Muxed functionality: JTAG `TDI` and `spi_device_mosi_i` |
-| `IO_DPS2` | output | Muxed functionality: JTAG `TDO` and `spi_device_miso_o` |
+| `IO_DPS1` | input | Muxed functionality: JTAG `TDI` and `spi_device_sdi_i` |
+| `IO_DPS2` | output | Muxed functionality: JTAG `TDO` and `spi_device_sdo_o` |
| `IO_DPS3` | input | Muxed functionality: JTAG `TMS` and `spi_device_csb_i` |
| `IO_DPS4` | input | JTAG `TRST_N` |
| `IO_DPS5` | input | JTAG `SRST_N` |
diff --git a/hw/top_earlgrey/dv/tb/tb.sv b/hw/top_earlgrey/dv/tb/tb.sv
index dadbd43..cb70f9a 100644
--- a/hw/top_earlgrey/dv/tb/tb.sv
+++ b/hw/top_earlgrey/dv/tb/tb.sv
@@ -30,8 +30,8 @@
wire spi_device_sck;
wire spi_device_csb;
- wire spi_device_miso_o;
- wire spi_device_mosi_i;
+ wire spi_device_sdo_o;
+ wire spi_device_sdi_i;
wire srst_n;
wire jtag_spi_n;
@@ -136,14 +136,14 @@
// connect signals
assign io_dps[0] = jtag_spi_n ? jtag_tck : spi_device_sck;
- assign io_dps[1] = jtag_spi_n ? jtag_tdi : spi_device_mosi_i;
+ assign io_dps[1] = jtag_spi_n ? jtag_tdi : spi_device_sdi_i;
assign io_dps[3] = jtag_spi_n ? jtag_tms : spi_device_csb;
assign io_dps[4] = jtag_trst_n;
assign io_dps[5] = srst_n;
assign io_dps[6] = jtag_spi_n;
assign io_dps[7] = bootstrap;
- assign spi_device_miso_o = jtag_spi_n ? 1'b0 : io_dps[2];
- assign jtag_tdo = jtag_spi_n ? io_dps[2] : 1'b0;
+ assign spi_device_sdo_o = jtag_spi_n ? 1'b0 : io_dps[2];
+ assign jtag_tdo = jtag_spi_n ? io_dps[2] : 1'b0;
assign jtag_tck = jtag_if.tck;
assign jtag_tms = jtag_if.tms;
@@ -153,8 +153,8 @@
assign spi_device_sck = spi_if.sck;
assign spi_device_csb = spi_if.csb;
- assign spi_device_mosi_i = spi_if.mosi;
- assign spi_if.miso = spi_device_miso_o;
+ assign spi_device_sdi_i = spi_if.sdi;
+ assign spi_if.sdo = spi_device_sdo_o;
assign uart_rx = uart_if.uart_rx;
assign uart_if.uart_tx = uart_tx;
diff --git a/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson b/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
index a848785..2e652aa 100644
--- a/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
+++ b/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
@@ -2,7 +2,7 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
- // This is the master cfg hjson for DV simulations. It imports ALL individual DV sim
+ // This is a cfg hjson group for DV simulations. It includes ALL individual DV simulation
// cfgs of the IPs and the full chip used in top_earlgrey. This enables the common
// regression sets to be run in one shot.
name: top_earlgrey_batch_sim
diff --git a/hw/top_earlgrey/fpv/top_earlgrey_fpv_cfgs.hjson b/hw/top_earlgrey/fpv/top_earlgrey_fpv_cfgs.hjson
index 57521e0..c0f114c 100644
--- a/hw/top_earlgrey/fpv/top_earlgrey_fpv_cfgs.hjson
+++ b/hw/top_earlgrey/fpv/top_earlgrey_fpv_cfgs.hjson
@@ -3,7 +3,7 @@
// SPDX-License-Identifier: Apache-2.0
{
- // This is the master cfg hjson for FPV. It imports ALL individual FPV
+ // This is the primary cfg hjson for FPV. It imports ALL individual FPV
// cfgs of the IPs and the full chip used in top_earlgrey. This enables to run
// them all as a regression in one shot.
name: top_earlgrey_batch_fpv
diff --git a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson
index 974bb04..4aee36a 100644
--- a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson
+++ b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson
@@ -3,7 +3,7 @@
// SPDX-License-Identifier: Apache-2.0
{
- // This is the master cfg hjson for RTL linting. It imports ALL individual lint
+ // This is the primary cfg hjson for RTL linting. It imports ALL individual lint
// cfgs of the IPs and the full chip used in top_earlgrey. This enables to run
// them all as a regression in one shot.
name: top_earlgrey_batch
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index ba0d345..5d78507 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -134,9 +134,9 @@
// spi_device
logic cio_spi_device_sck_p2d;
logic cio_spi_device_csb_p2d;
- logic cio_spi_device_mosi_p2d;
- logic cio_spi_device_miso_d2p;
- logic cio_spi_device_miso_en_d2p;
+ logic cio_spi_device_sdi_p2d;
+ logic cio_spi_device_sdo_d2p;
+ logic cio_spi_device_sdo_en_d2p;
// flash_ctrl
// rv_timer
// aes
@@ -586,11 +586,11 @@
// Input
.cio_sck_i (cio_spi_device_sck_p2d),
.cio_csb_i (cio_spi_device_csb_p2d),
- .cio_mosi_i (cio_spi_device_mosi_p2d),
+ .cio_sdi_i (cio_spi_device_sdi_p2d),
// Output
- .cio_miso_o (cio_spi_device_miso_d2p),
- .cio_miso_en_o (cio_spi_device_miso_en_d2p),
+ .cio_sdo_o (cio_spi_device_sdo_d2p),
+ .cio_sdo_en_o (cio_spi_device_sdo_en_d2p),
// Interrupt
.intr_rxf_o (intr_spi_device_rxf),
@@ -1040,8 +1040,8 @@
assign dio_d2p = {
1'b0, // DIO14: cio_spi_device_sck
1'b0, // DIO13: cio_spi_device_csb
- 1'b0, // DIO12: cio_spi_device_mosi
- cio_spi_device_miso_d2p, // DIO11
+ 1'b0, // DIO12: cio_spi_device_sdi
+ cio_spi_device_sdo_d2p, // DIO11
1'b0, // DIO10: cio_uart_rx
cio_uart_tx_d2p, // DIO9
1'b0, // DIO8: cio_usbdev_sense
@@ -1058,8 +1058,8 @@
assign dio_d2p_en = {
1'b0, // DIO14: cio_spi_device_sck
1'b0, // DIO13: cio_spi_device_csb
- 1'b0, // DIO12: cio_spi_device_mosi
- cio_spi_device_miso_en_d2p, // DIO11
+ 1'b0, // DIO12: cio_spi_device_sdi
+ cio_spi_device_sdo_en_d2p, // DIO11
1'b0, // DIO10: cio_uart_rx
cio_uart_tx_en_d2p, // DIO9
1'b0, // DIO8: cio_usbdev_sense
@@ -1076,8 +1076,8 @@
// Output-only DIOs have no p2d signal
assign cio_spi_device_sck_p2d = dio_p2d[14]; // DIO14
assign cio_spi_device_csb_p2d = dio_p2d[13]; // DIO13
- assign cio_spi_device_mosi_p2d = dio_p2d[12]; // DIO12
- // DIO11: cio_spi_device_miso
+ assign cio_spi_device_sdi_p2d = dio_p2d[12]; // DIO12
+ // DIO11: cio_spi_device_sdo
assign cio_uart_rx_p2d = dio_p2d[10]; // DIO10
// DIO9: cio_uart_tx
assign cio_usbdev_sense_p2d = dio_p2d[8]; // DIO8
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
index 8d8004c..bf5b017 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
@@ -36,8 +36,8 @@
TopEarlgreyDioPinUsbdevSense = 8,
TopEarlgreyDioPinUartTx = 9,
TopEarlgreyDioPinUartRx = 10,
- TopEarlgreyDioPinSpiDeviceMiso = 11,
- TopEarlgreyDioPinSpiDeviceMosi = 12,
+ TopEarlgreyDioPinSpiDeviceSdo = 11,
+ TopEarlgreyDioPinSpiDeviceSdi = 12,
TopEarlgreyDioPinSpiDeviceCsb = 13,
TopEarlgreyDioPinSpiDeviceSck = 14,
TopEarlgreyDioPinCount = 15
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv b/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv
index fc3a897..8352fc3 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv
@@ -13,10 +13,10 @@
// JTAG interface -- not hooked up at the moment
// inout IO_DPS0, // IO_JTCK, IO_SDCK
// inout IO_DPS3, // IO_JTMS, IO_SDCSB
- // inout IO_DPS1, // IO_JTDI, IO_SDMOSI
+ // inout IO_DPS1, // IO_JTDI, IO_SDSDI
// inout IO_DPS4, // IO_JTRST_N,
// inout IO_DPS5, // IO_JSRST_N,
- // inout IO_DPS2, // IO_JTDO, IO_MISO
+ // inout IO_DPS2, // IO_JTDO, IO_SDO
// inout IO_DPS6, // JTAG=1, SPI=0
// inout IO_DPS7, // BOOTSTRAP=1
// UART interface
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
index aa2c121..20c4203 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
@@ -10,10 +10,10 @@
// JTAG interface
inout IO_DPS0, // IO_JTCK, IO_SDCK
inout IO_DPS3, // IO_JTMS, IO_SDCSB
- inout IO_DPS1, // IO_JTDI, IO_SDMOSI
+ inout IO_DPS1, // IO_JTDI, IO_SDSDI
inout IO_DPS4, // IO_JTRST_N,
inout IO_DPS5, // IO_JSRST_N,
- inout IO_DPS2, // IO_JTDO, IO_MISO
+ inout IO_DPS2, // IO_JTDO, IO_SDO
inout IO_DPS6, // JTAG=1, SPI=0
inout IO_DPS7, // BOOTSTRAP=1
// UART interface
@@ -105,8 +105,8 @@
// DIO Pads
.dio_pad_io ( { IO_DPS0, // SCK, JTAG_TCK
IO_DPS3, // CSB, JTAG_TMS
- IO_DPS1, // MOSI, JTAG_TDI
- IO_DPS2, // MISO, JTAG_TDO
+ IO_DPS1, // SDI, JTAG_TDI
+ IO_DPS2, // SDO, JTAG_TDO
IO_URX,
IO_UTX,
IO_USB_SENSE0,
@@ -162,9 +162,9 @@
.TrstIdx ( 18 ), // MIO 18
.SrstIdx ( 19 ), // MIO 19
.TdiIdx ( padctrl_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceMosi ),
+ top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSdi ),
.TdoIdx ( padctrl_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceMiso )
+ top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSdo )
) jtag_mux (
// To JTAG inside core
.jtag_tck_o ( jtag_tck ),
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv b/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv
index c219b3c..ced92de 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv
@@ -13,10 +13,10 @@
// JTAG interface
inout IO_DPS0, // IO_JTCK, IO_SDCK
inout IO_DPS3, // IO_JTMS, IO_SDCSB
- inout IO_DPS1, // IO_JTDI, IO_SDMOSI
+ inout IO_DPS1, // IO_JTDI, IO_SDSDI
inout IO_DPS4, // IO_JTRST_N,
inout IO_DPS5, // IO_JSRST_N,
- inout IO_DPS2, // IO_JTDO, IO_MISO
+ inout IO_DPS2, // IO_JTDO, IO_SDO
inout IO_DPS6, // JTAG=1, SPI=0
inout IO_DPS7, // BOOTSTRAP=1
// UART interface
@@ -127,8 +127,8 @@
// DIO Pads
.dio_pad_io ( { IO_DPS0, // SCK, JTAG_TCK
IO_DPS3, // CSB, JTAG_TMS
- IO_DPS1, // MOSI, JTAG_TDI
- IO_DPS2, // MISO, JTAG_TDO
+ IO_DPS1, // SDI, JTAG_TDI
+ IO_DPS2, // SDO, JTAG_TDO
IO_URX,
IO_UTX,
IO_USB_SENSE0,
@@ -184,9 +184,9 @@
.TrstIdx ( 18 ), // MIO 18
.SrstIdx ( 19 ), // MIO 19
.TdiIdx ( padctrl_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceMosi ),
+ top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSdi ),
.TdoIdx ( padctrl_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceMiso )
+ top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSdo )
) jtag_mux (
// To JTAG inside core
.jtag_tck_o ( jtag_tck ),
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
index 084c916..72329fe 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
@@ -13,10 +13,10 @@
// JTAG interface
inout IO_DPS0, // IO_JTCK, IO_SDCK
inout IO_DPS3, // IO_JTMS, IO_SDCSB
- inout IO_DPS1, // IO_JTDI, IO_SDMOSI
+ inout IO_DPS1, // IO_JTDI, IO_SDSDI
inout IO_DPS4, // IO_JTRST_N,
inout IO_DPS5, // IO_JSRST_N,
- inout IO_DPS2, // IO_JTDO, IO_MISO
+ inout IO_DPS2, // IO_JTDO, IO_SDO
inout IO_DPS6, // JTAG=1, SPI=0
inout IO_DPS7, // BOOTSTRAP=1
// UART interface
@@ -109,8 +109,8 @@
// DIO Pads
.dio_pad_io ( { IO_DPS0, // SCK, JTAG_TCK
IO_DPS3, // CSB, JTAG_TMS
- IO_DPS1, // MOSI, JTAG_TDI
- IO_DPS2, // MISO, JTAG_TDO
+ IO_DPS1, // SDI, JTAG_TDI
+ IO_DPS2, // SDO, JTAG_TDO
IO_URX,
IO_UTX,
IO_USB_SENSE0,
@@ -166,9 +166,9 @@
.TrstIdx ( 18 ), // MIO 18
.SrstIdx ( 19 ), // MIO 19
.TdiIdx ( padctrl_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceMosi ),
+ top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSdi ),
.TdoIdx ( padctrl_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceMiso )
+ top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSdo )
) jtag_mux (
// To JTAG inside core
.jtag_tck_o ( jtag_tck ),
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv b/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
index 189e5a0..b17bd86 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
@@ -15,8 +15,8 @@
logic cio_uart_rx_p2d, cio_uart_tx_d2p, cio_uart_tx_en_d2p;
logic cio_spi_device_sck_p2d, cio_spi_device_csb_p2d;
- logic cio_spi_device_mosi_p2d;
- logic cio_spi_device_miso_d2p, cio_spi_device_miso_en_d2p;
+ logic cio_spi_device_sdi_p2d;
+ logic cio_spi_device_sdo_d2p, cio_spi_device_sdo_en_d2p;
logic cio_usbdev_sense_p2d;
logic cio_usbdev_se0_d2p, cio_usbdev_se0_en_d2p;
@@ -37,7 +37,7 @@
assign dio_in = {cio_spi_device_sck_p2d,
cio_spi_device_csb_p2d,
- cio_spi_device_mosi_p2d,
+ cio_spi_device_sdi_p2d,
1'b0,
cio_uart_rx_p2d,
1'b0,
@@ -60,7 +60,7 @@
assign cio_usbdev_dp_pullup_d2p = dio_out[6];
assign cio_usbdev_se0_d2p = dio_out[7];
assign cio_uart_tx_d2p = dio_out[9];
- assign cio_spi_device_miso_d2p = dio_out[11];
+ assign cio_spi_device_sdo_d2p = dio_out[11];
assign cio_usbdev_dn_en_d2p = dio_oe[0];
assign cio_usbdev_dp_en_d2p = dio_oe[1];
@@ -71,7 +71,7 @@
assign cio_usbdev_dp_pullup_en_d2p = dio_oe[6];
assign cio_usbdev_se0_en_d2p = dio_oe[7];
assign cio_uart_tx_en_d2p = dio_oe[9];
- assign cio_spi_device_miso_en_d2p = dio_oe[11];
+ assign cio_spi_device_sdo_en_d2p = dio_oe[11];
// Top-level design
top_earlgrey top_earlgrey (
@@ -167,9 +167,9 @@
.rst_ni (rst_ni),
.spi_device_sck_o (cio_spi_device_sck_p2d),
.spi_device_csb_o (cio_spi_device_csb_p2d),
- .spi_device_mosi_o (cio_spi_device_mosi_p2d),
- .spi_device_miso_i (cio_spi_device_miso_d2p),
- .spi_device_miso_en_i (cio_spi_device_miso_en_d2p)
+ .spi_device_sdi_o (cio_spi_device_sdi_p2d),
+ .spi_device_sdo_i (cio_spi_device_sdo_d2p),
+ .spi_device_sdo_en_i (cio_spi_device_sdo_en_d2p)
);
// USB DPI
diff --git a/hw/top_earlgrey/syn/constraints.sdc b/hw/top_earlgrey/syn/constraints.sdc
index c5db867..3e496d5 100644
--- a/hw/top_earlgrey/syn/constraints.sdc
+++ b/hw/top_earlgrey/syn/constraints.sdc
@@ -17,8 +17,8 @@
#####################
set PORT_SPI_DEVICE_SCK 14
set PORT_SPI_DEVICE_CSB 13
-set PORT_SPI_DEVICE_MOSI 12
-set PORT_SPI_DEVICE_MISO 11
+set PORT_SPI_DEVICE_SDI 12
+set PORT_SPI_DEVICE_SDO 11
set PORT_UART_RX 10
set PORT_UART_TX 9
@@ -160,11 +160,11 @@
set IN_DEL 6.0
set OUT_DEL 6.0
-set_input_delay ${IN_DEL} [get_ports dio_in_i[$PORT_SPI_DEVICE_CSB]] -clock SPID_CLK
-set_input_delay ${IN_DEL} [get_ports dio_in_i[$PORT_SPI_DEVICE_MOSI]] -clock SPID_CLK
+set_input_delay ${IN_DEL} [get_ports dio_in_i[$PORT_SPI_DEVICE_CSB]] -clock SPID_CLK
+set_input_delay ${IN_DEL} [get_ports dio_in_i[$PORT_SPI_DEVICE_SDI]] -clock SPID_CLK
-set_output_delay ${OUT_DEL} [get_ports dio_out_o[$PORT_SPI_DEVICE_MISO]] -clock SPID_CLK
-set_output_delay ${OUT_DEL} [get_ports dio_oe_o[$PORT_SPI_DEVICE_MISO]] -clock SPID_CLK
+set_output_delay ${OUT_DEL} [get_ports dio_out_o[$PORT_SPI_DEVICE_SDO]] -clock SPID_CLK
+set_output_delay ${OUT_DEL} [get_ports dio_oe_o[$PORT_SPI_DEVICE_SDO]] -clock SPID_CLK
#####################
# CDC #
diff --git a/util/dvsim/FlowCfg.py b/util/dvsim/FlowCfg.py
index fec3c46..64ac88d 100644
--- a/util/dvsim/FlowCfg.py
+++ b/util/dvsim/FlowCfg.py
@@ -51,15 +51,15 @@
# are overridden with the override values.
self.overrides = []
- # List of cfgs if the parsed cfg is a master cfg list
+ # List of cfgs if the parsed cfg is a primary cfg list
self.cfgs = []
- # Add a notion of "master" cfg - this is indicated using
+ # Add a notion of "primary" cfg - this is indicated using
# a special key 'use_cfgs' within the hjson cfg.
- self.is_master_cfg = False
+ self.is_primary_cfg = False
- # For a master cfg, it is the aggregated list of all deploy objects under self.cfgs.
- # For a non-master cfg, it is the list of items slated for dispatch.
+ # For a primary cfg, it is the aggregated list of all deploy objects under self.cfgs.
+ # For a non-primary cfg, it is the list of items slated for dispatch.
self.deploy = []
# Timestamp
@@ -97,7 +97,7 @@
def __post_init__(self):
# Run some post init checks
- if not self.is_master_cfg:
+ if not self.is_primary_cfg:
# Check if self.cfgs is a list of exactly 1 item (self)
if not (len(self.cfgs) == 1 and self.cfgs[0].name == self.name):
log.error("Parse error!\n%s", self.cfgs)
@@ -129,12 +129,12 @@
'''
hjson_dict = parse_hjson(flow_cfg_file)
- # Check if this is the master cfg, if this is the entry point cfg file
+ # Check if this is the primary cfg, if this is the entry point cfg file
if is_entry_point:
- self.is_master_cfg = self.check_if_master_cfg(hjson_dict)
+ self.is_primary_cfg = self.check_if_primary_cfg(hjson_dict)
- # If not a master cfg, then register self with self.cfgs
- if self.is_master_cfg is False:
+ # If not a primary cfg, then register self with self.cfgs
+ if self.is_primary_cfg is False:
self.cfgs.append(self)
# Resolve the raw hjson dict to build this object
@@ -148,8 +148,8 @@
self.rel_path = os.path.dirname(self.flow_cfg_file).replace(
self.proj_root + '/', '')
- def check_if_master_cfg(self, hjson_dict):
- # This is a master cfg only if it has a single key called "use_cfgs"
+ def check_if_primary_cfg(self, hjson_dict):
+ # This is a primary cfg only if it has a single key called "use_cfgs"
# which contains a list of actual flow cfgs.
hjson_cfg_dict_keys = hjson_dict.keys()
return ("use_cfgs" in hjson_cfg_dict_keys and type(hjson_dict["use_cfgs"]) is list)
@@ -226,15 +226,15 @@
import_cfgs.extend(hjson_dict[key])
rm_hjson_dict_keys.append(key)
- # If this is a master cfg list and the key is 'use_cfgs'
- elif self.is_master_cfg and key == "use_cfgs":
+ # If this is a primary cfg list and the key is 'use_cfgs'
+ elif self.is_primary_cfg and key == "use_cfgs":
use_cfgs.extend(hjson_dict[key])
- # If this is a not master cfg list and the key is 'use_cfgs'
- elif not self.is_master_cfg and key == "use_cfgs":
+ # If this is a not primary cfg list and the key is 'use_cfgs'
+ elif not self.is_primary_cfg and key == "use_cfgs":
# Throw an error and exit
log.error(
- "Key \"use_cfgs\" encountered in a non-master cfg file list \"%s\"",
+ "Key \"use_cfgs\" encountered in a non-primary cfg file list \"%s\"",
self.flow_cfg_file)
sys.exit(1)
@@ -254,8 +254,8 @@
else:
log.error("Cfg file \"%s\" has already been parsed", cfg_file)
- # Parse master cfg files
- if self.is_master_cfg:
+ # Parse primary cfg files
+ if self.is_primary_cfg:
for entry in use_cfgs:
if type(entry) is str:
# Treat this as a file entry
@@ -290,10 +290,10 @@
def _conv_inline_cfg_to_hjson(self, idict):
'''Dump a temp hjson file in the scratch space from input dict.
- This method is to be called only by a master cfg'''
+ This method is to be called only by a primary cfg'''
- if not self.is_master_cfg:
- log.fatal("This method can only be called by a master cfg")
+ if not self.is_primary_cfg:
+ log.fatal("This method can only be called by a primary cfg")
sys.exit(1)
name = idict["name"] if "name" in idict.keys() else None
@@ -412,7 +412,7 @@
item._print_list()
def prune_selected_cfgs(self):
- '''Prune the list of configs for a master config file'''
+ '''Prune the list of configs for a primary config file'''
# This should run after self.cfgs has been set
assert self.cfgs
@@ -421,10 +421,10 @@
if self.select_cfgs is None:
return
- # If the user passed --select-cfgs, but this isn't a master config
+ # If the user passed --select-cfgs, but this isn't a primary config
# file, we should probably complain.
- if not self.is_master_cfg:
- log.error('The configuration file at {!r} is not a master config, '
+ if not self.is_primary_cfg:
+ log.error('The configuration file at {!r} is not a primary config, '
'but --select-cfgs was passed on the command line.'
.format(self.flow_cfg_file))
sys.exit(1)
@@ -443,7 +443,7 @@
'''Public facing API for _create_deploy_objects().
'''
self.prune_selected_cfgs()
- if self.is_master_cfg:
+ if self.is_primary_cfg:
self.deploy = []
for item in self.cfgs:
item._create_deploy_objects()
@@ -475,7 +475,7 @@
results.append(result)
self.errors_seen |= item.errors_seen
- if self.is_master_cfg:
+ if self.is_primary_cfg:
self.gen_results_summary()
self.gen_email_html_summary()
@@ -492,7 +492,7 @@
return "[%s](%s)" % (link_text, results_page_url)
def gen_email_html_summary(self):
- if self.is_master_cfg:
+ if self.is_primary_cfg:
# user can customize email content by using email_summary_md,
# otherwise default to send out results_summary_md
gen_results = self.email_summary_md or self.results_summary_md
@@ -651,7 +651,7 @@
for item in self.cfgs:
item._publish_results()
- if self.is_master_cfg:
+ if self.is_primary_cfg:
self.publish_results_summary()
def publish_results_summary(self):
diff --git a/util/dvsim/LintCfg.py b/util/dvsim/LintCfg.py
index 6cb895c..f28e14f 100644
--- a/util/dvsim/LintCfg.py
+++ b/util/dvsim/LintCfg.py
@@ -107,7 +107,7 @@
# parsing script that transforms the tool output into the hjson above
# needs to be adapted.
#
- # note that if this is a master config, the results will
+ # note that if this is a primary config, the results will
# be generated using the _gen_results_summary function
# '''
diff --git a/util/dvsim/OneShotCfg.py b/util/dvsim/OneShotCfg.py
index 578ba47..d574133 100644
--- a/util/dvsim/OneShotCfg.py
+++ b/util/dvsim/OneShotCfg.py
@@ -93,8 +93,8 @@
self.__dict__,
ignored_wildcards)
- # Stuff below only pertains to individual cfg (not master cfg).
- if not self.is_master_cfg:
+ # Stuff below only pertains to individual cfg (not primary cfg).
+ if not self.is_primary_cfg:
# Print info
log.info("[scratch_dir]: [%s]: [%s]", self.name, self.scratch_path)
@@ -113,7 +113,7 @@
self._process_exports()
# Create objects from raw dicts - build_modes, sim_modes, run_modes,
- # tests and regressions, only if not a master cfg obj
+ # tests and regressions, only if not a primary cfg obj
self._create_objects()
# Post init checks
diff --git a/util/dvsim/SimCfg.py b/util/dvsim/SimCfg.py
index 62516d7..2060c45 100644
--- a/util/dvsim/SimCfg.py
+++ b/util/dvsim/SimCfg.py
@@ -160,7 +160,7 @@
self.cov_report_deploy = None
self.results_summary = OrderedDict()
- # If is_master_cfg is set, then each cfg will have its own cov_deploy.
+ # If is_primary_cfg is set, then each cfg will have its own cov_deploy.
# Maintain an array of those in cov_deploys.
self.cov_deploys = []
@@ -190,19 +190,19 @@
self.__dict__ = find_and_substitute_wildcards(self.__dict__,
self.__dict__,
ignored_wildcards,
- self.is_master_cfg)
+ self.is_primary_cfg)
# Set the title for simulation results.
self.results_title = self.name.upper() + " Simulation Results"
- # Stuff below only pertains to individual cfg (not master cfg)
+ # Stuff below only pertains to individual cfg (not primary cfg)
# or individual selected cfgs (if select_cfgs is configured via command line)
# TODO: find a better way to support select_cfgs
- if not self.is_master_cfg and (not self.select_cfgs or
- self.name in self.select_cfgs):
+ if not self.is_primary_cfg and (not self.select_cfgs or
+ self.name in self.select_cfgs):
# If self.tool is None at this point, there was no --tool argument on
# the command line, and there is no default tool set in the config
- # file. That's ok if this is a master config (where the
+ # file. That's ok if this is a primary config (where the
# sub-configurations can choose tools themselves), but not otherwise.
if self.tool is None:
log.error('Config file does not specify a default tool, '
@@ -227,7 +227,7 @@
self._process_exports()
# Create objects from raw dicts - build_modes, sim_modes, run_modes,
- # tests and regressions, only if not a master cfg obj
+ # tests and regressions, only if not a primary cfg obj
self._create_objects()
# Post init checks
diff --git a/util/dvsim/SynCfg.py b/util/dvsim/SynCfg.py
index 4a6991c..53473da 100644
--- a/util/dvsim/SynCfg.py
+++ b/util/dvsim/SynCfg.py
@@ -119,7 +119,7 @@
# }
# }
#
- # note that if this is a master config, the results will
+ # note that if this is a primary config, the results will
# be generated using the _gen_results_summary function
# '''
diff --git a/util/dvsim/dvsim.py b/util/dvsim/dvsim.py
index 16c28c3..3f94485 100755
--- a/util/dvsim/dvsim.py
+++ b/util/dvsim/dvsim.py
@@ -244,10 +244,10 @@
whatg.add_argument("--select-cfgs",
nargs="*",
metavar="CFG",
- help=('The .hjson file is a master config. Only run '
+ help=('The .hjson file is a primary config. Only run '
'the given configs from it. If this argument is '
'not used, dvsim will process all configs listed '
- 'in a master config.'))
+ 'in a primary config.'))
disg = parser.add_argument_group('Dispatch options')
diff --git a/util/fpga/README.md b/util/fpga/README.md
index 85d41fa..dab4314 100644
--- a/util/fpga/README.md
+++ b/util/fpga/README.md
@@ -20,7 +20,7 @@
This directory contains following files:
-* `splice_nexysvideo.sh` - master script
+* `splice_nexysvideo.sh` - main script to load memory contents into bitfile
* `bram_load.mmi` - format which vivado tool understands on which FPGA
BRAM locations the SW contents should go
* `addr4x.py` - utility script used underneath to do address calculation
diff --git a/util/i2csvg/convert.py b/util/i2csvg/convert.py
index 452ee16..bf93e17 100644
--- a/util/i2csvg/convert.py
+++ b/util/i2csvg/convert.py
@@ -2,7 +2,7 @@
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
#
-# Convert I2C master format to SVG
+# Convert I2C host format to SVG
import logging as log
from collections import namedtuple
@@ -121,7 +121,7 @@
S - Start flag, P - stop flag,
R - read flag, C - continue read flag, N - NackOk flag
followed by the data byte
- Special cases:
+ Special cases:
M - indicates multiple bytes instead of data byte
A - followed by 0 or 1 address/direction or 2 address/data
Data value in quotes is a tag
diff --git a/util/i2csvg/smbus/SMBus.md b/util/i2csvg/smbus/SMBus.md
index 8dad018..173363b 100644
--- a/util/i2csvg/smbus/SMBus.md
+++ b/util/i2csvg/smbus/SMBus.md
@@ -1,6 +1,6 @@
-# Using I2C master for SMBus commands
+# Using I2C host for SMBus commands
-The I2C master can generate all the SMBus commands listed in the Rev 3.0 SMBus specification.
+The I2C host can generate all the SMBus commands listed in the Rev 3.0 SMBus specification.
### Quick Command
diff --git a/util/simplespi/spitest.py b/util/simplespi/spitest.py
index 14d754c..f69004e 100755
--- a/util/simplespi/spitest.py
+++ b/util/simplespi/spitest.py
@@ -87,8 +87,8 @@
# interfaces start from 1 here, so this is Channel A (called 0 in jtag)
spi.configure('ftdi://ftdi:2232h/1')
- # Get a port to a SPI slave w/ /CS on A*BUS3 and SPI mode 0 @ 1MHz
- slave = spi.get_port(cs=0, freq=1E6, mode=0)
+ # Get a port to a SPI device w/ /CS on A*BUS3 and SPI mode 0 @ 1MHz
+ device = spi.get_port(cs=0, freq=1E6, mode=0)
# Get GPIO port to manage extra pins
# BUS4 = JTAG TRST_N, BUS5 = JTAG SRST_N, BUS6 = JTAG_SPIN
@@ -120,7 +120,7 @@
print("Select SPI")
gpio.write(0x30)
- # Synchronous exchange with the remote SPI slave
+ # Synchronous exchange with the remote SPI device
if args.length:
s = ''
for i in range(args.length):
@@ -137,7 +137,7 @@
while len(s):
write_buf = bytes(s[:4], encoding='utf8')
- read_buf = slave.exchange(write_buf, duplex=True).tobytes()
+ read_buf = device.exchange(write_buf, duplex=True).tobytes()
print("Got " + str(read_buf))
s = s[4:]
