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opensecura / 3p / lowrisc / opentitan / fe4ea0b25ba835aebfd2f5db87caaf182df2cf99 / . / util / topgen / templates
tree: cbb3aae1dba12e9da538a0270208800ab61ed6bd [path history] [tgz]
  1. alert_test.c.tpl
  2. BUILD.tpl
  3. chip_env_pkg__params.sv.tpl
  4. chiplevel.sv.tpl
  5. clang-format
  6. plic_all_irqs_test.c.tpl
  7. README.md
  8. rstmgr_tgl_excl.cfg.tpl
  9. tb__alert_handler_connect.sv.tpl
  10. tb__xbar_connect.sv.tpl
  11. toplevel.c.tpl
  12. toplevel.h.tpl
  13. toplevel.rs.tpl
  14. toplevel.sv.tpl
  15. toplevel_memory.h.tpl
  16. toplevel_memory.ld.tpl
  17. toplevel_memory.rs.tpl
  18. toplevel_pkg.sv.tpl
  19. toplevel_rnd_cnst_pkg.sv.tpl
  20. xbar_env_pkg__params.sv.tpl
  21. xbar_tgl_excl.cfg.tpl
util/topgen/templates/README.md

OpenTitan topgen templates

This directory contains templates used by topgen to assembly a chip toplevel.