[ast / sensor_ctrl] Expand ast alerts to 13
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast.sv b/hw/top_earlgrey/ip/ast/rtl/ast.sv
index 543134a..4f521bd 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast.sv
@@ -578,6 +578,9 @@
.alert_req_o ( alert_req_o.alerts[Ot3Sel] )
); // of u_alert_ot2
+// temporary assignment
+assign alert_req_o.alerts[Ot4Sel] = '{p: 1'b0, n: 1'b1};
+assign alert_req_o.alerts[Ot5Sel] = '{p: 1'b0, n: 1'b1};
///////////////////////////////////////
// AST Registers (Always ON)
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast_pkg.sv b/hw/top_earlgrey/ip/ast/rtl/ast_pkg.sv
index 8295716..e4cac38 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast_pkg.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast_pkg.sv
@@ -12,7 +12,7 @@
package ast_pkg;
// Alerts
- parameter int NumAlerts = 11;
+ parameter int NumAlerts = 13;
parameter int NumIoRails = 2;
parameter int AsSel = 0;
parameter int CgSel = 1;
@@ -25,6 +25,8 @@
parameter int Ot1Sel = 8;
parameter int Ot2Sel = 9;
parameter int Ot3Sel = 10;
+ parameter int Ot4Sel = 11;
+ parameter int Ot5Sel = 12;
//
parameter int EntropyStreams = 4;
parameter int AdcChannels = 2;
diff --git a/hw/top_earlgrey/ip/sensor_ctrl/data/sensor_ctrl.hjson b/hw/top_earlgrey/ip/sensor_ctrl/data/sensor_ctrl.hjson
index e57e547..b20536b 100644
--- a/hw/top_earlgrey/ip/sensor_ctrl/data/sensor_ctrl.hjson
+++ b/hw/top_earlgrey/ip/sensor_ctrl/data/sensor_ctrl.hjson
@@ -23,7 +23,7 @@
param_list: [
{ name: "NumAlerts",
type: "int",
- default: "11",
+ default: "13",
desc: "Number of alerts",
local: "true"
},
@@ -69,6 +69,12 @@
{ name: "recov_ot3",
desc: "Triggered through AST",
},
+ { name: "recov_ot4",
+ desc: "Triggered through AST",
+ },
+ { name: "recov_ot5",
+ desc: "Triggered through AST",
+ },
]
diff --git a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl.sv b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl.sv
index 68a8ef3..8b23b8a 100644
--- a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl.sv
+++ b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl.sv
@@ -103,6 +103,10 @@
reg2hw.alert_test.recov_ot2.q;
assign alert_test[ast_pkg::Ot3Sel] = reg2hw.alert_test.recov_ot3.qe &
reg2hw.alert_test.recov_ot3.q;
+ assign alert_test[ast_pkg::Ot4Sel] = reg2hw.alert_test.recov_ot4.qe &
+ reg2hw.alert_test.recov_ot4.q;
+ assign alert_test[ast_pkg::Ot5Sel] = reg2hw.alert_test.recov_ot5.qe &
+ reg2hw.alert_test.recov_ot5.q;
// fire an alert whenever indicated
diff --git a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_pkg.sv b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_pkg.sv
index 4dd9321..dc74247 100644
--- a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_pkg.sv
@@ -7,7 +7,7 @@
package sensor_ctrl_reg_pkg;
// Param list
- parameter int NumAlerts = 11;
+ parameter int NumAlerts = 13;
parameter int NumIoRails = 2;
// Address widths within the block
@@ -62,6 +62,14 @@
logic q;
logic qe;
} recov_ot3;
+ struct packed {
+ logic q;
+ logic qe;
+ } recov_ot4;
+ struct packed {
+ logic q;
+ logic qe;
+ } recov_ot5;
} sensor_ctrl_reg2hw_alert_test_reg_t;
typedef struct packed {
@@ -95,15 +103,15 @@
// Register -> HW type
typedef struct packed {
- sensor_ctrl_reg2hw_alert_test_reg_t alert_test; // [76:55]
- sensor_ctrl_reg2hw_ack_mode_mreg_t [10:0] ack_mode; // [54:33]
- sensor_ctrl_reg2hw_alert_trig_mreg_t [10:0] alert_trig; // [32:22]
- sensor_ctrl_reg2hw_alert_state_mreg_t [10:0] alert_state; // [21:0]
+ sensor_ctrl_reg2hw_alert_test_reg_t alert_test; // [90:65]
+ sensor_ctrl_reg2hw_ack_mode_mreg_t [12:0] ack_mode; // [64:39]
+ sensor_ctrl_reg2hw_alert_trig_mreg_t [12:0] alert_trig; // [38:26]
+ sensor_ctrl_reg2hw_alert_state_mreg_t [12:0] alert_state; // [25:0]
} sensor_ctrl_reg2hw_t;
// HW -> register type
typedef struct packed {
- sensor_ctrl_hw2reg_alert_state_mreg_t [10:0] alert_state; // [26:5]
+ sensor_ctrl_hw2reg_alert_state_mreg_t [12:0] alert_state; // [30:5]
sensor_ctrl_hw2reg_status_reg_t status; // [4:0]
} sensor_ctrl_hw2reg_t;
@@ -116,7 +124,7 @@
parameter logic [BlockAw-1:0] SENSOR_CTRL_STATUS_OFFSET = 5'h 14;
// Reset values for hwext registers and their fields
- parameter logic [10:0] SENSOR_CTRL_ALERT_TEST_RESVAL = 11'h 0;
+ parameter logic [12:0] SENSOR_CTRL_ALERT_TEST_RESVAL = 13'h 0;
parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_AS_RESVAL = 1'h 0;
parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_CG_RESVAL = 1'h 0;
parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_GD_RESVAL = 1'h 0;
@@ -128,6 +136,8 @@
parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_OT1_RESVAL = 1'h 0;
parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_OT2_RESVAL = 1'h 0;
parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_OT3_RESVAL = 1'h 0;
+ parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_OT4_RESVAL = 1'h 0;
+ parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_OT5_RESVAL = 1'h 0;
// Register index
typedef enum int {
@@ -143,7 +153,7 @@
parameter logic [3:0] SENSOR_CTRL_PERMIT [6] = '{
4'b 0011, // index[0] SENSOR_CTRL_ALERT_TEST
4'b 0001, // index[1] SENSOR_CTRL_CFG_REGWEN
- 4'b 0111, // index[2] SENSOR_CTRL_ACK_MODE
+ 4'b 1111, // index[2] SENSOR_CTRL_ACK_MODE
4'b 0011, // index[3] SENSOR_CTRL_ALERT_TRIG
4'b 0011, // index[4] SENSOR_CTRL_ALERT_STATE
4'b 0001 // index[5] SENSOR_CTRL_STATUS
diff --git a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv
index 5fafe39..2422860 100644
--- a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv
+++ b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv
@@ -126,6 +126,10 @@
logic alert_test_recov_ot2_we;
logic alert_test_recov_ot3_wd;
logic alert_test_recov_ot3_we;
+ logic alert_test_recov_ot4_wd;
+ logic alert_test_recov_ot4_we;
+ logic alert_test_recov_ot5_wd;
+ logic alert_test_recov_ot5_we;
logic cfg_regwen_qs;
logic cfg_regwen_wd;
logic cfg_regwen_we;
@@ -162,6 +166,12 @@
logic [1:0] ack_mode_val_10_qs;
logic [1:0] ack_mode_val_10_wd;
logic ack_mode_val_10_we;
+ logic [1:0] ack_mode_val_11_qs;
+ logic [1:0] ack_mode_val_11_wd;
+ logic ack_mode_val_11_we;
+ logic [1:0] ack_mode_val_12_qs;
+ logic [1:0] ack_mode_val_12_wd;
+ logic ack_mode_val_12_we;
logic alert_trig_val_0_qs;
logic alert_trig_val_0_wd;
logic alert_trig_val_0_we;
@@ -195,6 +205,12 @@
logic alert_trig_val_10_qs;
logic alert_trig_val_10_wd;
logic alert_trig_val_10_we;
+ logic alert_trig_val_11_qs;
+ logic alert_trig_val_11_wd;
+ logic alert_trig_val_11_we;
+ logic alert_trig_val_12_qs;
+ logic alert_trig_val_12_wd;
+ logic alert_trig_val_12_we;
logic alert_state_val_0_qs;
logic alert_state_val_0_wd;
logic alert_state_val_0_we;
@@ -228,6 +244,12 @@
logic alert_state_val_10_qs;
logic alert_state_val_10_wd;
logic alert_state_val_10_we;
+ logic alert_state_val_11_qs;
+ logic alert_state_val_11_wd;
+ logic alert_state_val_11_we;
+ logic alert_state_val_12_qs;
+ logic alert_state_val_12_wd;
+ logic alert_state_val_12_we;
logic status_ast_init_done_qs;
logic [1:0] status_io_pok_qs;
@@ -399,6 +421,36 @@
);
+ // F[recov_ot4]: 11:11
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test_recov_ot4 (
+ .re (1'b0),
+ .we (alert_test_recov_ot4_we),
+ .wd (alert_test_recov_ot4_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.alert_test.recov_ot4.qe),
+ .q (reg2hw.alert_test.recov_ot4.q),
+ .qs ()
+ );
+
+
+ // F[recov_ot5]: 12:12
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test_recov_ot5 (
+ .re (1'b0),
+ .we (alert_test_recov_ot5_we),
+ .wd (alert_test_recov_ot5_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.alert_test.recov_ot5.qe),
+ .q (reg2hw.alert_test.recov_ot5.q),
+ .qs ()
+ );
+
+
// R[cfg_regwen]: V(False)
prim_subreg #(
@@ -716,6 +768,58 @@
);
+ // F[val_11]: 23:22
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_ack_mode_val_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ack_mode_val_11_we & cfg_regwen_qs),
+ .wd (ack_mode_val_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ack_mode[11].q),
+
+ // to register interface (read)
+ .qs (ack_mode_val_11_qs)
+ );
+
+
+ // F[val_12]: 25:24
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_ack_mode_val_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ack_mode_val_12_we & cfg_regwen_qs),
+ .wd (ack_mode_val_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ack_mode[12].q),
+
+ // to register interface (read)
+ .qs (ack_mode_val_12_qs)
+ );
+
+
// Subregister 0 of Multireg alert_trig
@@ -1007,6 +1111,58 @@
);
+ // F[val_11]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_alert_trig_val_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_trig_val_11_we),
+ .wd (alert_trig_val_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_trig[11].q),
+
+ // to register interface (read)
+ .qs (alert_trig_val_11_qs)
+ );
+
+
+ // F[val_12]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_alert_trig_val_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_trig_val_12_we),
+ .wd (alert_trig_val_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_trig[12].q),
+
+ // to register interface (read)
+ .qs (alert_trig_val_12_qs)
+ );
+
+
// Subregister 0 of Multireg alert_state
@@ -1298,6 +1454,58 @@
);
+ // F[val_11]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_alert_state_val_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_state_val_11_we),
+ .wd (alert_state_val_11_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_state[11].de),
+ .d (hw2reg.alert_state[11].d),
+
+ // to internal hardware
+ .qe (reg2hw.alert_state[11].qe),
+ .q (reg2hw.alert_state[11].q),
+
+ // to register interface (read)
+ .qs (alert_state_val_11_qs)
+ );
+
+
+ // F[val_12]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_alert_state_val_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_state_val_12_we),
+ .wd (alert_state_val_12_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_state[12].de),
+ .d (hw2reg.alert_state[12].d),
+
+ // to internal hardware
+ .qe (reg2hw.alert_state[12].qe),
+ .q (reg2hw.alert_state[12].q),
+
+ // to register interface (read)
+ .qs (alert_state_val_12_qs)
+ );
+
+
// R[status]: V(False)
@@ -1412,6 +1620,12 @@
assign alert_test_recov_ot3_we = addr_hit[0] & reg_we & !reg_error;
assign alert_test_recov_ot3_wd = reg_wdata[10];
+ assign alert_test_recov_ot4_we = addr_hit[0] & reg_we & !reg_error;
+ assign alert_test_recov_ot4_wd = reg_wdata[11];
+
+ assign alert_test_recov_ot5_we = addr_hit[0] & reg_we & !reg_error;
+ assign alert_test_recov_ot5_wd = reg_wdata[12];
+
assign cfg_regwen_we = addr_hit[1] & reg_we & !reg_error;
assign cfg_regwen_wd = reg_wdata[0];
@@ -1448,6 +1662,12 @@
assign ack_mode_val_10_we = addr_hit[2] & reg_we & !reg_error;
assign ack_mode_val_10_wd = reg_wdata[21:20];
+ assign ack_mode_val_11_we = addr_hit[2] & reg_we & !reg_error;
+ assign ack_mode_val_11_wd = reg_wdata[23:22];
+
+ assign ack_mode_val_12_we = addr_hit[2] & reg_we & !reg_error;
+ assign ack_mode_val_12_wd = reg_wdata[25:24];
+
assign alert_trig_val_0_we = addr_hit[3] & reg_we & !reg_error;
assign alert_trig_val_0_wd = reg_wdata[0];
@@ -1481,6 +1701,12 @@
assign alert_trig_val_10_we = addr_hit[3] & reg_we & !reg_error;
assign alert_trig_val_10_wd = reg_wdata[10];
+ assign alert_trig_val_11_we = addr_hit[3] & reg_we & !reg_error;
+ assign alert_trig_val_11_wd = reg_wdata[11];
+
+ assign alert_trig_val_12_we = addr_hit[3] & reg_we & !reg_error;
+ assign alert_trig_val_12_wd = reg_wdata[12];
+
assign alert_state_val_0_we = addr_hit[4] & reg_we & !reg_error;
assign alert_state_val_0_wd = reg_wdata[0];
@@ -1514,6 +1740,12 @@
assign alert_state_val_10_we = addr_hit[4] & reg_we & !reg_error;
assign alert_state_val_10_wd = reg_wdata[10];
+ assign alert_state_val_11_we = addr_hit[4] & reg_we & !reg_error;
+ assign alert_state_val_11_wd = reg_wdata[11];
+
+ assign alert_state_val_12_we = addr_hit[4] & reg_we & !reg_error;
+ assign alert_state_val_12_wd = reg_wdata[12];
+
// Read data return
always_comb begin
reg_rdata_next = '0;
@@ -1530,6 +1762,8 @@
reg_rdata_next[8] = '0;
reg_rdata_next[9] = '0;
reg_rdata_next[10] = '0;
+ reg_rdata_next[11] = '0;
+ reg_rdata_next[12] = '0;
end
addr_hit[1]: begin
@@ -1548,6 +1782,8 @@
reg_rdata_next[17:16] = ack_mode_val_8_qs;
reg_rdata_next[19:18] = ack_mode_val_9_qs;
reg_rdata_next[21:20] = ack_mode_val_10_qs;
+ reg_rdata_next[23:22] = ack_mode_val_11_qs;
+ reg_rdata_next[25:24] = ack_mode_val_12_qs;
end
addr_hit[3]: begin
@@ -1562,6 +1798,8 @@
reg_rdata_next[8] = alert_trig_val_8_qs;
reg_rdata_next[9] = alert_trig_val_9_qs;
reg_rdata_next[10] = alert_trig_val_10_qs;
+ reg_rdata_next[11] = alert_trig_val_11_qs;
+ reg_rdata_next[12] = alert_trig_val_12_qs;
end
addr_hit[4]: begin
@@ -1576,6 +1814,8 @@
reg_rdata_next[8] = alert_state_val_8_qs;
reg_rdata_next[9] = alert_state_val_9_qs;
reg_rdata_next[10] = alert_state_val_10_qs;
+ reg_rdata_next[11] = alert_state_val_11_qs;
+ reg_rdata_next[12] = alert_state_val_12_qs;
end
addr_hit[5]: begin
diff --git a/util/topgen.py b/util/topgen.py
index 8ddf19a..2d3dde0 100755
--- a/util/topgen.py
+++ b/util/topgen.py
@@ -150,7 +150,8 @@
for alert in top['alert']:
for k in range(alert['width']):
async_on = str(alert['async']) + async_on
- async_on = ("%d'b" % n_alerts) + async_on
+ # convert to hexstring to shorten line length
+ async_on = ("%d'h" % n_alerts) + hex(int(async_on,2))[2:]
log.info("alert handler parameterization:")
log.info("NAlerts = %d" % n_alerts)
