| commit | fe294ca0b6e02ff8f3f9d87e9ba54579139edc0e | [log] [tgz] |
|---|---|---|
| author | Nigel Scales <nigel.scales@gmail.com> | Fri Mar 04 15:36:35 2022 +0000 |
| committer | cindychip <cindy.chen0316@gmail.com> | Sun Mar 06 23:04:20 2022 -0800 |
| tree | 2c751845a5b79c3c64ba0671d8fccba1d599c72a | |
| parent | caac850c7a837ecbfcc1027197d856d696f902ae [diff] |
[adc_ctrl/dv] Added counter tests
- Added tests
- adc_ctrl_poweron_counter
- adc_ctrl_lowpower_counter
- Added test sequences
- adc_ctrl_counter_vseq
Randomize wakeup_time powerup_time and low/high/one shot power mode, wait for data then repeat.
- adc_ctrl_poweron_counter_vseq
Extends adc_ctrl_counter_vseq for normal and one shot mode.
- adc_ctrl_lowpower_counter_vseq
Extends adc_ctrl_counter_vseq for low power mode.
- Added assertions
- WakeupTime_A - checks wakeup timing in low power mode
- EnterLowPower_A - Checks ADC controller enters low power mode
- Updated model
- Updated to latest spec / RTL
- Modelled adc_fsm_reset register
- Modelled interrupt registers for One Shot mode.
- Updated adc_ctrl_filters_polled_vseq to perform FSM reset at the end of each iteration as
to make sure model and RTL are synchronised before each new configuration
- Updated PwrupTime_A to new spec (programmed value + 2) cycles
- Enabled PwrupTime_A for all tests and removed plusarg control
Signed-off-by: Nigel Scales <nigel.scales@gmail.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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