commit fd2c22e839006ef31bc275368dd8a1422ae71423
author Weicai Yang <weicai@google.com> Tue Feb 11 18:37:14 2020 -0800
committer weicaiyang <49293026+weicaiyang@users.noreply.github.com> Fri Feb 21 13:30:08 2020 -0800
tree 8ea9411c012c47a4c4a96ca2f0dfa11414b610d1
parent 9d3e40053d4a4cf3ebaa8319bb0082407be419bb

[dv] Add simulation result summary page

Here is the report that will be generated
https://reports.opentitan.org/hw/top_earlgrey/dv/summarys.html
Also fix xbar coverage error

Signed-off-by: Weicai Yang <weicai@google.com>

util/tlgen/generate.py

diff --git a/util/tlgen/generate.py b/util/tlgen/generate.py
index 6320783..3b39ab0 100644
--- a/util/tlgen/generate.py
+++ b/util/tlgen/generate.py
@@ -3,6 +3,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 import logging as log
+
 from mako import exceptions
 from mako.template import Template
 from pkg_resources import resource_filename
@@ -11,7 +12,6 @@
 from .xbar import Xbar
 
 
-
 def generate(xbar):  #xbar: Xbar -> str
     """generate uses elaborated model then creates top level Xbar module
     with prefix.

util/tlgen/generate_tb.py

diff --git a/util/tlgen/generate_tb.py b/util/tlgen/generate_tb.py
index 446f5f4..64b0d6b 100644
--- a/util/tlgen/generate_tb.py
+++ b/util/tlgen/generate_tb.py
@@ -16,7 +16,7 @@
     # list all the generate files for TB
     tb_files = [
         "xbar_env_pkg__params.sv", "tb__xbar_connect.sv", "xbar.sim.core",
-        "xbar.bind.sv", "Makefile", "xbar.sim_cfg.hjson"
+        "xbar.bind.sv", "Makefile", "xbar.sim_cfg.hjson", "xbar.testplan.hjson"
     ]
 
     for fname in tb_files:
@@ -29,8 +29,15 @@
             fname = "xbar_%s_bind.sv" % (xbar.name)
         elif fname == "xbar.sim_cfg.hjson":
             fname = "xbar_%s_sim_cfg.hjson" % (xbar.name)
+        elif fname == "xbar.testplan.hjson":
+            fname = "xbar_%s_testplan.hjson" % (xbar.name)
 
-        dv_filepath = dv_path / fname
+        # save testplan at data directory
+        if fname == "xbar_%s_testplan.hjson" % (xbar.name):
+            dv_filepath = dv_path / '../../data/autogen' / fname
+        else:
+            dv_filepath = dv_path / fname
+
         with dv_filepath.open(mode='w', encoding='UTF-8') as fout:
             try:
                 fout.write(tpl.render(xbar=xbar))

util/tlgen/xbar.sim_cfg.hjson.tpl

diff --git a/util/tlgen/xbar.sim_cfg.hjson.tpl b/util/tlgen/xbar.sim_cfg.hjson.tpl
index decb93e..4ff37b2 100644
--- a/util/tlgen/xbar.sim_cfg.hjson.tpl
+++ b/util/tlgen/xbar.sim_cfg.hjson.tpl
@@ -7,12 +7,6 @@
   // Top level dut name (sv module).
   dut: xbar_${xbar.name}
 
-  // Testplan hjson file.
-  testplan: "{proj_root}/hw/top_earlgrey/ip/xbar_${xbar.name}/data/autogen/xbar_${xbar.name}_testplan.hjson"
-
-  // Add xbar_${xbar.name} specific exclusion files.
-  vcs_cov_excl_files: ["{proj_root}/hw/top_earlgrey/ip/xbar_${xbar.name}/dv/cov/xbar_cov_excl.el"]
-
   // Import additional common sim cfg files.
   import_cfgs: [// xbar common sim cfg file
                 "{proj_root}/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson"]

util/tlgen/xbar.testplan.hjson.tpl

diff --git a/util/tlgen/xbar.testplan.hjson.tpl b/util/tlgen/xbar.testplan.hjson.tpl
new file mode 100644
index 0000000..11e5cc8
--- /dev/null
+++ b/util/tlgen/xbar.testplan.hjson.tpl
@@ -0,0 +1,9 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_${xbar.name}_testplan.hjson file generated by `tlgen.py` tool
+{
+  name: "xbar_${xbar.name}"
+  import_testplans: ["hw/ip/tlul/data/tlul_testplan.hjson"]
+}