[top] auto-generate files
Signed-off-by: Timothy Chen <timothytim@google.com>
[top / flash_ctrl] more auto generate files
Signed-off-by: Timothy Chen <timothytim@google.com>
[top] Auto-generate files
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
index 0474d14..deb6564 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
@@ -60,6 +60,8 @@
],
param_list: [
+ // The reg parameters can be modified directly through top_*.hjson.
+ // The template will automatically propagate the appropriate values.
{ name: "RegNumBanks",
desc: "Number of flash banks",
type: "int",
@@ -67,6 +69,13 @@
local: "true"
},
+ { name: "RegPagesPerBank",
+ desc: "Number of pages per bank",
+ type: "int",
+ default: "256",
+ local: "true"
+ },
+
{ name: "NumRegions",
desc: "Number of configurable flash regions",
type: "int",
@@ -74,6 +83,8 @@
local: "true"
},
+ // The following parameters are derived from topgen and should not be
+ // direclty modified.
{ name: "NumInfos0",
desc: "Number of configurable flash info pages for info type 0",
type: "int",
@@ -86,6 +97,38 @@
default: "4",
local: "true"
},
+
+ { name: "WordsPerPage",
+ desc: "Number of words per page",
+ type: "int",
+ default: "128",
+ local: "true"
+ },
+
+ { name: "BytesPerWord",
+ desc: "Number of bytes per word",
+ type: "int",
+ default: "8",
+ local: "true"
+ },
+
+ { name: "BytesPerPage",
+ desc: "Number of bytes per page",
+ type: "int",
+ default: "1024",
+ local: "true"
+ },
+
+ { name: "BytesPerBank",
+ desc: "Number of bytes per bank",
+ type: "int",
+ default: "262144",
+ local: "true"
+ },
+
+
+
+
],
regwidth: "32",
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
index e64d0b5..83f1c46 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
@@ -7,8 +7,11 @@
package flash_ctrl_pkg;
- // design constants
+ // design parameters that can be altered through topgen
parameter int NumBanks = flash_ctrl_reg_pkg::RegNumBanks;
+ parameter int PagesPerBank = flash_ctrl_reg_pkg::RegPagesPerBank;
+
+ // fixed parameters of flash derived from topgen parameters
parameter int DataWidth = 64;
parameter int MetaDataWidth = 12;
parameter int InfoTypes = 2; // How many types of info per bank
@@ -24,7 +27,6 @@
4,
4
});
- parameter int PagesPerBank = 256; // Data pages per bank
parameter int WordsPerPage = 128; // Number of flash words per page
parameter int BusWidth = top_pkg::TL_DW;
parameter int MpRegions = 8; // flash controller protection regions
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
index 5cf54aa..0b1c4ea 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
@@ -8,9 +8,14 @@
// Param list
parameter int RegNumBanks = 2;
+ parameter int RegPagesPerBank = 256;
parameter int NumRegions = 8;
parameter int NumInfos0 = 4;
parameter int NumInfos1 = 4;
+ parameter int WordsPerPage = 128;
+ parameter int BytesPerWord = 8;
+ parameter int BytesPerPage = 1024;
+ parameter int BytesPerBank = 262144;
////////////////////////////
// Typedefs for registers //
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 43d0303..4fef081 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -675,6 +675,7 @@
rst_ni: lc
}
base_addr: 0x40030000
+ generated: "true"
clock_reset_export: []
clock_connections:
{
@@ -3149,8 +3150,9 @@
}
type: eflash
base_addr: 0x20000000
+ banks: 2
+ pages_per_bank: 256
swaccess: ro
- size: 0x80000
inter_signal_list:
[
{
@@ -3183,6 +3185,16 @@
{
clk_i: clkmgr_clocks.clk_main_infra
}
+ words_per_page: 128
+ data_width: 64
+ metadata_width: 12
+ info_types: 2
+ infos_per_bank:
+ [
+ 4
+ 4
+ ]
+ size: 0x80000
}
]
inter_module:
diff --git a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
new file mode 100644
index 0000000..7e7aef8
--- /dev/null
+++ b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
@@ -0,0 +1,963 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{ name: "FLASH_CTRL",
+ clock_primary: "clk_i",
+ bus_device: "tlul",
+ interrupt_list: [
+ { name: "prog_empty", desc: "Program FIFO empty" },
+ { name: "prog_lvl", desc: "Program FIFO drained to level" },
+ { name: "rd_full", desc: "Read FIFO full" },
+ { name: "rd_lvl", desc: "Read FIFO filled to level" },
+ { name: "op_done", desc: "Operation complete" },
+ { name: "op_error", desc: "Operation failed with error" },
+ ],
+
+ // Define flash_ctrl <-> flash_phy struct package
+ inter_signal_list: [
+ { struct: "flash", // flash_req_t, flash_rsp_t
+ type: "req_rsp",
+ name: "flash", // flash_o (req), flash_i (rsp)
+ act: "req",
+ package: "flash_ctrl_pkg", // Origin package (only needs for the requester)
+ },
+
+ { struct: "otp_flash",
+ type: "uni",
+ name: "otp",
+ act: "rcv",
+ package: "flash_ctrl_pkg"
+ },
+
+ { struct: "lc_flash",
+ type: "req_rsp",
+ name: "lc",
+ act: "rsp",
+ package: "flash_ctrl_pkg"
+ },
+
+ { struct: "edn_entropy",
+ type: "uni",
+ name: "edn",
+ act: "rcv",
+ package: "flash_ctrl_pkg"
+ },
+
+ { struct: "pwr_flash",
+ type: "req_rsp",
+ name: "pwrmgr",
+ act: "rsp",
+ package: "pwrmgr_pkg"
+ },
+
+ { struct: "keymgr_flash",
+ type: "uni",
+ name: "keymgr",
+ act: "req",
+ package: "flash_ctrl_pkg"
+ }
+
+ ],
+
+ param_list: [
+ // The reg parameters can be modified directly through top_*.hjson.
+ // The template will automatically propagate the appropriate values.
+ { name: "RegNumBanks",
+ desc: "Number of flash banks",
+ type: "int",
+ default: "2",
+ local: "true"
+ },
+
+ { name: "RegPagesPerBank",
+ desc: "Number of pages per bank",
+ type: "int",
+ default: "256",
+ local: "true"
+ },
+
+ { name: "NumRegions",
+ desc: "Number of configurable flash regions",
+ type: "int",
+ default: "8",
+ local: "true"
+ },
+
+ // The following parameters are derived from topgen and should not be
+ // direclty modified.
+ { name: "NumInfos0",
+ desc: "Number of configurable flash info pages for info type 0",
+ type: "int",
+ default: "4",
+ local: "true"
+ },
+ { name: "NumInfos1",
+ desc: "Number of configurable flash info pages for info type 1",
+ type: "int",
+ default: "4",
+ local: "true"
+ },
+
+ { name: "WordsPerPage",
+ desc: "Number of words per page",
+ type: "int",
+ default: "128",
+ local: "true"
+ },
+
+ { name: "BytesPerWord",
+ desc: "Number of bytes per word",
+ type: "int",
+ default: "8",
+ local: "true"
+ },
+
+ { name: "BytesPerPage",
+ desc: "Number of bytes per page",
+ type: "int",
+ default: "1024",
+ local: "true"
+ },
+
+ { name: "BytesPerBank",
+ desc: "Number of bytes per bank",
+ type: "int",
+ default: "262144",
+ local: "true"
+ },
+
+
+
+
+ ],
+
+ regwidth: "32",
+ registers: [
+
+ { name: "CTRL_REGWEN",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ desc: '''
+ Controls the configurability of the !!CONTROL register.
+
+ This register ensures the contents of !!CONTROL cannot be changed by software once a flash
+ operation has begun.
+
+ It unlocks whenever the existing flash operation completes, regardless of success or error.
+ ''',
+
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Configuration enable.
+
+ This bit defaults to 1 and is set to 0 by hardware when flash operation is initiated.
+ When the controller completes the flash operation, this bit is set
+ back to 1 to allow software configuration of !!CONTROL
+ ''',
+ resval: "1",
+ },
+ ]
+ tags: [// This regwen is completely under HW management and thus cannot be manipulated
+ // by software.
+ "excl:CsrNonInitTests:CsrExclCheck"]
+ },
+
+
+ { name: "CONTROL",
+ desc: "Control register",
+ regwen: "CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "0",
+ hwaccess: "hrw",
+ name: "START",
+ desc: '''
+ Start flash transaction. This bit shall only be set after the other fields of the
+ CONTROL register and ADDR have been programmed
+ '''
+ resval: "0"
+ tags: [// Dont enable flash - it causes several side-effects.
+ "excl:CsrAllTests:CsrExclWrite"],
+ },
+ { bits: "5:4",
+ name: "OP",
+ desc: "Flash operation selection",
+ resval: "0"
+ enum: [
+ { value: "0",
+ name: "Read",
+ desc: '''
+ Flash Read.
+
+ Read desired number of flash words
+ '''
+ },
+ { value: "1",
+ name: "Prog",
+ desc: '''
+ Flash Program.
+
+ Program desired number of flash words
+ '''
+ },
+ { value: "2",
+ name: "Erase",
+ desc: '''
+ Flash Erase Operation.
+
+ See ERASE_SEL for details on erase operation
+ '''
+ },
+ ]
+ },
+
+ { bits: "6",
+ name: "PROG_SEL",
+ desc: "Flash program operation type selection",
+ resval: "0"
+ enum: [
+ { value: "0",
+ name: "Normal program",
+ desc: '''
+ Normal program operation to the flash
+ '''
+ },
+ { value: "1",
+ name: "Program repair",
+ desc: '''
+ Repair program operation to the flash. Whether this is actually
+ supported depends on the underlying flash memory.
+ '''
+ },
+ ]
+ },
+
+ { bits: "7",
+ name: "ERASE_SEL",
+ desc: "Flash erase operation type selection",
+ resval: "0"
+ enum: [
+ { value: "0",
+ name: "Page Erase",
+ desc: '''
+ Erase 1 page of flash
+ '''
+ },
+ { value: "1",
+ name: "Bank Erase",
+ desc: '''
+ Erase 1 bank of flash
+ '''
+ },
+ ]
+ },
+ { bits: "8",
+ name: "PARTITION_SEL",
+ desc: '''
+ Selects either info or data partition for operation.
+
+ When 0, select data partition - this is the portion of flash that is accessible both
+ by the host and by the controller.
+
+ When 1, select info partition - this is the portion of flash that is only accessible
+ by the controller.
+
+ '''
+ resval: "0"
+ },
+ { bits: "9",
+ name: "INFO_SEL",
+ desc: '''
+ Informational partions can have multiple types.
+
+ This field selects the info type to be accessed.
+ '''
+ resval: "0"
+ },
+ { bits: "27:16",
+ name: "NUM",
+ desc: "Number of bus words the flash operation should read or program.",
+ resval: "0"
+ },
+ ]
+ },
+ { name: "ADDR",
+ desc: "Address for flash operation",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ fields: [
+ { bits: "31:0",
+ name: "START",
+ desc: '''
+ Start address of a flash transaction. Software should supply the full byte address.
+ The flash controller will then truncate the address as needed. For read operations,
+ the flash controller will truncate to the closest, lower word aligned address. For
+ example, if 0x13 is supplied, the controller will perform a read at address 0x10.
+
+ Program operations behave similarly, the controller does not have read modified write
+ support.
+
+ For page erases, the controller will truncate to the closest lower page aligned
+ address. Similarly for bank erases, the controller will truncate to the closest
+ lower bank aligned address.
+ '''
+ resval: "0"
+ },
+ ]
+ },
+
+ // Data partition memory protection region setup
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "REGION_CFG_REGWEN"
+ desc: "Memory region registers configuration enable.",
+ count: "NumRegions",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ compact: false,
+ fields: [
+ { bits: "0",
+ name: "REGION",
+ resval: "1"
+ desc: "Region register write enable. Once set to 0, it can longer be configured to 1",
+ enum: [
+ { value: "0",
+ name: "Region locked",
+ desc: '''
+ Region can no longer be configured until next reset
+ '''
+ },
+ { value: "1",
+ name: "Region enabled",
+ desc: '''
+ Region can be configured
+ '''
+ },
+ ]
+ },
+ ],
+ },
+ },
+
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "MP_REGION_CFG",
+ desc: "Memory protection configuration for data partition",
+ count: "NumRegions",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGION_CFG_REGWEN",
+ regwen_multi: true,
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Region enabled, following fields apply
+ ''',
+ resval: "0"
+ },
+ { bits: "1",
+ name: "RD_EN",
+ desc: '''
+ Region can be read
+ ''',
+ resval: "0"
+ },
+ { bits: "2",
+ name: "PROG_EN",
+ desc: '''
+ Region can be programmed
+ ''',
+ resval: "0"
+ }
+ { bits: "3",
+ name: "ERASE_EN",
+ desc: '''
+ Region can be erased
+ ''',
+ resval: "0"
+ }
+ { bits: "4",
+ name: "SCRAMBLE_EN",
+ desc: '''
+ Region is scramble and ECC enabled.
+ ''',
+ resval: "0"
+ }
+ { bits: "16:8",
+ name: "BASE",
+ desc: '''
+ Region base page. Note the granularity is page, not byte or word
+ ''',
+ resval: "0"
+ },
+ { bits: "29:20", // need to template this term long term for flash size
+ name: "SIZE",
+ desc: '''
+ Region size in number of pages
+ ''',
+ resval: "0"
+ },
+ ],
+ },
+ },
+
+ // Default region permissions for data partition memory protection
+ { name: "DEFAULT_REGION",
+ desc: "Default region permissions",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ fields: [
+ { bits: "0",
+ name: "RD_EN",
+ desc: '''
+ Region can be read
+ ''',
+ resval: "0"
+ },
+ { bits: "1",
+ name: "PROG_EN",
+ desc: '''
+ Region can be programmed
+ ''',
+ resval: "0"
+ }
+ { bits: "2",
+ name: "ERASE_EN",
+ desc: '''
+ Region can be erased
+ ''',
+ resval: "0"
+ },
+ { bits: "3",
+ name: "SCRAMBLE_EN",
+ desc: '''
+ Region is scramble and ECC enabled
+ ''',
+ resval: "0"
+ }
+ ]
+ },
+
+ // Info partition memory protection setup
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "BANK0_INFO0_REGWEN"
+ desc: "Memory region registers configuration enable.",
+ count: "NumInfos0",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ compact: false,
+ fields: [
+ { bits: "0",
+ name: "REGION",
+ resval: "1"
+ desc: "Info0 page write enable. Once set to 0, it can longer be configured to 1",
+ enum: [
+ { value: "0",
+ name: "Page locked",
+ desc: '''
+ Region can no longer be configured until next reset
+ '''
+ },
+ { value: "1",
+ name: "Page enabled",
+ desc: '''
+ Region can be configured
+ '''
+ },
+ ]
+ },
+ ],
+ },
+ },
+
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "BANK0_INFO0_PAGE_CFG",
+ desc: '''
+ Memory protection configuration for info partition in bank0,
+ Unlike data partition, each page is individually protected.
+ '''
+ count: "NumInfos0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "BANK0_INFO0_REGWEN",
+ regwen_multi: true,
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Region enabled, following fields apply
+ ''',
+ resval: "0"
+ },
+ { bits: "1",
+ name: "RD_EN",
+ desc: '''
+ Region can be read
+ ''',
+ resval: "0"
+ },
+ { bits: "2",
+ name: "PROG_EN",
+ desc: '''
+ Region can be programmed
+ ''',
+ resval: "0"
+ }
+ { bits: "3",
+ name: "ERASE_EN",
+ desc: '''
+ Region can be erased
+ ''',
+ resval: "0"
+ }
+ { bits: "4",
+ name: "SCRAMBLE_EN",
+ desc: '''
+ Region is scramble and ECC enabled.
+ ''',
+ resval: "0"
+ }
+ ],
+ },
+ },
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "BANK0_INFO1_REGWEN"
+ desc: "Memory region registers configuration enable.",
+ count: "NumInfos1",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ compact: false,
+ fields: [
+ { bits: "0",
+ name: "REGION",
+ resval: "1"
+ desc: "Info1 page write enable. Once set to 0, it can longer be configured to 1",
+ enum: [
+ { value: "0",
+ name: "Page locked",
+ desc: '''
+ Region can no longer be configured until next reset
+ '''
+ },
+ { value: "1",
+ name: "Page enabled",
+ desc: '''
+ Region can be configured
+ '''
+ },
+ ]
+ },
+ ],
+ },
+ },
+
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "BANK0_INFO1_PAGE_CFG",
+ desc: '''
+ Memory protection configuration for info partition in bank0,
+ Unlike data partition, each page is individually protected.
+ '''
+ count: "NumInfos1",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "BANK0_INFO1_REGWEN",
+ regwen_multi: true,
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Region enabled, following fields apply
+ ''',
+ resval: "0"
+ },
+ { bits: "1",
+ name: "RD_EN",
+ desc: '''
+ Region can be read
+ ''',
+ resval: "0"
+ },
+ { bits: "2",
+ name: "PROG_EN",
+ desc: '''
+ Region can be programmed
+ ''',
+ resval: "0"
+ }
+ { bits: "3",
+ name: "ERASE_EN",
+ desc: '''
+ Region can be erased
+ ''',
+ resval: "0"
+ }
+ { bits: "4",
+ name: "SCRAMBLE_EN",
+ desc: '''
+ Region is scramble and ECC enabled.
+ ''',
+ resval: "0"
+ }
+ ],
+ },
+ },
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "BANK1_INFO0_REGWEN"
+ desc: "Memory region registers configuration enable.",
+ count: "NumInfos0",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ compact: false,
+ fields: [
+ { bits: "0",
+ name: "REGION",
+ resval: "1"
+ desc: "Info0 page write enable. Once set to 0, it can longer be configured to 1",
+ enum: [
+ { value: "0",
+ name: "Page locked",
+ desc: '''
+ Region can no longer be configured until next reset
+ '''
+ },
+ { value: "1",
+ name: "Page enabled",
+ desc: '''
+ Region can be configured
+ '''
+ },
+ ]
+ },
+ ],
+ },
+ },
+
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "BANK1_INFO0_PAGE_CFG",
+ desc: '''
+ Memory protection configuration for info partition in bank1,
+ Unlike data partition, each page is individually protected.
+ '''
+ count: "NumInfos0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "BANK1_INFO0_REGWEN",
+ regwen_multi: true,
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Region enabled, following fields apply
+ ''',
+ resval: "0"
+ },
+ { bits: "1",
+ name: "RD_EN",
+ desc: '''
+ Region can be read
+ ''',
+ resval: "0"
+ },
+ { bits: "2",
+ name: "PROG_EN",
+ desc: '''
+ Region can be programmed
+ ''',
+ resval: "0"
+ }
+ { bits: "3",
+ name: "ERASE_EN",
+ desc: '''
+ Region can be erased
+ ''',
+ resval: "0"
+ }
+ { bits: "4",
+ name: "SCRAMBLE_EN",
+ desc: '''
+ Region is scramble and ECC enabled.
+ ''',
+ resval: "0"
+ }
+ ],
+ },
+ },
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "BANK1_INFO1_REGWEN"
+ desc: "Memory region registers configuration enable.",
+ count: "NumInfos1",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ compact: false,
+ fields: [
+ { bits: "0",
+ name: "REGION",
+ resval: "1"
+ desc: "Info1 page write enable. Once set to 0, it can longer be configured to 1",
+ enum: [
+ { value: "0",
+ name: "Page locked",
+ desc: '''
+ Region can no longer be configured until next reset
+ '''
+ },
+ { value: "1",
+ name: "Page enabled",
+ desc: '''
+ Region can be configured
+ '''
+ },
+ ]
+ },
+ ],
+ },
+ },
+
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "BANK1_INFO1_PAGE_CFG",
+ desc: '''
+ Memory protection configuration for info partition in bank1,
+ Unlike data partition, each page is individually protected.
+ '''
+ count: "NumInfos1",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "BANK1_INFO1_REGWEN",
+ regwen_multi: true,
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Region enabled, following fields apply
+ ''',
+ resval: "0"
+ },
+ { bits: "1",
+ name: "RD_EN",
+ desc: '''
+ Region can be read
+ ''',
+ resval: "0"
+ },
+ { bits: "2",
+ name: "PROG_EN",
+ desc: '''
+ Region can be programmed
+ ''',
+ resval: "0"
+ }
+ { bits: "3",
+ name: "ERASE_EN",
+ desc: '''
+ Region can be erased
+ ''',
+ resval: "0"
+ }
+ { bits: "4",
+ name: "SCRAMBLE_EN",
+ desc: '''
+ Region is scramble and ECC enabled.
+ ''',
+ resval: "0"
+ }
+ ],
+ },
+ },
+
+ { name: "BANK_CFG_REGWEN"
+ desc: "Bank configuration registers configuration enable.",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ fields: [
+ { bits: "0",
+ name: "BANK",
+ resval: "1"
+ desc: "Bank register write enable. Once set to 0, it can longer be configured to 1",
+ enum: [
+ { value: "0",
+ name: "Bank locked",
+ desc: '''
+ Bank can no longer be configured until next reset
+ '''
+ },
+ { value: "1",
+ name: "Bank enabled",
+ desc: '''
+ Bank can be configured
+ '''
+ },
+ ]
+ },
+ ],
+ },
+
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "MP_BANK_CFG",
+ desc: "Memory protect bank configuration",
+ count: "RegNumBanks",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "BANK_CFG_REGWEN"
+ fields: [
+ { bits: "0",
+ name: "ERASE_EN",
+ desc: '''
+ Bank wide erase enable
+ ''',
+ resval: "0"
+ },
+ ],
+ },
+ },
+
+ { name: "OP_STATUS",
+ desc: "Flash Operation Status",
+ swaccess: "rw",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "0", name: "done",
+ desc: "Flash operation done. Set by HW, cleared by SW" },
+ { bits: "1", name: "err",
+ desc: "Flash operation error. Set by HW, cleared by SW"},
+ ]
+ },
+ { name: "STATUS",
+ desc: "Flash Controller Status",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "0", name: "rd_full", desc: "Flash read FIFO full, software must consume data"},
+ { bits: "1", name: "rd_empty", desc: "Flash read FIFO empty", resval: "1"},
+ { bits: "2", name: "prog_full", desc: "Flash program FIFO full"},
+ { bits: "3", name: "prog_empty", desc: "Flash program FIFO empty, software must provide data", resval: "1"},
+ { bits: "4", name: "init_wip", desc: "Flash controller undergoing init, inclusive of phy init"},
+ { bits: "16:8", name: "error_addr", desc: "Flash controller error address."},
+ ]
+ },
+
+ { name: "PHY_STATUS",
+ desc: "Flash Phy Status",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "0",
+ name: "init_wip",
+ desc: "Flash phy controller initializing"
+ },
+ { bits: "1",
+ name: "prog_normal_avail",
+ resval: "0x1",
+ desc: "Normal program supported"
+ },
+ { bits: "2",
+ name: "prog_repair_avail",
+ resval: "0x1",
+ desc: "Program repair supported"
+ },
+ ]
+ },
+
+ { name: "Scratch",
+ desc: "Flash Controller Scratch",
+ swaccess: "rw",
+ fields: [
+ { bits: "31:0", name: "data", desc: "Flash ctrl scratch register" },
+ ]
+ },
+ { name: "FIFO_LVL",
+ desc: "Programmable depth where FIFOs should generate interrupts",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "4:0",
+ name: "PROG",
+ desc: '''
+ When the program FIFO drains to this level, trigger an interrupt.
+ Default value is set such that interrupt does not trigger at reset.
+ '''
+ resval: "0xF"
+ },
+ { bits: "12:8",
+ name: "RD",
+ desc: '''
+ When the read FIFO fills to this level, trigger an interrupt.
+ Default value is set such that interrupt does not trigger at reset.
+ '''
+ resval: "0xF"
+ },
+ ]
+ }
+
+ { name: "FIFO_RST",
+ desc: "Reset for flash controller FIFOs",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Active high resets for both program and read FIFOs. This is especially useful after the controller
+ encounters an error of some kind.
+
+ This bit will hold the FIFO in reset as long as it is set.
+ '''
+ resval: "0"
+ },
+ ]
+ },
+
+ { window: {
+ name: "prog_fifo",
+ items: "1",
+ validbits: "32",
+ byte-write: "false",
+ unusual: "false"
+ swaccess: "wo",
+ desc: '''
+ Flash program FIFO.
+
+ The FIFO is 16 entries of 4B flash words. This FIFO can only be programmed
+ by software after a program operation has been initiated via the !!CONTROL register.
+ This ensures accidental programming of the program FIFO cannot lock up the system.
+ '''
+ },
+ },
+ { window: {
+ name: "rd_fifo",
+ items: "1",
+ validbits: "32",
+ byte-write: "false",
+ unusual: "false"
+ swaccess: "ro",
+ desc: '''
+ Flash read FIFO.
+
+ The FIFO is 16 entries of 4B flash words
+ '''
+ },
+ },
+ ]
+}
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
new file mode 100644
index 0000000..8e3cccd
--- /dev/null
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
@@ -0,0 +1,761 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Flash Controller Module
+//
+//
+
+`include "prim_assert.sv"
+
+module flash_ctrl import flash_ctrl_pkg::*; (
+ input clk_i,
+ input rst_ni,
+
+ // Bus Interface
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+
+ // Flash Interface
+ input flash_rsp_t flash_i,
+ output flash_req_t flash_o,
+
+ // otp/lc/pwrmgr/keymgr Interface
+ input otp_flash_t otp_i,
+ input lc_flash_req_t lc_i,
+ output lc_flash_rsp_t lc_o,
+ input pwrmgr_pkg::pwr_flash_req_t pwrmgr_i,
+ output pwrmgr_pkg::pwr_flash_rsp_t pwrmgr_o,
+ input edn_entropy_t edn_i,
+ output keymgr_flash_t keymgr_o,
+
+ // Interrupts
+ output logic intr_prog_empty_o, // Program fifo is empty
+ output logic intr_prog_lvl_o, // Program fifo is empty
+ output logic intr_rd_full_o, // Read fifo is full
+ output logic intr_rd_lvl_o, // Read fifo is full
+ output logic intr_op_done_o, // Requested flash operation (wr/erase) done
+ output logic intr_op_error_o // Requested flash operation (wr/erase) done
+);
+
+ import flash_ctrl_reg_pkg::*;
+
+ flash_ctrl_reg2hw_t reg2hw;
+ flash_ctrl_hw2reg_t hw2reg;
+
+ tlul_pkg::tl_h2d_t tl_fifo_h2d [2];
+ tlul_pkg::tl_d2h_t tl_fifo_d2h [2];
+
+ // Register module
+ flash_ctrl_reg_top u_reg (
+ .clk_i,
+ .rst_ni,
+
+ .tl_i,
+ .tl_o,
+
+ .tl_win_o (tl_fifo_h2d),
+ .tl_win_i (tl_fifo_d2h),
+
+ .reg2hw,
+ .hw2reg,
+
+ .devmode_i (1'b1)
+ );
+
+ // FIFO Connections
+ logic prog_fifo_wvalid;
+ logic prog_fifo_wready;
+ logic prog_fifo_rvalid;
+ logic prog_fifo_ren;
+ logic [BusWidth-1:0] prog_fifo_wdata;
+ logic [BusWidth-1:0] prog_fifo_rdata;
+ logic [FifoDepthW-1:0] prog_fifo_depth;
+ logic rd_fifo_wready;
+ logic rd_fifo_rvalid;
+ logic rd_fifo_rready;
+ logic rd_fifo_wen;
+ logic rd_fifo_ren;
+ logic [BusWidth-1:0] rd_fifo_wdata;
+ logic [BusWidth-1:0] rd_fifo_rdata;
+ logic [FifoDepthW-1:0] rd_fifo_depth;
+
+ // Program Control Connections
+ logic prog_flash_req;
+ logic prog_flash_ovfl;
+ logic [BusAddrW-1:0] prog_flash_addr;
+ logic prog_op_valid;
+
+ // Read Control Connections
+ logic rd_flash_req;
+ logic rd_flash_ovfl;
+ logic [BusAddrW-1:0] rd_flash_addr;
+
+ // Erase Control Connections
+ logic erase_flash_req;
+ logic [BusAddrW-1:0] erase_flash_addr;
+ flash_erase_e erase_flash_type;
+
+ // Done / Error signaling from ctrl modules
+ logic prog_done, rd_done, erase_done;
+ logic prog_err, rd_err, erase_err;
+
+ // Flash Memory Protection Connections
+ logic [BusAddrW-1:0] flash_addr;
+ logic flash_req;
+ logic flash_rd_done, flash_prog_done, flash_erase_done;
+ logic flash_mp_error;
+ logic [BusWidth-1:0] flash_prog_data;
+ logic flash_prog_last;
+ flash_prog_e flash_prog_type;
+ logic [BusWidth-1:0] flash_rd_data;
+ logic flash_rd_err;
+ logic flash_phy_busy;
+ logic rd_op;
+ logic prog_op;
+ logic erase_op;
+ logic [AllPagesW-1:0] err_addr;
+ flash_lcmgr_phase_e phase;
+
+ // Flash control arbitration connections to hardware interface
+ flash_ctrl_reg2hw_control_reg_t hw_ctrl;
+ logic hw_req;
+ logic [top_pkg::TL_AW-1:0] hw_addr;
+ logic hw_done;
+ logic hw_err;
+ logic hw_rvalid;
+ logic hw_rready;
+ flash_sel_e if_sel;
+ logic sw_sel;
+ flash_lcmgr_phase_e hw_phase;
+ logic creator_seed_priv;
+ logic owner_seed_priv;
+
+ // Flash control arbitration connections to software interface
+ logic sw_ctrl_done;
+ logic sw_ctrl_err;
+
+ // Flash control muxed connections
+ flash_ctrl_reg2hw_control_reg_t muxed_ctrl;
+ logic [top_pkg::TL_AW-1:0] muxed_addr;
+ logic op_start;
+ logic [11:0] op_num_words;
+ logic [BusAddrW-1:0] op_addr;
+ flash_op_e op_type;
+ flash_part_e op_part;
+ logic [InfoTypesWidth-1:0] op_info_sel;
+ flash_erase_e op_erase_type;
+ flash_prog_e op_prog_type;
+
+ logic ctrl_init_busy;
+ logic fifo_clr;
+
+ // software tlul to flash control aribration
+ logic sw_rvalid;
+ logic adapter_rvalid;
+ logic sw_wvalid;
+ logic sw_wen;
+ logic sw_wready;
+
+ // lfsr for local entropy usage
+ logic [31:0] rand_val;
+ logic lfsr_en;
+
+ prim_lfsr #(
+ .DefaultSeed(),
+ .EntropyDw(4),
+ .LfsrDw(32),
+ .StateOutDw(32)
+ ) u_lfsr (
+ .clk_i,
+ .rst_ni,
+ .seed_en_i('0),
+ .seed_i('0),
+ .lfsr_en_i(lfsr_en),
+ .entropy_i(edn_i.valid ? edn_i.entropy : '0),
+ .state_o(rand_val)
+ );
+
+ // flash control arbitration between softawre / harware interfaces
+ flash_ctrl_arb u_ctrl_arb (
+ .clk_i,
+ .rst_ni,
+
+ // software interface to rd_ctrl / erase_ctrl
+ .sw_ctrl_i(reg2hw.control),
+ .sw_addr_i(reg2hw.addr.q),
+ .sw_ack_o(sw_ctrl_done),
+ .sw_err_o(sw_ctrl_err),
+
+ // software interface to rd_fifo
+ .sw_rvalid_o(sw_rvalid),
+ .sw_rready_i(adapter_rvalid),
+
+ // software interface to prog_fifo
+ .sw_wvalid_i(sw_wvalid & sw_wen),
+ .sw_wready_o(sw_wready),
+
+ // hardware interface to rd_ctrl / erase_ctrl
+ .hw_req_i(hw_req),
+ .hw_ctrl_i(hw_ctrl),
+
+ // hardware interface indicating operation phase
+ .hw_phase_i(hw_phase),
+
+ // hardware works on word address, however software expects byte address
+ .hw_addr_i(hw_addr),
+ .hw_ack_o(hw_done),
+ .hw_err_o(hw_err),
+
+ // hardware interface to rd_fifo
+ .hw_rvalid_o(hw_rvalid),
+ .hw_rready_i(hw_rready),
+
+ // hardware interface does not talk to prog_fifo
+
+ // muxed interface to rd_ctrl / erase_ctrl
+ .muxed_ctrl_o(muxed_ctrl),
+ .muxed_addr_o(muxed_addr),
+ .prog_ack_i(prog_done),
+ .prog_err_i(prog_err),
+ .rd_ack_i(rd_done),
+ .rd_err_i(rd_err),
+ .erase_ack_i(erase_done),
+ .erase_err_i(erase_err),
+
+ // muxed interface to rd_fifo
+ .rd_fifo_rvalid_i(rd_fifo_rvalid),
+ .rd_fifo_rready_o(rd_fifo_rready),
+
+ // muxed interface to prog_fifo
+ .prog_fifo_wvalid_o(prog_fifo_wvalid),
+ .prog_fifo_wready_i(prog_fifo_wready),
+
+ // flash phy initilization ongoing
+ .flash_phy_busy_i(flash_phy_busy),
+
+ // clear fifos
+ .fifo_clr_o(fifo_clr),
+
+ // phase indication
+ .phase_o(phase),
+
+ // indication that sw has been selected
+ .sel_o(if_sel),
+
+ // enable lfsr
+ .lfsr_en_o(lfsr_en)
+ );
+
+ assign op_start = muxed_ctrl.start.q;
+ assign op_num_words = muxed_ctrl.num.q;
+ assign op_erase_type = flash_erase_e'(muxed_ctrl.erase_sel.q);
+ assign op_prog_type = flash_prog_e'(muxed_ctrl.prog_sel.q);
+ assign op_addr = muxed_addr[BusByteWidth +: BusAddrW];
+ assign op_type = flash_op_e'(muxed_ctrl.op.q);
+ assign op_part = flash_part_e'(muxed_ctrl.partition_sel.q);
+ assign op_info_sel = muxed_ctrl.info_sel.q;
+ assign rd_op = op_type == FlashOpRead;
+ assign prog_op = op_type == FlashOpProgram;
+ assign erase_op = op_type == FlashOpErase;
+ assign sw_sel = if_sel == SwSel;
+
+ // hardware interface
+
+ // software only has privilege to change creator seed when provision enable is set and
+ // before the the seed is set as valid in otp
+ assign creator_seed_priv = lc_i.provision_en & ~otp_i.seed_valid;
+
+ // owner seed is under software control and can be modided whenever provision enable is set
+ assign owner_seed_priv = lc_i.provision_en;
+
+ flash_ctrl_lcmgr u_flash_hw_if (
+ .clk_i,
+ .rst_ni,
+
+ .init_i(pwrmgr_i.flash_init),
+ .init_done_o(pwrmgr_o.flash_done),
+ .provision_en_i(lc_i.provision_en),
+
+ // interface to ctrl arb control ports
+ .ctrl_o(hw_ctrl),
+ .req_o(hw_req),
+ .addr_o(hw_addr),
+ .done_i(hw_done),
+ .err_i(hw_err),
+
+ // interface to ctrl_arb data ports
+ .rready_o(hw_rready),
+ .rvalid_i(hw_rvalid),
+
+ // direct form rd_fifo
+ .rdata_i(rd_fifo_rdata),
+
+ // external rma request
+ .rma_i(lc_i.rma_req),
+ .rma_token_i(lc_i.rma_req_token),
+ .rma_token_o(lc_o.rma_ack_token),
+ .rma_rsp_o(lc_o.rma_ack),
+
+ // random value
+ .rand_i(rand_val),
+
+ // outgoing seeds
+ .seeds_o(keymgr_o.seeds),
+ .seed_err_o(), // TBD hook-up to Err code register
+
+ // phase indication
+ .phase_o(hw_phase),
+
+ // init ongoing
+ .init_busy_o(ctrl_init_busy)
+ );
+
+ // Program FIFO
+ // Since the program and read FIFOs are never used at the same time, it should really be one
+ // FIFO with muxed inputs and outputs. This should be addressed once the flash integration
+ // strategy has been identified
+ assign prog_op_valid = op_start & prog_op;
+
+ tlul_adapter_sram #(
+ .SramAw(1), //address unused
+ .SramDw(BusWidth),
+ .ByteAccess(0), //flash may not support byte access
+ .ErrOnRead(1) //reads not supported
+ ) u_to_prog_fifo (
+ .clk_i,
+ .rst_ni,
+ .tl_i (tl_fifo_h2d[0]),
+ .tl_o (tl_fifo_d2h[0]),
+ .req_o (sw_wvalid),
+ .gnt_i (sw_wready),
+ .we_o (sw_wen),
+ .addr_o (),
+ .wmask_o (),
+ .wdata_o (prog_fifo_wdata),
+ .rdata_i (BusWidth'(0)),
+ .rvalid_i (1'b0),
+ .rerror_i (2'b0)
+ );
+
+ prim_fifo_sync #(
+ .Width(BusWidth),
+ .Depth(FifoDepth)
+ ) u_prog_fifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (reg2hw.fifo_rst.q | fifo_clr),
+ .wvalid_i(prog_fifo_wvalid & prog_op_valid),
+ .wready_o(prog_fifo_wready),
+ .wdata_i (prog_fifo_wdata),
+ .depth_o (prog_fifo_depth),
+ .rvalid_o(prog_fifo_rvalid),
+ .rready_i(prog_fifo_ren),
+ .rdata_o (prog_fifo_rdata)
+ );
+
+ // Program handler is consumer of prog_fifo
+
+ // OTP control bits can be used to explicitly disable repair
+ logic [ProgTypes-1:0] otp_en;
+ assign otp_en[FlashProgNormal] = 1'b1;
+ assign otp_en[FlashProgRepair] = otp_i.prog_repair_en;
+
+ flash_ctrl_prog u_flash_ctrl_prog (
+ .clk_i,
+ .rst_ni,
+
+ // Control interface
+ .op_start_i (prog_op_valid),
+ .op_num_words_i (op_num_words),
+ .op_done_o (prog_done),
+ .op_err_o (prog_err),
+ .op_addr_i (op_addr),
+ .op_type_i (op_prog_type),
+ .type_avail_i (flash_i.prog_type_avail & otp_en),
+
+ // FIFO Interface
+ .data_i (prog_fifo_rdata),
+ .data_rdy_i (prog_fifo_rvalid),
+ .data_rd_o (prog_fifo_ren),
+
+ // Flash Macro Interface
+ .flash_req_o (prog_flash_req),
+ .flash_addr_o (prog_flash_addr),
+ .flash_ovfl_o (prog_flash_ovfl),
+ .flash_data_o (flash_prog_data),
+ .flash_last_o (flash_prog_last),
+ .flash_type_o (flash_prog_type),
+ .flash_done_i (flash_prog_done),
+ .flash_error_i (flash_mp_error)
+ );
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ adapter_rvalid <= 1'b0;
+ end else begin
+ adapter_rvalid <= rd_fifo_ren && sw_rvalid;
+ end
+ end
+
+ // tlul adapter represents software's access interface to flash
+ tlul_adapter_sram #(
+ .SramAw(1), //address unused
+ .SramDw(BusWidth),
+ .ByteAccess(0), //flash may not support byte access
+ .ErrOnWrite(1) //writes not supported
+ ) u_to_rd_fifo (
+ .clk_i,
+ .rst_ni,
+ .tl_i (tl_fifo_h2d[1]),
+ .tl_o (tl_fifo_d2h[1]),
+ .req_o (rd_fifo_ren),
+ .gnt_i (rd_fifo_rvalid),
+ .we_o (),
+ .addr_o (),
+ .wmask_o (),
+ .wdata_o (),
+ .rdata_i (rd_fifo_rdata),
+ .rvalid_i (adapter_rvalid),
+ .rerror_i (2'b0)
+ );
+
+ prim_fifo_sync #(
+ .Width(BusWidth),
+ .Depth(FifoDepth)
+ ) u_rd_fifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (reg2hw.fifo_rst.q | fifo_clr),
+ .wvalid_i(rd_fifo_wen),
+ .wready_o(rd_fifo_wready),
+ .wdata_i (rd_fifo_wdata),
+ .depth_o (rd_fifo_depth),
+ .rvalid_o(rd_fifo_rvalid),
+ .rready_i(rd_fifo_rready),
+ .rdata_o (rd_fifo_rdata)
+ );
+
+ // Read handler is consumer of rd_fifo
+ flash_ctrl_rd u_flash_ctrl_rd (
+ .clk_i,
+ .rst_ni,
+
+ // To arbiter Interface
+ .op_start_i (op_start & rd_op),
+ .op_num_words_i (op_num_words),
+ .op_done_o (rd_done),
+ .op_err_o (rd_err),
+ .op_addr_i (op_addr),
+
+ // FIFO Interface
+ .data_rdy_i (rd_fifo_wready),
+ .data_o (rd_fifo_wdata),
+ .data_wr_o (rd_fifo_wen),
+
+ // Flash Macro Interface
+ .flash_req_o (rd_flash_req),
+ .flash_addr_o (rd_flash_addr),
+ .flash_ovfl_o (rd_flash_ovfl),
+ .flash_data_i (flash_rd_data),
+ .flash_done_i (flash_rd_done),
+ .flash_error_i (flash_mp_error | flash_rd_err)
+ );
+
+ // Erase handler does not consume fifo
+ flash_ctrl_erase u_flash_ctrl_erase (
+ // Software Interface
+ .op_start_i (op_start & erase_op),
+ .op_type_i (op_erase_type),
+ .op_done_o (erase_done),
+ .op_err_o (erase_err),
+ .op_addr_i (op_addr),
+
+ // Flash Macro Interface
+ .flash_req_o (erase_flash_req),
+ .flash_addr_o (erase_flash_addr),
+ .flash_op_o (erase_flash_type),
+ .flash_done_i (flash_erase_done),
+ .flash_error_i (flash_mp_error)
+ );
+
+ // Final muxing to flash macro module
+ always_comb begin
+ unique case (op_type)
+ FlashOpRead: begin
+ flash_req = rd_flash_req;
+ flash_addr = rd_flash_addr;
+ end
+ FlashOpProgram: begin
+ flash_req = prog_flash_req;
+ flash_addr = prog_flash_addr;
+ end
+ FlashOpErase: begin
+ flash_req = erase_flash_req;
+ flash_addr = erase_flash_addr;
+ end
+ default: begin
+ flash_req = 1'b0;
+ flash_addr = '0;
+ end
+ endcase // unique case (op_type)
+ end
+
+ //////////////////////////////////////
+ // Data partition protection configuration
+ //////////////////////////////////////
+ // extra region is the default region
+ mp_region_cfg_t [MpRegions:0] region_cfgs;
+ assign region_cfgs[MpRegions-1:0] = reg2hw.mp_region_cfg[MpRegions-1:0];
+
+ //default region
+ assign region_cfgs[MpRegions].base.q = '0;
+ assign region_cfgs[MpRegions].size.q = NumBanks * PagesPerBank;
+ assign region_cfgs[MpRegions].en.q = 1'b1;
+ assign region_cfgs[MpRegions].rd_en.q = reg2hw.default_region.rd_en.q;
+ assign region_cfgs[MpRegions].prog_en.q = reg2hw.default_region.prog_en.q;
+ assign region_cfgs[MpRegions].erase_en.q = reg2hw.default_region.erase_en.q;
+ assign region_cfgs[MpRegions].scramble_en.q = reg2hw.default_region.scramble_en.q;
+
+ //////////////////////////////////////
+ // Info partition protection configuration
+ //////////////////////////////////////
+ info_page_cfg_t [NumBanks-1:0][InfoTypes-1:0][InfosPerBank-1:0] reg2hw_info_page_cfgs;
+ info_page_cfg_t [NumBanks-1:0][InfoTypes-1:0][InfosPerBank-1:0] info_page_cfgs;
+
+ // transform from reg output to structure
+ assign reg2hw_info_page_cfgs[0][0] = reg2hw.bank0_info0_page_cfg;
+ assign reg2hw_info_page_cfgs[0][1] = reg2hw.bank0_info1_page_cfg;
+ assign reg2hw_info_page_cfgs[1][0] = reg2hw.bank1_info0_page_cfg;
+ assign reg2hw_info_page_cfgs[1][1] = reg2hw.bank1_info1_page_cfg;
+
+ // qualify reg2hw settings with creator / owner privileges
+ for(genvar i = 0; i < NumBanks; i++) begin : gen_info_priv_bank
+ for (genvar j = 0; j < InfoTypes; j++) begin : gen_info_priv_type
+ flash_ctrl_info_cfg # (
+ .Bank(i),
+ .InfoSel(j)
+ ) u_info_cfg (
+ .cfgs_i(reg2hw_info_page_cfgs[i][j]),
+ .creator_seed_priv_i(creator_seed_priv),
+ .owner_seed_priv_i(owner_seed_priv),
+ .cfgs_o(info_page_cfgs[i][j])
+ );
+ end
+ end
+
+ //////////////////////////////////////
+ // flash memory protection
+ //////////////////////////////////////
+ // direct assignment since prog/rd/erase_ctrl do not make use of op_part
+ flash_part_e flash_part_sel;
+ logic [InfoTypesWidth-1:0] flash_info_sel;
+ assign flash_part_sel = op_part;
+ assign flash_info_sel = op_info_sel;
+
+ // Flash memory protection
+ // Memory protection is page based and thus should use phy addressing
+ // This should move to flash_phy long term
+ flash_mp u_flash_mp (
+ .clk_i,
+ .rst_ni,
+
+ // arbiter interface selection
+ .if_sel_i(if_sel),
+
+ // sw configuration for data partition
+ .region_cfgs_i(region_cfgs),
+ .bank_cfgs_i(reg2hw.mp_bank_cfg),
+
+ // sw configuration for info partition
+ .info_page_cfgs_i(info_page_cfgs),
+
+ // read / prog / erase controls
+ .req_i(flash_req),
+ .phase_i(phase),
+ .req_addr_i(flash_addr[BusAddrW-1 -: AllPagesW]),
+ .req_part_i(flash_part_sel),
+ .info_sel_i(flash_info_sel),
+ .addr_ovfl_i(rd_flash_ovfl | prog_flash_ovfl),
+ .rd_i(rd_op),
+ .prog_i(prog_op),
+ .pg_erase_i(erase_op & (erase_flash_type == FlashErasePage)),
+ .bk_erase_i(erase_op & (erase_flash_type == FlashEraseBank)),
+ .rd_done_o(flash_rd_done),
+ .prog_done_o(flash_prog_done),
+ .erase_done_o(flash_erase_done),
+ .error_o(flash_mp_error),
+ .err_addr_o(err_addr),
+
+ // flash phy interface
+ .req_o(flash_o.req),
+ .scramble_en_o(flash_o.scramble_en),
+ .rd_o(flash_o.rd),
+ .prog_o(flash_o.prog),
+ .pg_erase_o(flash_o.pg_erase),
+ .bk_erase_o(flash_o.bk_erase),
+ .rd_done_i(flash_i.rd_done),
+ .prog_done_i(flash_i.prog_done),
+ .erase_done_i(flash_i.erase_done)
+ );
+
+
+ // software interface feedback
+ // most values (other than flash_phy_busy) should only update when software operations
+ // are actually selected
+ assign hw2reg.op_status.done.d = 1'b1;
+ assign hw2reg.op_status.done.de = sw_ctrl_done;
+ assign hw2reg.op_status.err.d = 1'b1;
+ assign hw2reg.op_status.err.de = sw_ctrl_err;
+ assign hw2reg.status.rd_full.d = ~rd_fifo_wready;
+ assign hw2reg.status.rd_full.de = sw_sel;
+ assign hw2reg.status.rd_empty.d = ~rd_fifo_rvalid;
+ assign hw2reg.status.rd_empty.de = sw_sel;
+ assign hw2reg.status.prog_full.d = ~prog_fifo_wready;
+ assign hw2reg.status.prog_full.de = sw_sel;
+ assign hw2reg.status.prog_empty.d = ~prog_fifo_rvalid;
+ assign hw2reg.status.prog_empty.de = sw_sel;
+ assign hw2reg.status.init_wip.d = flash_phy_busy | ctrl_init_busy;
+ assign hw2reg.status.init_wip.de = 1'b1;
+ assign hw2reg.status.error_addr.d = err_addr;
+ assign hw2reg.status.error_addr.de = sw_sel;
+ assign hw2reg.control.start.d = 1'b0;
+ assign hw2reg.control.start.de = sw_ctrl_done;
+ // if software operation selected, based on transaction start
+ // if software operation not selected, software is free to change contents
+ assign hw2reg.ctrl_regwen.d = sw_sel ? !op_start : 1'b1;
+
+ // phy status
+ assign hw2reg.phy_status.init_wip.d = flash_phy_busy;
+ assign hw2reg.phy_status.init_wip.de = 1'b1;
+ assign hw2reg.phy_status.prog_normal_avail.d = flash_i.prog_type_avail[FlashProgNormal];
+ assign hw2reg.phy_status.prog_normal_avail.de = 1'b1;
+ assign hw2reg.phy_status.prog_repair_avail.d = flash_i.prog_type_avail[FlashProgRepair];
+ assign hw2reg.phy_status.prog_repair_avail.de = 1'b1;
+
+ // Flash Interface
+ assign flash_o.addr = flash_addr;
+ assign flash_o.part = flash_part_sel;
+ assign flash_o.prog_type = flash_prog_type;
+ assign flash_o.prog_data = flash_prog_data;
+ assign flash_o.prog_last = flash_prog_last;
+ assign flash_o.region_cfgs = region_cfgs;
+ assign flash_o.addr_key = otp_i.addr_key;
+ assign flash_o.data_key = otp_i.data_key;
+ assign flash_rd_err = flash_i.rd_err;
+ assign flash_rd_data = flash_i.rd_data;
+ assign flash_phy_busy = flash_i.init_busy;
+
+ // Interface to pwrmgr
+ // flash is not idle as long as there is a stateful operation ongoing
+ logic flash_idle_d;
+ assign flash_idle_d = ~(flash_o.req &
+ (flash_o.prog | flash_o.pg_erase | flash_o.bk_erase));
+
+ prim_flop #(
+ .Width(1),
+ .ResetValue(1'b1)
+ ) u_reg_idle (
+ .clk_i,
+ .rst_ni,
+ .d_i(flash_idle_d),
+ .q_o(pwrmgr_o.flash_idle)
+ );
+
+
+ // Interrupts
+ // Generate edge triggered signals for sources that are level
+ logic [3:0] intr_src;
+ logic [3:0] intr_src_q;
+ logic [3:0] intr_assert;
+
+ assign intr_src = { ~prog_fifo_rvalid,
+ reg2hw.fifo_lvl.prog.q == prog_fifo_depth,
+ ~rd_fifo_wready,
+ reg2hw.fifo_lvl.rd.q == rd_fifo_depth
+ };
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intr_src_q <= 4'h8; //prog_fifo is empty by default
+ end else if (sw_sel) begin
+ intr_src_q <= intr_src;
+ end
+ end
+
+ assign intr_assert = ~intr_src_q & intr_src;
+
+
+ assign intr_prog_empty_o = reg2hw.intr_enable.prog_empty.q & reg2hw.intr_state.prog_empty.q;
+ assign intr_prog_lvl_o = reg2hw.intr_enable.prog_lvl.q & reg2hw.intr_state.prog_lvl.q;
+ assign intr_rd_full_o = reg2hw.intr_enable.rd_full.q & reg2hw.intr_state.rd_full.q;
+ assign intr_rd_lvl_o = reg2hw.intr_enable.rd_lvl.q & reg2hw.intr_state.rd_lvl.q;
+ assign intr_op_done_o = reg2hw.intr_enable.op_done.q & reg2hw.intr_state.op_done.q;
+ assign intr_op_error_o = reg2hw.intr_enable.op_error.q & reg2hw.intr_state.op_error.q;
+
+ assign hw2reg.intr_state.prog_empty.d = 1'b1;
+ assign hw2reg.intr_state.prog_empty.de = intr_assert[3] |
+ (reg2hw.intr_test.prog_empty.qe &
+ reg2hw.intr_test.prog_empty.q);
+
+ assign hw2reg.intr_state.prog_lvl.d = 1'b1;
+ assign hw2reg.intr_state.prog_lvl.de = intr_assert[2] |
+ (reg2hw.intr_test.prog_lvl.qe &
+ reg2hw.intr_test.prog_lvl.q);
+
+ assign hw2reg.intr_state.rd_full.d = 1'b1;
+ assign hw2reg.intr_state.rd_full.de = intr_assert[1] |
+ (reg2hw.intr_test.rd_full.qe &
+ reg2hw.intr_test.rd_full.q);
+
+ assign hw2reg.intr_state.rd_lvl.d = 1'b1;
+ assign hw2reg.intr_state.rd_lvl.de = intr_assert[0] |
+ (reg2hw.intr_test.rd_lvl.qe &
+ reg2hw.intr_test.rd_lvl.q);
+
+
+ assign hw2reg.intr_state.op_done.d = 1'b1;
+ assign hw2reg.intr_state.op_done.de = sw_ctrl_done |
+ (reg2hw.intr_test.op_done.qe &
+ reg2hw.intr_test.op_done.q);
+
+ assign hw2reg.intr_state.op_error.d = 1'b1;
+ assign hw2reg.intr_state.op_error.de = sw_ctrl_err |
+ (reg2hw.intr_test.op_error.qe &
+ reg2hw.intr_test.op_error.q);
+
+
+
+ // Unused bits
+ logic [BusByteWidth-1:0] unused_byte_sel;
+ logic [top_pkg::TL_AW-1-BusAddrW:0] unused_higher_addr_bits;
+ logic [top_pkg::TL_AW-1:0] unused_scratch;
+
+
+ // Unused signals
+ assign unused_byte_sel = muxed_addr[BusByteWidth-1:0];
+ assign unused_higher_addr_bits = muxed_addr[top_pkg::TL_AW-1:BusAddrW];
+ assign unused_scratch = reg2hw.scratch;
+
+
+ // Assertions
+ `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid )
+ `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready )
+ `ASSERT_KNOWN(FlashKnownO_A, {flash_o.req, flash_o.rd, flash_o.prog, flash_o.pg_erase,
+ flash_o.bk_erase})
+ `ASSERT_KNOWN_IF(FlashAddrKnown_A, flash_o.addr, flash_o.req)
+ `ASSERT_KNOWN_IF(FlashProgKnown_A, flash_o.prog_data, flash_o.prog & flash_o.req)
+ `ASSERT_KNOWN(IntrProgEmptyKnownO_A, intr_prog_empty_o)
+ `ASSERT_KNOWN(IntrProgLvlKnownO_A, intr_prog_lvl_o )
+ `ASSERT_KNOWN(IntrProgRdFullKnownO_A, intr_rd_full_o )
+ `ASSERT_KNOWN(IntrRdLvlKnownO_A, intr_rd_lvl_o )
+ `ASSERT_KNOWN(IntrOpDoneKnownO_A, intr_op_done_o )
+ `ASSERT_KNOWN(IntrOpErrorKnownO_A, intr_op_error_o )
+
+endmodule
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv
new file mode 100644
index 0000000..cef3d82
--- /dev/null
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv
@@ -0,0 +1,363 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Flash Controller module.
+//
+
+package flash_ctrl_pkg;
+
+ // design parameters that can be altered through topgen
+ parameter int NumBanks = flash_ctrl_reg_pkg::RegNumBanks;
+ parameter int PagesPerBank = flash_ctrl_reg_pkg::RegPagesPerBank;
+
+ // fixed parameters of flash derived from topgen parameters
+ parameter int DataWidth = 64;
+ parameter int MetaDataWidth = 12;
+ parameter int InfoTypes = 2; // How many types of info per bank
+
+// The following hard-wired values are there to work-around verilator.
+// For some reason if the values are assigned through parameters verilator thinks
+// they are not constant
+ parameter int InfoTypeSize [InfoTypes] = '{
+ 4,
+ 4
+ };
+ parameter int InfosPerBank = max_info_pages('{
+ 4,
+ 4
+ });
+ parameter int WordsPerPage = 128; // Number of flash words per page
+ parameter int BusWidth = top_pkg::TL_DW;
+ parameter int MpRegions = 8; // flash controller protection regions
+ parameter int FifoDepth = 16; // rd / prog fifos
+ parameter int InfoTypesWidth = prim_util_pkg::vbits(InfoTypes);
+
+ // flash phy parameters
+ parameter int DataByteWidth = prim_util_pkg::vbits(DataWidth / 8);
+ parameter int BankW = prim_util_pkg::vbits(NumBanks);
+ parameter int InfoPageW = prim_util_pkg::vbits(InfosPerBank);
+ parameter int PageW = prim_util_pkg::vbits(PagesPerBank);
+ parameter int WordW = prim_util_pkg::vbits(WordsPerPage);
+ parameter int AddrW = BankW + PageW + WordW; // all flash range
+ parameter int BankAddrW = PageW + WordW; // 1 bank of flash range
+ parameter int AllPagesW = BankW + PageW;
+
+ // flash ctrl / bus parameters
+ // flash / bus width may be different from actual flash word width
+ parameter int BusByteWidth = prim_util_pkg::vbits(BusWidth / 8);
+ parameter int WidthMultiple = DataWidth / BusWidth;
+ parameter int BusWordsPerPage = WordsPerPage * WidthMultiple;
+ parameter int BusWordW = prim_util_pkg::vbits(BusWordsPerPage);
+ parameter int BusAddrW = BankW + PageW + BusWordW;
+ parameter int BusBankAddrW = PageW + BusWordW;
+ parameter int PhyAddrStart = BusWordW - WordW;
+
+ // fifo parameters
+ parameter int FifoDepthW = prim_util_pkg::vbits(FifoDepth+1);
+
+ // The end address in bus words for each kind of partition in each bank
+ parameter logic [PageW-1:0] DataPartitionEndAddr = PagesPerBank - 1;
+ parameter logic [PageW-1:0] InfoPartitionEndAddr [InfoTypes] = '{
+ InfoTypeSize[0] - 1,
+ InfoTypeSize[1] - 1
+ };
+
+ ////////////////////////////
+ // All memory protection, seed related parameters
+ // Those related for seed pages should be template candidates
+ ////////////////////////////
+
+ // parameters for connected components
+ parameter int SeedWidth = 256;
+
+ // lcmgr phase enum
+ typedef enum logic [1:0] {
+ PhaseSeed,
+ PhaseRma,
+ PhaseNone,
+ PhaseInvalid
+ } flash_lcmgr_phase_e;
+
+ // alias for super long reg_pkg typedef
+ typedef flash_ctrl_reg_pkg::flash_ctrl_reg2hw_bank0_info0_page_cfg_mreg_t info_page_cfg_t;
+ typedef flash_ctrl_reg_pkg::flash_ctrl_reg2hw_mp_region_cfg_mreg_t mp_region_cfg_t;
+
+ // memory protection specific structs
+ typedef struct packed {
+ logic [InfoTypesWidth-1:0] sel;
+ logic [AllPagesW-1:0] addr;
+ } page_addr_t;
+
+ typedef struct packed {
+ page_addr_t page;
+ flash_lcmgr_phase_e phase;
+ info_page_cfg_t cfg;
+ } info_page_attr_t;
+
+ typedef struct packed {
+ flash_lcmgr_phase_e phase;
+ mp_region_cfg_t cfg;
+ } data_region_attr_t;
+
+ // flash life cycle / key manager management constants
+ // One page for creator seeds
+ // One page for owner seeds
+ parameter int NumSeeds = 2;
+ parameter int SeedBank = 0;
+ parameter int SeedInfoSel = 0;
+ parameter int CreatorSeedIdx = 0;
+ parameter int OwnerSeedIdx = 1;
+ parameter int CreatorInfoPage = 1;
+ parameter int OwnerInfoPage = 2;
+
+ // which page of which info type of which bank
+ parameter page_addr_t SeedInfoPageSel [NumSeeds] = '{
+ '{
+ sel: SeedInfoSel,
+ addr: {SeedBank, CreatorInfoPage}
+ },
+
+ '{
+ sel: SeedInfoSel,
+ addr: {SeedBank, OwnerInfoPage}
+ }
+ };
+
+ // hardware interface memory protection rules
+ parameter int HwInfoRules = 3;
+ parameter int HwDataRules = 1;
+
+ parameter info_page_cfg_t CfgAllowRead = '{
+ en: 1'b1,
+ rd_en: 1'b1,
+ prog_en: 1'b0,
+ erase_en: 1'b0,
+ scramble_en: 1'b0 // TBD, update to 1 once tb supports ECC
+ };
+
+ parameter info_page_cfg_t CfgAllowReadErase = '{
+ en: 1'b1,
+ rd_en: 1'b1,
+ prog_en: 1'b0,
+ erase_en: 1'b1,
+ scramble_en: 1'b0 // TBD, update to 1 once tb supports ECC
+ };
+
+ parameter info_page_attr_t HwInfoPageAttr[HwInfoRules] = '{
+ '{
+ page: SeedInfoPageSel[CreatorSeedIdx],
+ phase: PhaseSeed,
+ cfg: CfgAllowRead
+ },
+
+ '{
+ page: SeedInfoPageSel[OwnerSeedIdx],
+ phase: PhaseSeed,
+ cfg: CfgAllowRead
+ },
+
+ '{
+ page: SeedInfoPageSel[OwnerSeedIdx],
+ phase: PhaseRma,
+ cfg: CfgAllowReadErase
+ }
+ };
+
+ parameter data_region_attr_t HwDataAttr[HwDataRules] = '{
+ '{
+ phase: PhaseRma,
+ cfg: '{
+ en: 1'b1,
+ rd_en: 1'b1,
+ prog_en: 1'b0,
+ erase_en: 1'b1,
+ scramble_en: 1'b0,
+ base: '0,
+ size: '{default:'1}
+ }
+ }
+ };
+
+
+ ////////////////////////////
+ // Flash operation related enums
+ ////////////////////////////
+
+ // Flash Operations Supported
+ typedef enum logic [1:0] {
+ FlashOpRead = 2'h0,
+ FlashOpProgram = 2'h1,
+ FlashOpErase = 2'h2,
+ FlashOpInvalid = 2'h3
+ } flash_op_e;
+
+ // Flash Program Operations Supported
+ typedef enum logic {
+ FlashProgNormal = 0,
+ FlashProgRepair = 1
+ } flash_prog_e;
+ parameter int ProgTypes = 2;
+
+ // Flash Erase Operations Supported
+ typedef enum logic {
+ FlashErasePage = 0,
+ FlashEraseBank = 1
+ } flash_erase_e;
+
+ // Flash function select
+ typedef enum logic [1:0] {
+ NoneSel,
+ SwSel,
+ HwSel
+ } flash_sel_e;
+
+ // Flash tlul to fifo direction
+ typedef enum logic {
+ WriteDir = 1'b0,
+ ReadDir = 1'b1
+ } flash_flfo_dir_e;
+
+ // Flash partition type
+ typedef enum logic {
+ FlashPartData = 1'b0,
+ FlashPartInfo = 1'b1
+ } flash_part_e;
+
+ // Flash controller to memory
+ typedef struct packed {
+ logic req;
+ logic scramble_en;
+ logic rd;
+ logic prog;
+ logic pg_erase;
+ logic bk_erase;
+ flash_part_e part;
+ logic [BusAddrW-1:0] addr;
+ logic [BusWidth-1:0] prog_data;
+ logic prog_last;
+ flash_prog_e prog_type;
+ mp_region_cfg_t [MpRegions:0] region_cfgs;
+ logic [127:0] addr_key;
+ logic [127:0] data_key;
+ } flash_req_t;
+
+ // default value of flash_req_t (for dangling ports)
+ parameter flash_req_t FLASH_REQ_DEFAULT = '{
+ req: 1'b0,
+ scramble_en: 1'b0,
+ rd: 1'b0,
+ prog: 1'b0,
+ pg_erase: 1'b0,
+ bk_erase: 1'b0,
+ part: FlashPartData,
+ addr: '0,
+ prog_data: '0,
+ prog_last: '0,
+ prog_type: FlashProgNormal,
+ region_cfgs: '0,
+ addr_key: 128'hDEADBEEFBEEFFACEDEADBEEF5A5AA5A5,
+ data_key: 128'hDEADBEEF5A5AA5A5DEADBEEFBEEFFACE
+ };
+
+ // memory to flash controller
+ typedef struct packed {
+ logic [ProgTypes-1:0] prog_type_avail;
+ logic rd_done;
+ logic prog_done;
+ logic erase_done;
+ logic rd_err;
+ logic [BusWidth-1:0] rd_data;
+ logic init_busy;
+ } flash_rsp_t;
+
+ // default value of flash_rsp_t (for dangling ports)
+ parameter flash_rsp_t FLASH_RSP_DEFAULT = '{
+ prog_type_avail: '{default: '1},
+ rd_done: 1'b0,
+ prog_done: 1'b0,
+ erase_done: 1'b0,
+ rd_err: '0,
+ rd_data: '0,
+ init_busy: 1'b0
+ };
+
+ ////////////////////////////
+ // The following inter-module should be moved to OTP/LC
+ ////////////////////////////
+
+ // otp to flash_ctrl
+ typedef struct packed {
+ logic [127:0] addr_key;
+ logic [127:0] data_key;
+ // TBD: this signal will become multi-bit in the future
+ logic seed_valid;
+ logic prog_repair_en;
+ } otp_flash_t;
+
+ // lc to flash_ctrl
+ typedef struct packed {
+ // TBD: this signal will become multi-bit in the future
+ logic rma_req;
+ logic [BusWidth-1:0] rma_req_token;
+ logic provision_en;
+ } lc_flash_req_t;
+
+ // flash_ctrl to lc
+ typedef struct packed {
+ logic rma_ack;
+ logic [BusWidth-1:0] rma_ack_token;
+ } lc_flash_rsp_t;
+
+ // flash_ctrl to keymgr
+ typedef struct packed {
+ logic [NumSeeds-1:0][SeedWidth-1:0] seeds;
+ } keymgr_flash_t;
+
+ // place holder for interface to EDN, replace with real one later
+ typedef struct packed {
+ logic valid;
+ logic [3:0] entropy;
+ } edn_entropy_t;
+
+ // default value of otp_flash_t
+ // These are hardwired default values that should never be used.
+ // Real values are individualized and supplied from OTP.
+ parameter otp_flash_t OTP_FLASH_DEFAULT = '{
+ addr_key: 128'hDEADBEEFBEEFFACEDEADBEEF5A5AA5A5,
+ data_key: 128'hDEADBEEF5A5AA5A5DEADBEEFBEEFFACE,
+ seed_valid: 1'b1,
+ prog_repair_en: 1'b1
+ };
+
+ parameter lc_flash_req_t LC_FLASH_REQ_DEFAULT = '{
+ rma_req: 1'b0,
+ rma_req_token: '0,
+ provision_en: 1'b1
+ };
+
+ parameter edn_entropy_t EDN_ENTROPY_DEFAULT = '{
+ valid: 1'b1,
+ entropy: '0
+ };
+
+
+ // find the max number pages among info types
+ function automatic integer max_info_pages(int infos[InfoTypes]);
+ int current_max = 0;
+ for (int i = 0; i < InfoTypes; i++) begin
+ if (infos[i] > current_max) begin
+ current_max = infos[i];
+ end
+ end
+ return current_max;
+ endfunction // max_info_banks
+
+
+endpackage : flash_ctrl_pkg
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
new file mode 100644
index 0000000..0b1c4ea
--- /dev/null
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
@@ -0,0 +1,583 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package flash_ctrl_reg_pkg;
+
+ // Param list
+ parameter int RegNumBanks = 2;
+ parameter int RegPagesPerBank = 256;
+ parameter int NumRegions = 8;
+ parameter int NumInfos0 = 4;
+ parameter int NumInfos1 = 4;
+ parameter int WordsPerPage = 128;
+ parameter int BytesPerWord = 8;
+ parameter int BytesPerPage = 1024;
+ parameter int BytesPerBank = 262144;
+
+ ////////////////////////////
+ // Typedefs for registers //
+ ////////////////////////////
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } prog_empty;
+ struct packed {
+ logic q;
+ } prog_lvl;
+ struct packed {
+ logic q;
+ } rd_full;
+ struct packed {
+ logic q;
+ } rd_lvl;
+ struct packed {
+ logic q;
+ } op_done;
+ struct packed {
+ logic q;
+ } op_error;
+ } flash_ctrl_reg2hw_intr_state_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } prog_empty;
+ struct packed {
+ logic q;
+ } prog_lvl;
+ struct packed {
+ logic q;
+ } rd_full;
+ struct packed {
+ logic q;
+ } rd_lvl;
+ struct packed {
+ logic q;
+ } op_done;
+ struct packed {
+ logic q;
+ } op_error;
+ } flash_ctrl_reg2hw_intr_enable_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } prog_empty;
+ struct packed {
+ logic q;
+ logic qe;
+ } prog_lvl;
+ struct packed {
+ logic q;
+ logic qe;
+ } rd_full;
+ struct packed {
+ logic q;
+ logic qe;
+ } rd_lvl;
+ struct packed {
+ logic q;
+ logic qe;
+ } op_done;
+ struct packed {
+ logic q;
+ logic qe;
+ } op_error;
+ } flash_ctrl_reg2hw_intr_test_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } start;
+ struct packed {
+ logic [1:0] q;
+ } op;
+ struct packed {
+ logic q;
+ } prog_sel;
+ struct packed {
+ logic q;
+ } erase_sel;
+ struct packed {
+ logic q;
+ } partition_sel;
+ struct packed {
+ logic q;
+ } info_sel;
+ struct packed {
+ logic [11:0] q;
+ } num;
+ } flash_ctrl_reg2hw_control_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } flash_ctrl_reg2hw_addr_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } en;
+ struct packed {
+ logic q;
+ } rd_en;
+ struct packed {
+ logic q;
+ } prog_en;
+ struct packed {
+ logic q;
+ } erase_en;
+ struct packed {
+ logic q;
+ } scramble_en;
+ struct packed {
+ logic [8:0] q;
+ } base;
+ struct packed {
+ logic [9:0] q;
+ } size;
+ } flash_ctrl_reg2hw_mp_region_cfg_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } rd_en;
+ struct packed {
+ logic q;
+ } prog_en;
+ struct packed {
+ logic q;
+ } erase_en;
+ struct packed {
+ logic q;
+ } scramble_en;
+ } flash_ctrl_reg2hw_default_region_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } en;
+ struct packed {
+ logic q;
+ } rd_en;
+ struct packed {
+ logic q;
+ } prog_en;
+ struct packed {
+ logic q;
+ } erase_en;
+ struct packed {
+ logic q;
+ } scramble_en;
+ } flash_ctrl_reg2hw_bank0_info0_page_cfg_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } en;
+ struct packed {
+ logic q;
+ } rd_en;
+ struct packed {
+ logic q;
+ } prog_en;
+ struct packed {
+ logic q;
+ } erase_en;
+ struct packed {
+ logic q;
+ } scramble_en;
+ } flash_ctrl_reg2hw_bank0_info1_page_cfg_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } en;
+ struct packed {
+ logic q;
+ } rd_en;
+ struct packed {
+ logic q;
+ } prog_en;
+ struct packed {
+ logic q;
+ } erase_en;
+ struct packed {
+ logic q;
+ } scramble_en;
+ } flash_ctrl_reg2hw_bank1_info0_page_cfg_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } en;
+ struct packed {
+ logic q;
+ } rd_en;
+ struct packed {
+ logic q;
+ } prog_en;
+ struct packed {
+ logic q;
+ } erase_en;
+ struct packed {
+ logic q;
+ } scramble_en;
+ } flash_ctrl_reg2hw_bank1_info1_page_cfg_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } flash_ctrl_reg2hw_mp_bank_cfg_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } flash_ctrl_reg2hw_scratch_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [4:0] q;
+ } prog;
+ struct packed {
+ logic [4:0] q;
+ } rd;
+ } flash_ctrl_reg2hw_fifo_lvl_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } flash_ctrl_reg2hw_fifo_rst_reg_t;
+
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } prog_empty;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_lvl;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_full;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_lvl;
+ struct packed {
+ logic d;
+ logic de;
+ } op_done;
+ struct packed {
+ logic d;
+ logic de;
+ } op_error;
+ } flash_ctrl_hw2reg_intr_state_reg_t;
+
+ typedef struct packed {
+ logic d;
+ } flash_ctrl_hw2reg_ctrl_regwen_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } start;
+ } flash_ctrl_hw2reg_control_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } done;
+ struct packed {
+ logic d;
+ logic de;
+ } err;
+ } flash_ctrl_hw2reg_op_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } rd_full;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_empty;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_full;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_empty;
+ struct packed {
+ logic d;
+ logic de;
+ } init_wip;
+ struct packed {
+ logic [8:0] d;
+ logic de;
+ } error_addr;
+ } flash_ctrl_hw2reg_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } init_wip;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_normal_avail;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_repair_avail;
+ } flash_ctrl_hw2reg_phy_status_reg_t;
+
+
+ ///////////////////////////////////////
+ // Register to internal design logic //
+ ///////////////////////////////////////
+ typedef struct packed {
+ flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [395:390]
+ flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [389:384]
+ flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [383:372]
+ flash_ctrl_reg2hw_control_reg_t control; // [371:353]
+ flash_ctrl_reg2hw_addr_reg_t addr; // [352:321]
+ flash_ctrl_reg2hw_mp_region_cfg_mreg_t [7:0] mp_region_cfg; // [320:129]
+ flash_ctrl_reg2hw_default_region_reg_t default_region; // [128:125]
+ flash_ctrl_reg2hw_bank0_info0_page_cfg_mreg_t [3:0] bank0_info0_page_cfg; // [124:105]
+ flash_ctrl_reg2hw_bank0_info1_page_cfg_mreg_t [3:0] bank0_info1_page_cfg; // [104:85]
+ flash_ctrl_reg2hw_bank1_info0_page_cfg_mreg_t [3:0] bank1_info0_page_cfg; // [84:65]
+ flash_ctrl_reg2hw_bank1_info1_page_cfg_mreg_t [3:0] bank1_info1_page_cfg; // [64:45]
+ flash_ctrl_reg2hw_mp_bank_cfg_mreg_t [1:0] mp_bank_cfg; // [44:43]
+ flash_ctrl_reg2hw_scratch_reg_t scratch; // [42:11]
+ flash_ctrl_reg2hw_fifo_lvl_reg_t fifo_lvl; // [10:1]
+ flash_ctrl_reg2hw_fifo_rst_reg_t fifo_rst; // [0:0]
+ } flash_ctrl_reg2hw_t;
+
+ ///////////////////////////////////////
+ // Internal design logic to register //
+ ///////////////////////////////////////
+ typedef struct packed {
+ flash_ctrl_hw2reg_intr_state_reg_t intr_state; // [44:39]
+ flash_ctrl_hw2reg_ctrl_regwen_reg_t ctrl_regwen; // [38:39]
+ flash_ctrl_hw2reg_control_reg_t control; // [38:20]
+ flash_ctrl_hw2reg_op_status_reg_t op_status; // [19:20]
+ flash_ctrl_hw2reg_status_reg_t status; // [19:20]
+ flash_ctrl_hw2reg_phy_status_reg_t phy_status; // [19:20]
+ } flash_ctrl_hw2reg_t;
+
+ // Register Address
+ parameter logic [8:0] FLASH_CTRL_INTR_STATE_OFFSET = 9'h 0;
+ parameter logic [8:0] FLASH_CTRL_INTR_ENABLE_OFFSET = 9'h 4;
+ parameter logic [8:0] FLASH_CTRL_INTR_TEST_OFFSET = 9'h 8;
+ parameter logic [8:0] FLASH_CTRL_CTRL_REGWEN_OFFSET = 9'h c;
+ parameter logic [8:0] FLASH_CTRL_CONTROL_OFFSET = 9'h 10;
+ parameter logic [8:0] FLASH_CTRL_ADDR_OFFSET = 9'h 14;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET = 9'h 18;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET = 9'h 1c;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET = 9'h 20;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET = 9'h 24;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET = 9'h 28;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET = 9'h 2c;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET = 9'h 30;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET = 9'h 34;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_0_OFFSET = 9'h 38;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_1_OFFSET = 9'h 3c;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_2_OFFSET = 9'h 40;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_3_OFFSET = 9'h 44;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_4_OFFSET = 9'h 48;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_5_OFFSET = 9'h 4c;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_6_OFFSET = 9'h 50;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_7_OFFSET = 9'h 54;
+ parameter logic [8:0] FLASH_CTRL_DEFAULT_REGION_OFFSET = 9'h 58;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET = 9'h 5c;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET = 9'h 60;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET = 9'h 64;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET = 9'h 68;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_OFFSET = 9'h 6c;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_OFFSET = 9'h 70;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_OFFSET = 9'h 74;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_OFFSET = 9'h 78;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_REGWEN_0_OFFSET = 9'h 7c;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_REGWEN_1_OFFSET = 9'h 80;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_REGWEN_2_OFFSET = 9'h 84;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_REGWEN_3_OFFSET = 9'h 88;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_0_OFFSET = 9'h 8c;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_1_OFFSET = 9'h 90;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_2_OFFSET = 9'h 94;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_3_OFFSET = 9'h 98;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET = 9'h 9c;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET = 9'h a0;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET = 9'h a4;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET = 9'h a8;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_OFFSET = 9'h ac;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_OFFSET = 9'h b0;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_OFFSET = 9'h b4;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_OFFSET = 9'h b8;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_REGWEN_0_OFFSET = 9'h bc;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_REGWEN_1_OFFSET = 9'h c0;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_REGWEN_2_OFFSET = 9'h c4;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_REGWEN_3_OFFSET = 9'h c8;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_0_OFFSET = 9'h cc;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_1_OFFSET = 9'h d0;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_2_OFFSET = 9'h d4;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_3_OFFSET = 9'h d8;
+ parameter logic [8:0] FLASH_CTRL_BANK_CFG_REGWEN_OFFSET = 9'h dc;
+ parameter logic [8:0] FLASH_CTRL_MP_BANK_CFG_OFFSET = 9'h e0;
+ parameter logic [8:0] FLASH_CTRL_OP_STATUS_OFFSET = 9'h e4;
+ parameter logic [8:0] FLASH_CTRL_STATUS_OFFSET = 9'h e8;
+ parameter logic [8:0] FLASH_CTRL_PHY_STATUS_OFFSET = 9'h ec;
+ parameter logic [8:0] FLASH_CTRL_SCRATCH_OFFSET = 9'h f0;
+ parameter logic [8:0] FLASH_CTRL_FIFO_LVL_OFFSET = 9'h f4;
+ parameter logic [8:0] FLASH_CTRL_FIFO_RST_OFFSET = 9'h f8;
+
+ // Window parameter
+ parameter logic [8:0] FLASH_CTRL_PROG_FIFO_OFFSET = 9'h fc;
+ parameter logic [8:0] FLASH_CTRL_PROG_FIFO_SIZE = 9'h 4;
+ parameter logic [8:0] FLASH_CTRL_RD_FIFO_OFFSET = 9'h 100;
+ parameter logic [8:0] FLASH_CTRL_RD_FIFO_SIZE = 9'h 4;
+
+ // Register Index
+ typedef enum int {
+ FLASH_CTRL_INTR_STATE,
+ FLASH_CTRL_INTR_ENABLE,
+ FLASH_CTRL_INTR_TEST,
+ FLASH_CTRL_CTRL_REGWEN,
+ FLASH_CTRL_CONTROL,
+ FLASH_CTRL_ADDR,
+ FLASH_CTRL_REGION_CFG_REGWEN_0,
+ FLASH_CTRL_REGION_CFG_REGWEN_1,
+ FLASH_CTRL_REGION_CFG_REGWEN_2,
+ FLASH_CTRL_REGION_CFG_REGWEN_3,
+ FLASH_CTRL_REGION_CFG_REGWEN_4,
+ FLASH_CTRL_REGION_CFG_REGWEN_5,
+ FLASH_CTRL_REGION_CFG_REGWEN_6,
+ FLASH_CTRL_REGION_CFG_REGWEN_7,
+ FLASH_CTRL_MP_REGION_CFG_0,
+ FLASH_CTRL_MP_REGION_CFG_1,
+ FLASH_CTRL_MP_REGION_CFG_2,
+ FLASH_CTRL_MP_REGION_CFG_3,
+ FLASH_CTRL_MP_REGION_CFG_4,
+ FLASH_CTRL_MP_REGION_CFG_5,
+ FLASH_CTRL_MP_REGION_CFG_6,
+ FLASH_CTRL_MP_REGION_CFG_7,
+ FLASH_CTRL_DEFAULT_REGION,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_0,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_1,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_2,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_3,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3,
+ FLASH_CTRL_BANK0_INFO1_REGWEN_0,
+ FLASH_CTRL_BANK0_INFO1_REGWEN_1,
+ FLASH_CTRL_BANK0_INFO1_REGWEN_2,
+ FLASH_CTRL_BANK0_INFO1_REGWEN_3,
+ FLASH_CTRL_BANK0_INFO1_PAGE_CFG_0,
+ FLASH_CTRL_BANK0_INFO1_PAGE_CFG_1,
+ FLASH_CTRL_BANK0_INFO1_PAGE_CFG_2,
+ FLASH_CTRL_BANK0_INFO1_PAGE_CFG_3,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_0,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_1,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_2,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_3,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3,
+ FLASH_CTRL_BANK1_INFO1_REGWEN_0,
+ FLASH_CTRL_BANK1_INFO1_REGWEN_1,
+ FLASH_CTRL_BANK1_INFO1_REGWEN_2,
+ FLASH_CTRL_BANK1_INFO1_REGWEN_3,
+ FLASH_CTRL_BANK1_INFO1_PAGE_CFG_0,
+ FLASH_CTRL_BANK1_INFO1_PAGE_CFG_1,
+ FLASH_CTRL_BANK1_INFO1_PAGE_CFG_2,
+ FLASH_CTRL_BANK1_INFO1_PAGE_CFG_3,
+ FLASH_CTRL_BANK_CFG_REGWEN,
+ FLASH_CTRL_MP_BANK_CFG,
+ FLASH_CTRL_OP_STATUS,
+ FLASH_CTRL_STATUS,
+ FLASH_CTRL_PHY_STATUS,
+ FLASH_CTRL_SCRATCH,
+ FLASH_CTRL_FIFO_LVL,
+ FLASH_CTRL_FIFO_RST
+ } flash_ctrl_id_e;
+
+ // Register width information to check illegal writes
+ parameter logic [3:0] FLASH_CTRL_PERMIT [63] = '{
+ 4'b 0001, // index[ 0] FLASH_CTRL_INTR_STATE
+ 4'b 0001, // index[ 1] FLASH_CTRL_INTR_ENABLE
+ 4'b 0001, // index[ 2] FLASH_CTRL_INTR_TEST
+ 4'b 0001, // index[ 3] FLASH_CTRL_CTRL_REGWEN
+ 4'b 1111, // index[ 4] FLASH_CTRL_CONTROL
+ 4'b 1111, // index[ 5] FLASH_CTRL_ADDR
+ 4'b 0001, // index[ 6] FLASH_CTRL_REGION_CFG_REGWEN_0
+ 4'b 0001, // index[ 7] FLASH_CTRL_REGION_CFG_REGWEN_1
+ 4'b 0001, // index[ 8] FLASH_CTRL_REGION_CFG_REGWEN_2
+ 4'b 0001, // index[ 9] FLASH_CTRL_REGION_CFG_REGWEN_3
+ 4'b 0001, // index[10] FLASH_CTRL_REGION_CFG_REGWEN_4
+ 4'b 0001, // index[11] FLASH_CTRL_REGION_CFG_REGWEN_5
+ 4'b 0001, // index[12] FLASH_CTRL_REGION_CFG_REGWEN_6
+ 4'b 0001, // index[13] FLASH_CTRL_REGION_CFG_REGWEN_7
+ 4'b 1111, // index[14] FLASH_CTRL_MP_REGION_CFG_0
+ 4'b 1111, // index[15] FLASH_CTRL_MP_REGION_CFG_1
+ 4'b 1111, // index[16] FLASH_CTRL_MP_REGION_CFG_2
+ 4'b 1111, // index[17] FLASH_CTRL_MP_REGION_CFG_3
+ 4'b 1111, // index[18] FLASH_CTRL_MP_REGION_CFG_4
+ 4'b 1111, // index[19] FLASH_CTRL_MP_REGION_CFG_5
+ 4'b 1111, // index[20] FLASH_CTRL_MP_REGION_CFG_6
+ 4'b 1111, // index[21] FLASH_CTRL_MP_REGION_CFG_7
+ 4'b 0001, // index[22] FLASH_CTRL_DEFAULT_REGION
+ 4'b 0001, // index[23] FLASH_CTRL_BANK0_INFO0_REGWEN_0
+ 4'b 0001, // index[24] FLASH_CTRL_BANK0_INFO0_REGWEN_1
+ 4'b 0001, // index[25] FLASH_CTRL_BANK0_INFO0_REGWEN_2
+ 4'b 0001, // index[26] FLASH_CTRL_BANK0_INFO0_REGWEN_3
+ 4'b 0001, // index[27] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0
+ 4'b 0001, // index[28] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1
+ 4'b 0001, // index[29] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2
+ 4'b 0001, // index[30] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3
+ 4'b 0001, // index[31] FLASH_CTRL_BANK0_INFO1_REGWEN_0
+ 4'b 0001, // index[32] FLASH_CTRL_BANK0_INFO1_REGWEN_1
+ 4'b 0001, // index[33] FLASH_CTRL_BANK0_INFO1_REGWEN_2
+ 4'b 0001, // index[34] FLASH_CTRL_BANK0_INFO1_REGWEN_3
+ 4'b 0001, // index[35] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_0
+ 4'b 0001, // index[36] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_1
+ 4'b 0001, // index[37] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_2
+ 4'b 0001, // index[38] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_3
+ 4'b 0001, // index[39] FLASH_CTRL_BANK1_INFO0_REGWEN_0
+ 4'b 0001, // index[40] FLASH_CTRL_BANK1_INFO0_REGWEN_1
+ 4'b 0001, // index[41] FLASH_CTRL_BANK1_INFO0_REGWEN_2
+ 4'b 0001, // index[42] FLASH_CTRL_BANK1_INFO0_REGWEN_3
+ 4'b 0001, // index[43] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0
+ 4'b 0001, // index[44] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1
+ 4'b 0001, // index[45] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2
+ 4'b 0001, // index[46] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3
+ 4'b 0001, // index[47] FLASH_CTRL_BANK1_INFO1_REGWEN_0
+ 4'b 0001, // index[48] FLASH_CTRL_BANK1_INFO1_REGWEN_1
+ 4'b 0001, // index[49] FLASH_CTRL_BANK1_INFO1_REGWEN_2
+ 4'b 0001, // index[50] FLASH_CTRL_BANK1_INFO1_REGWEN_3
+ 4'b 0001, // index[51] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_0
+ 4'b 0001, // index[52] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_1
+ 4'b 0001, // index[53] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_2
+ 4'b 0001, // index[54] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_3
+ 4'b 0001, // index[55] FLASH_CTRL_BANK_CFG_REGWEN
+ 4'b 0001, // index[56] FLASH_CTRL_MP_BANK_CFG
+ 4'b 0001, // index[57] FLASH_CTRL_OP_STATUS
+ 4'b 0111, // index[58] FLASH_CTRL_STATUS
+ 4'b 0001, // index[59] FLASH_CTRL_PHY_STATUS
+ 4'b 1111, // index[60] FLASH_CTRL_SCRATCH
+ 4'b 0011, // index[61] FLASH_CTRL_FIFO_LVL
+ 4'b 0001 // index[62] FLASH_CTRL_FIFO_RST
+ };
+endpackage
+
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_top.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_top.sv
new file mode 100644
index 0000000..280c91c
--- /dev/null
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_top.sv
@@ -0,0 +1,7388 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+`include "prim_assert.sv"
+
+module flash_ctrl_reg_top (
+ input clk_i,
+ input rst_ni,
+
+ // Below Regster interface can be changed
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+
+ // Output port for window
+ output tlul_pkg::tl_h2d_t tl_win_o [2],
+ input tlul_pkg::tl_d2h_t tl_win_i [2],
+
+ // To HW
+ output flash_ctrl_reg_pkg::flash_ctrl_reg2hw_t reg2hw, // Write
+ input flash_ctrl_reg_pkg::flash_ctrl_hw2reg_t hw2reg, // Read
+
+ // Config
+ input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+ import flash_ctrl_reg_pkg::* ;
+
+ localparam int AW = 9;
+ localparam int DW = 32;
+ localparam int DBW = DW/8; // Byte Width
+
+ // register signals
+ logic reg_we;
+ logic reg_re;
+ logic [AW-1:0] reg_addr;
+ logic [DW-1:0] reg_wdata;
+ logic [DBW-1:0] reg_be;
+ logic [DW-1:0] reg_rdata;
+ logic reg_error;
+
+ logic addrmiss, wr_err;
+
+ logic [DW-1:0] reg_rdata_next;
+
+ tlul_pkg::tl_h2d_t tl_reg_h2d;
+ tlul_pkg::tl_d2h_t tl_reg_d2h;
+
+ tlul_pkg::tl_h2d_t tl_socket_h2d [3];
+ tlul_pkg::tl_d2h_t tl_socket_d2h [3];
+
+ logic [1:0] reg_steer;
+
+ // socket_1n connection
+ assign tl_reg_h2d = tl_socket_h2d[2];
+ assign tl_socket_d2h[2] = tl_reg_d2h;
+
+ assign tl_win_o[0] = tl_socket_h2d[0];
+ assign tl_socket_d2h[0] = tl_win_i[0];
+ assign tl_win_o[1] = tl_socket_h2d[1];
+ assign tl_socket_d2h[1] = tl_win_i[1];
+
+ // Create Socket_1n
+ tlul_socket_1n #(
+ .N (3),
+ .HReqPass (1'b1),
+ .HRspPass (1'b1),
+ .DReqPass ({3{1'b1}}),
+ .DRspPass ({3{1'b1}}),
+ .HReqDepth (4'h0),
+ .HRspDepth (4'h0),
+ .DReqDepth ({3{4'h0}}),
+ .DRspDepth ({3{4'h0}})
+ ) u_socket (
+ .clk_i,
+ .rst_ni,
+ .tl_h_i (tl_i),
+ .tl_h_o (tl_o),
+ .tl_d_o (tl_socket_h2d),
+ .tl_d_i (tl_socket_d2h),
+ .dev_select_i (reg_steer)
+ );
+
+ // Create steering logic
+ always_comb begin
+ reg_steer = 2; // Default set to register
+
+ // TODO: Can below codes be unique case () inside ?
+ if (tl_i.a_address[AW-1:0] >= 252 && tl_i.a_address[AW-1:0] < 256) begin
+ reg_steer = 0;
+ end
+ if (tl_i.a_address[AW-1:0] >= 256 && tl_i.a_address[AW-1:0] < 260) begin
+ reg_steer = 1;
+ end
+ end
+
+ tlul_adapter_reg #(
+ .RegAw(AW),
+ .RegDw(DW)
+ ) u_reg_if (
+ .clk_i,
+ .rst_ni,
+
+ .tl_i (tl_reg_h2d),
+ .tl_o (tl_reg_d2h),
+
+ .we_o (reg_we),
+ .re_o (reg_re),
+ .addr_o (reg_addr),
+ .wdata_o (reg_wdata),
+ .be_o (reg_be),
+ .rdata_i (reg_rdata),
+ .error_i (reg_error)
+ );
+
+ assign reg_rdata = reg_rdata_next ;
+ assign reg_error = (devmode_i & addrmiss) | wr_err ;
+
+ // Define SW related signals
+ // Format: <reg>_<field>_{wd|we|qs}
+ // or <reg>_{wd|we|qs} if field == 1 or 0
+ logic intr_state_prog_empty_qs;
+ logic intr_state_prog_empty_wd;
+ logic intr_state_prog_empty_we;
+ logic intr_state_prog_lvl_qs;
+ logic intr_state_prog_lvl_wd;
+ logic intr_state_prog_lvl_we;
+ logic intr_state_rd_full_qs;
+ logic intr_state_rd_full_wd;
+ logic intr_state_rd_full_we;
+ logic intr_state_rd_lvl_qs;
+ logic intr_state_rd_lvl_wd;
+ logic intr_state_rd_lvl_we;
+ logic intr_state_op_done_qs;
+ logic intr_state_op_done_wd;
+ logic intr_state_op_done_we;
+ logic intr_state_op_error_qs;
+ logic intr_state_op_error_wd;
+ logic intr_state_op_error_we;
+ logic intr_enable_prog_empty_qs;
+ logic intr_enable_prog_empty_wd;
+ logic intr_enable_prog_empty_we;
+ logic intr_enable_prog_lvl_qs;
+ logic intr_enable_prog_lvl_wd;
+ logic intr_enable_prog_lvl_we;
+ logic intr_enable_rd_full_qs;
+ logic intr_enable_rd_full_wd;
+ logic intr_enable_rd_full_we;
+ logic intr_enable_rd_lvl_qs;
+ logic intr_enable_rd_lvl_wd;
+ logic intr_enable_rd_lvl_we;
+ logic intr_enable_op_done_qs;
+ logic intr_enable_op_done_wd;
+ logic intr_enable_op_done_we;
+ logic intr_enable_op_error_qs;
+ logic intr_enable_op_error_wd;
+ logic intr_enable_op_error_we;
+ logic intr_test_prog_empty_wd;
+ logic intr_test_prog_empty_we;
+ logic intr_test_prog_lvl_wd;
+ logic intr_test_prog_lvl_we;
+ logic intr_test_rd_full_wd;
+ logic intr_test_rd_full_we;
+ logic intr_test_rd_lvl_wd;
+ logic intr_test_rd_lvl_we;
+ logic intr_test_op_done_wd;
+ logic intr_test_op_done_we;
+ logic intr_test_op_error_wd;
+ logic intr_test_op_error_we;
+ logic ctrl_regwen_qs;
+ logic ctrl_regwen_re;
+ logic control_start_qs;
+ logic control_start_wd;
+ logic control_start_we;
+ logic [1:0] control_op_qs;
+ logic [1:0] control_op_wd;
+ logic control_op_we;
+ logic control_prog_sel_qs;
+ logic control_prog_sel_wd;
+ logic control_prog_sel_we;
+ logic control_erase_sel_qs;
+ logic control_erase_sel_wd;
+ logic control_erase_sel_we;
+ logic control_partition_sel_qs;
+ logic control_partition_sel_wd;
+ logic control_partition_sel_we;
+ logic control_info_sel_qs;
+ logic control_info_sel_wd;
+ logic control_info_sel_we;
+ logic [11:0] control_num_qs;
+ logic [11:0] control_num_wd;
+ logic control_num_we;
+ logic [31:0] addr_qs;
+ logic [31:0] addr_wd;
+ logic addr_we;
+ logic region_cfg_regwen_0_qs;
+ logic region_cfg_regwen_0_wd;
+ logic region_cfg_regwen_0_we;
+ logic region_cfg_regwen_1_qs;
+ logic region_cfg_regwen_1_wd;
+ logic region_cfg_regwen_1_we;
+ logic region_cfg_regwen_2_qs;
+ logic region_cfg_regwen_2_wd;
+ logic region_cfg_regwen_2_we;
+ logic region_cfg_regwen_3_qs;
+ logic region_cfg_regwen_3_wd;
+ logic region_cfg_regwen_3_we;
+ logic region_cfg_regwen_4_qs;
+ logic region_cfg_regwen_4_wd;
+ logic region_cfg_regwen_4_we;
+ logic region_cfg_regwen_5_qs;
+ logic region_cfg_regwen_5_wd;
+ logic region_cfg_regwen_5_we;
+ logic region_cfg_regwen_6_qs;
+ logic region_cfg_regwen_6_wd;
+ logic region_cfg_regwen_6_we;
+ logic region_cfg_regwen_7_qs;
+ logic region_cfg_regwen_7_wd;
+ logic region_cfg_regwen_7_we;
+ logic mp_region_cfg_0_en_0_qs;
+ logic mp_region_cfg_0_en_0_wd;
+ logic mp_region_cfg_0_en_0_we;
+ logic mp_region_cfg_0_rd_en_0_qs;
+ logic mp_region_cfg_0_rd_en_0_wd;
+ logic mp_region_cfg_0_rd_en_0_we;
+ logic mp_region_cfg_0_prog_en_0_qs;
+ logic mp_region_cfg_0_prog_en_0_wd;
+ logic mp_region_cfg_0_prog_en_0_we;
+ logic mp_region_cfg_0_erase_en_0_qs;
+ logic mp_region_cfg_0_erase_en_0_wd;
+ logic mp_region_cfg_0_erase_en_0_we;
+ logic mp_region_cfg_0_scramble_en_0_qs;
+ logic mp_region_cfg_0_scramble_en_0_wd;
+ logic mp_region_cfg_0_scramble_en_0_we;
+ logic [8:0] mp_region_cfg_0_base_0_qs;
+ logic [8:0] mp_region_cfg_0_base_0_wd;
+ logic mp_region_cfg_0_base_0_we;
+ logic [9:0] mp_region_cfg_0_size_0_qs;
+ logic [9:0] mp_region_cfg_0_size_0_wd;
+ logic mp_region_cfg_0_size_0_we;
+ logic mp_region_cfg_1_en_1_qs;
+ logic mp_region_cfg_1_en_1_wd;
+ logic mp_region_cfg_1_en_1_we;
+ logic mp_region_cfg_1_rd_en_1_qs;
+ logic mp_region_cfg_1_rd_en_1_wd;
+ logic mp_region_cfg_1_rd_en_1_we;
+ logic mp_region_cfg_1_prog_en_1_qs;
+ logic mp_region_cfg_1_prog_en_1_wd;
+ logic mp_region_cfg_1_prog_en_1_we;
+ logic mp_region_cfg_1_erase_en_1_qs;
+ logic mp_region_cfg_1_erase_en_1_wd;
+ logic mp_region_cfg_1_erase_en_1_we;
+ logic mp_region_cfg_1_scramble_en_1_qs;
+ logic mp_region_cfg_1_scramble_en_1_wd;
+ logic mp_region_cfg_1_scramble_en_1_we;
+ logic [8:0] mp_region_cfg_1_base_1_qs;
+ logic [8:0] mp_region_cfg_1_base_1_wd;
+ logic mp_region_cfg_1_base_1_we;
+ logic [9:0] mp_region_cfg_1_size_1_qs;
+ logic [9:0] mp_region_cfg_1_size_1_wd;
+ logic mp_region_cfg_1_size_1_we;
+ logic mp_region_cfg_2_en_2_qs;
+ logic mp_region_cfg_2_en_2_wd;
+ logic mp_region_cfg_2_en_2_we;
+ logic mp_region_cfg_2_rd_en_2_qs;
+ logic mp_region_cfg_2_rd_en_2_wd;
+ logic mp_region_cfg_2_rd_en_2_we;
+ logic mp_region_cfg_2_prog_en_2_qs;
+ logic mp_region_cfg_2_prog_en_2_wd;
+ logic mp_region_cfg_2_prog_en_2_we;
+ logic mp_region_cfg_2_erase_en_2_qs;
+ logic mp_region_cfg_2_erase_en_2_wd;
+ logic mp_region_cfg_2_erase_en_2_we;
+ logic mp_region_cfg_2_scramble_en_2_qs;
+ logic mp_region_cfg_2_scramble_en_2_wd;
+ logic mp_region_cfg_2_scramble_en_2_we;
+ logic [8:0] mp_region_cfg_2_base_2_qs;
+ logic [8:0] mp_region_cfg_2_base_2_wd;
+ logic mp_region_cfg_2_base_2_we;
+ logic [9:0] mp_region_cfg_2_size_2_qs;
+ logic [9:0] mp_region_cfg_2_size_2_wd;
+ logic mp_region_cfg_2_size_2_we;
+ logic mp_region_cfg_3_en_3_qs;
+ logic mp_region_cfg_3_en_3_wd;
+ logic mp_region_cfg_3_en_3_we;
+ logic mp_region_cfg_3_rd_en_3_qs;
+ logic mp_region_cfg_3_rd_en_3_wd;
+ logic mp_region_cfg_3_rd_en_3_we;
+ logic mp_region_cfg_3_prog_en_3_qs;
+ logic mp_region_cfg_3_prog_en_3_wd;
+ logic mp_region_cfg_3_prog_en_3_we;
+ logic mp_region_cfg_3_erase_en_3_qs;
+ logic mp_region_cfg_3_erase_en_3_wd;
+ logic mp_region_cfg_3_erase_en_3_we;
+ logic mp_region_cfg_3_scramble_en_3_qs;
+ logic mp_region_cfg_3_scramble_en_3_wd;
+ logic mp_region_cfg_3_scramble_en_3_we;
+ logic [8:0] mp_region_cfg_3_base_3_qs;
+ logic [8:0] mp_region_cfg_3_base_3_wd;
+ logic mp_region_cfg_3_base_3_we;
+ logic [9:0] mp_region_cfg_3_size_3_qs;
+ logic [9:0] mp_region_cfg_3_size_3_wd;
+ logic mp_region_cfg_3_size_3_we;
+ logic mp_region_cfg_4_en_4_qs;
+ logic mp_region_cfg_4_en_4_wd;
+ logic mp_region_cfg_4_en_4_we;
+ logic mp_region_cfg_4_rd_en_4_qs;
+ logic mp_region_cfg_4_rd_en_4_wd;
+ logic mp_region_cfg_4_rd_en_4_we;
+ logic mp_region_cfg_4_prog_en_4_qs;
+ logic mp_region_cfg_4_prog_en_4_wd;
+ logic mp_region_cfg_4_prog_en_4_we;
+ logic mp_region_cfg_4_erase_en_4_qs;
+ logic mp_region_cfg_4_erase_en_4_wd;
+ logic mp_region_cfg_4_erase_en_4_we;
+ logic mp_region_cfg_4_scramble_en_4_qs;
+ logic mp_region_cfg_4_scramble_en_4_wd;
+ logic mp_region_cfg_4_scramble_en_4_we;
+ logic [8:0] mp_region_cfg_4_base_4_qs;
+ logic [8:0] mp_region_cfg_4_base_4_wd;
+ logic mp_region_cfg_4_base_4_we;
+ logic [9:0] mp_region_cfg_4_size_4_qs;
+ logic [9:0] mp_region_cfg_4_size_4_wd;
+ logic mp_region_cfg_4_size_4_we;
+ logic mp_region_cfg_5_en_5_qs;
+ logic mp_region_cfg_5_en_5_wd;
+ logic mp_region_cfg_5_en_5_we;
+ logic mp_region_cfg_5_rd_en_5_qs;
+ logic mp_region_cfg_5_rd_en_5_wd;
+ logic mp_region_cfg_5_rd_en_5_we;
+ logic mp_region_cfg_5_prog_en_5_qs;
+ logic mp_region_cfg_5_prog_en_5_wd;
+ logic mp_region_cfg_5_prog_en_5_we;
+ logic mp_region_cfg_5_erase_en_5_qs;
+ logic mp_region_cfg_5_erase_en_5_wd;
+ logic mp_region_cfg_5_erase_en_5_we;
+ logic mp_region_cfg_5_scramble_en_5_qs;
+ logic mp_region_cfg_5_scramble_en_5_wd;
+ logic mp_region_cfg_5_scramble_en_5_we;
+ logic [8:0] mp_region_cfg_5_base_5_qs;
+ logic [8:0] mp_region_cfg_5_base_5_wd;
+ logic mp_region_cfg_5_base_5_we;
+ logic [9:0] mp_region_cfg_5_size_5_qs;
+ logic [9:0] mp_region_cfg_5_size_5_wd;
+ logic mp_region_cfg_5_size_5_we;
+ logic mp_region_cfg_6_en_6_qs;
+ logic mp_region_cfg_6_en_6_wd;
+ logic mp_region_cfg_6_en_6_we;
+ logic mp_region_cfg_6_rd_en_6_qs;
+ logic mp_region_cfg_6_rd_en_6_wd;
+ logic mp_region_cfg_6_rd_en_6_we;
+ logic mp_region_cfg_6_prog_en_6_qs;
+ logic mp_region_cfg_6_prog_en_6_wd;
+ logic mp_region_cfg_6_prog_en_6_we;
+ logic mp_region_cfg_6_erase_en_6_qs;
+ logic mp_region_cfg_6_erase_en_6_wd;
+ logic mp_region_cfg_6_erase_en_6_we;
+ logic mp_region_cfg_6_scramble_en_6_qs;
+ logic mp_region_cfg_6_scramble_en_6_wd;
+ logic mp_region_cfg_6_scramble_en_6_we;
+ logic [8:0] mp_region_cfg_6_base_6_qs;
+ logic [8:0] mp_region_cfg_6_base_6_wd;
+ logic mp_region_cfg_6_base_6_we;
+ logic [9:0] mp_region_cfg_6_size_6_qs;
+ logic [9:0] mp_region_cfg_6_size_6_wd;
+ logic mp_region_cfg_6_size_6_we;
+ logic mp_region_cfg_7_en_7_qs;
+ logic mp_region_cfg_7_en_7_wd;
+ logic mp_region_cfg_7_en_7_we;
+ logic mp_region_cfg_7_rd_en_7_qs;
+ logic mp_region_cfg_7_rd_en_7_wd;
+ logic mp_region_cfg_7_rd_en_7_we;
+ logic mp_region_cfg_7_prog_en_7_qs;
+ logic mp_region_cfg_7_prog_en_7_wd;
+ logic mp_region_cfg_7_prog_en_7_we;
+ logic mp_region_cfg_7_erase_en_7_qs;
+ logic mp_region_cfg_7_erase_en_7_wd;
+ logic mp_region_cfg_7_erase_en_7_we;
+ logic mp_region_cfg_7_scramble_en_7_qs;
+ logic mp_region_cfg_7_scramble_en_7_wd;
+ logic mp_region_cfg_7_scramble_en_7_we;
+ logic [8:0] mp_region_cfg_7_base_7_qs;
+ logic [8:0] mp_region_cfg_7_base_7_wd;
+ logic mp_region_cfg_7_base_7_we;
+ logic [9:0] mp_region_cfg_7_size_7_qs;
+ logic [9:0] mp_region_cfg_7_size_7_wd;
+ logic mp_region_cfg_7_size_7_we;
+ logic default_region_rd_en_qs;
+ logic default_region_rd_en_wd;
+ logic default_region_rd_en_we;
+ logic default_region_prog_en_qs;
+ logic default_region_prog_en_wd;
+ logic default_region_prog_en_we;
+ logic default_region_erase_en_qs;
+ logic default_region_erase_en_wd;
+ logic default_region_erase_en_we;
+ logic default_region_scramble_en_qs;
+ logic default_region_scramble_en_wd;
+ logic default_region_scramble_en_we;
+ logic bank0_info0_regwen_0_qs;
+ logic bank0_info0_regwen_0_wd;
+ logic bank0_info0_regwen_0_we;
+ logic bank0_info0_regwen_1_qs;
+ logic bank0_info0_regwen_1_wd;
+ logic bank0_info0_regwen_1_we;
+ logic bank0_info0_regwen_2_qs;
+ logic bank0_info0_regwen_2_wd;
+ logic bank0_info0_regwen_2_we;
+ logic bank0_info0_regwen_3_qs;
+ logic bank0_info0_regwen_3_wd;
+ logic bank0_info0_regwen_3_we;
+ logic bank0_info0_page_cfg_0_en_0_qs;
+ logic bank0_info0_page_cfg_0_en_0_wd;
+ logic bank0_info0_page_cfg_0_en_0_we;
+ logic bank0_info0_page_cfg_0_rd_en_0_qs;
+ logic bank0_info0_page_cfg_0_rd_en_0_wd;
+ logic bank0_info0_page_cfg_0_rd_en_0_we;
+ logic bank0_info0_page_cfg_0_prog_en_0_qs;
+ logic bank0_info0_page_cfg_0_prog_en_0_wd;
+ logic bank0_info0_page_cfg_0_prog_en_0_we;
+ logic bank0_info0_page_cfg_0_erase_en_0_qs;
+ logic bank0_info0_page_cfg_0_erase_en_0_wd;
+ logic bank0_info0_page_cfg_0_erase_en_0_we;
+ logic bank0_info0_page_cfg_0_scramble_en_0_qs;
+ logic bank0_info0_page_cfg_0_scramble_en_0_wd;
+ logic bank0_info0_page_cfg_0_scramble_en_0_we;
+ logic bank0_info0_page_cfg_1_en_1_qs;
+ logic bank0_info0_page_cfg_1_en_1_wd;
+ logic bank0_info0_page_cfg_1_en_1_we;
+ logic bank0_info0_page_cfg_1_rd_en_1_qs;
+ logic bank0_info0_page_cfg_1_rd_en_1_wd;
+ logic bank0_info0_page_cfg_1_rd_en_1_we;
+ logic bank0_info0_page_cfg_1_prog_en_1_qs;
+ logic bank0_info0_page_cfg_1_prog_en_1_wd;
+ logic bank0_info0_page_cfg_1_prog_en_1_we;
+ logic bank0_info0_page_cfg_1_erase_en_1_qs;
+ logic bank0_info0_page_cfg_1_erase_en_1_wd;
+ logic bank0_info0_page_cfg_1_erase_en_1_we;
+ logic bank0_info0_page_cfg_1_scramble_en_1_qs;
+ logic bank0_info0_page_cfg_1_scramble_en_1_wd;
+ logic bank0_info0_page_cfg_1_scramble_en_1_we;
+ logic bank0_info0_page_cfg_2_en_2_qs;
+ logic bank0_info0_page_cfg_2_en_2_wd;
+ logic bank0_info0_page_cfg_2_en_2_we;
+ logic bank0_info0_page_cfg_2_rd_en_2_qs;
+ logic bank0_info0_page_cfg_2_rd_en_2_wd;
+ logic bank0_info0_page_cfg_2_rd_en_2_we;
+ logic bank0_info0_page_cfg_2_prog_en_2_qs;
+ logic bank0_info0_page_cfg_2_prog_en_2_wd;
+ logic bank0_info0_page_cfg_2_prog_en_2_we;
+ logic bank0_info0_page_cfg_2_erase_en_2_qs;
+ logic bank0_info0_page_cfg_2_erase_en_2_wd;
+ logic bank0_info0_page_cfg_2_erase_en_2_we;
+ logic bank0_info0_page_cfg_2_scramble_en_2_qs;
+ logic bank0_info0_page_cfg_2_scramble_en_2_wd;
+ logic bank0_info0_page_cfg_2_scramble_en_2_we;
+ logic bank0_info0_page_cfg_3_en_3_qs;
+ logic bank0_info0_page_cfg_3_en_3_wd;
+ logic bank0_info0_page_cfg_3_en_3_we;
+ logic bank0_info0_page_cfg_3_rd_en_3_qs;
+ logic bank0_info0_page_cfg_3_rd_en_3_wd;
+ logic bank0_info0_page_cfg_3_rd_en_3_we;
+ logic bank0_info0_page_cfg_3_prog_en_3_qs;
+ logic bank0_info0_page_cfg_3_prog_en_3_wd;
+ logic bank0_info0_page_cfg_3_prog_en_3_we;
+ logic bank0_info0_page_cfg_3_erase_en_3_qs;
+ logic bank0_info0_page_cfg_3_erase_en_3_wd;
+ logic bank0_info0_page_cfg_3_erase_en_3_we;
+ logic bank0_info0_page_cfg_3_scramble_en_3_qs;
+ logic bank0_info0_page_cfg_3_scramble_en_3_wd;
+ logic bank0_info0_page_cfg_3_scramble_en_3_we;
+ logic bank0_info1_regwen_0_qs;
+ logic bank0_info1_regwen_0_wd;
+ logic bank0_info1_regwen_0_we;
+ logic bank0_info1_regwen_1_qs;
+ logic bank0_info1_regwen_1_wd;
+ logic bank0_info1_regwen_1_we;
+ logic bank0_info1_regwen_2_qs;
+ logic bank0_info1_regwen_2_wd;
+ logic bank0_info1_regwen_2_we;
+ logic bank0_info1_regwen_3_qs;
+ logic bank0_info1_regwen_3_wd;
+ logic bank0_info1_regwen_3_we;
+ logic bank0_info1_page_cfg_0_en_0_qs;
+ logic bank0_info1_page_cfg_0_en_0_wd;
+ logic bank0_info1_page_cfg_0_en_0_we;
+ logic bank0_info1_page_cfg_0_rd_en_0_qs;
+ logic bank0_info1_page_cfg_0_rd_en_0_wd;
+ logic bank0_info1_page_cfg_0_rd_en_0_we;
+ logic bank0_info1_page_cfg_0_prog_en_0_qs;
+ logic bank0_info1_page_cfg_0_prog_en_0_wd;
+ logic bank0_info1_page_cfg_0_prog_en_0_we;
+ logic bank0_info1_page_cfg_0_erase_en_0_qs;
+ logic bank0_info1_page_cfg_0_erase_en_0_wd;
+ logic bank0_info1_page_cfg_0_erase_en_0_we;
+ logic bank0_info1_page_cfg_0_scramble_en_0_qs;
+ logic bank0_info1_page_cfg_0_scramble_en_0_wd;
+ logic bank0_info1_page_cfg_0_scramble_en_0_we;
+ logic bank0_info1_page_cfg_1_en_1_qs;
+ logic bank0_info1_page_cfg_1_en_1_wd;
+ logic bank0_info1_page_cfg_1_en_1_we;
+ logic bank0_info1_page_cfg_1_rd_en_1_qs;
+ logic bank0_info1_page_cfg_1_rd_en_1_wd;
+ logic bank0_info1_page_cfg_1_rd_en_1_we;
+ logic bank0_info1_page_cfg_1_prog_en_1_qs;
+ logic bank0_info1_page_cfg_1_prog_en_1_wd;
+ logic bank0_info1_page_cfg_1_prog_en_1_we;
+ logic bank0_info1_page_cfg_1_erase_en_1_qs;
+ logic bank0_info1_page_cfg_1_erase_en_1_wd;
+ logic bank0_info1_page_cfg_1_erase_en_1_we;
+ logic bank0_info1_page_cfg_1_scramble_en_1_qs;
+ logic bank0_info1_page_cfg_1_scramble_en_1_wd;
+ logic bank0_info1_page_cfg_1_scramble_en_1_we;
+ logic bank0_info1_page_cfg_2_en_2_qs;
+ logic bank0_info1_page_cfg_2_en_2_wd;
+ logic bank0_info1_page_cfg_2_en_2_we;
+ logic bank0_info1_page_cfg_2_rd_en_2_qs;
+ logic bank0_info1_page_cfg_2_rd_en_2_wd;
+ logic bank0_info1_page_cfg_2_rd_en_2_we;
+ logic bank0_info1_page_cfg_2_prog_en_2_qs;
+ logic bank0_info1_page_cfg_2_prog_en_2_wd;
+ logic bank0_info1_page_cfg_2_prog_en_2_we;
+ logic bank0_info1_page_cfg_2_erase_en_2_qs;
+ logic bank0_info1_page_cfg_2_erase_en_2_wd;
+ logic bank0_info1_page_cfg_2_erase_en_2_we;
+ logic bank0_info1_page_cfg_2_scramble_en_2_qs;
+ logic bank0_info1_page_cfg_2_scramble_en_2_wd;
+ logic bank0_info1_page_cfg_2_scramble_en_2_we;
+ logic bank0_info1_page_cfg_3_en_3_qs;
+ logic bank0_info1_page_cfg_3_en_3_wd;
+ logic bank0_info1_page_cfg_3_en_3_we;
+ logic bank0_info1_page_cfg_3_rd_en_3_qs;
+ logic bank0_info1_page_cfg_3_rd_en_3_wd;
+ logic bank0_info1_page_cfg_3_rd_en_3_we;
+ logic bank0_info1_page_cfg_3_prog_en_3_qs;
+ logic bank0_info1_page_cfg_3_prog_en_3_wd;
+ logic bank0_info1_page_cfg_3_prog_en_3_we;
+ logic bank0_info1_page_cfg_3_erase_en_3_qs;
+ logic bank0_info1_page_cfg_3_erase_en_3_wd;
+ logic bank0_info1_page_cfg_3_erase_en_3_we;
+ logic bank0_info1_page_cfg_3_scramble_en_3_qs;
+ logic bank0_info1_page_cfg_3_scramble_en_3_wd;
+ logic bank0_info1_page_cfg_3_scramble_en_3_we;
+ logic bank1_info0_regwen_0_qs;
+ logic bank1_info0_regwen_0_wd;
+ logic bank1_info0_regwen_0_we;
+ logic bank1_info0_regwen_1_qs;
+ logic bank1_info0_regwen_1_wd;
+ logic bank1_info0_regwen_1_we;
+ logic bank1_info0_regwen_2_qs;
+ logic bank1_info0_regwen_2_wd;
+ logic bank1_info0_regwen_2_we;
+ logic bank1_info0_regwen_3_qs;
+ logic bank1_info0_regwen_3_wd;
+ logic bank1_info0_regwen_3_we;
+ logic bank1_info0_page_cfg_0_en_0_qs;
+ logic bank1_info0_page_cfg_0_en_0_wd;
+ logic bank1_info0_page_cfg_0_en_0_we;
+ logic bank1_info0_page_cfg_0_rd_en_0_qs;
+ logic bank1_info0_page_cfg_0_rd_en_0_wd;
+ logic bank1_info0_page_cfg_0_rd_en_0_we;
+ logic bank1_info0_page_cfg_0_prog_en_0_qs;
+ logic bank1_info0_page_cfg_0_prog_en_0_wd;
+ logic bank1_info0_page_cfg_0_prog_en_0_we;
+ logic bank1_info0_page_cfg_0_erase_en_0_qs;
+ logic bank1_info0_page_cfg_0_erase_en_0_wd;
+ logic bank1_info0_page_cfg_0_erase_en_0_we;
+ logic bank1_info0_page_cfg_0_scramble_en_0_qs;
+ logic bank1_info0_page_cfg_0_scramble_en_0_wd;
+ logic bank1_info0_page_cfg_0_scramble_en_0_we;
+ logic bank1_info0_page_cfg_1_en_1_qs;
+ logic bank1_info0_page_cfg_1_en_1_wd;
+ logic bank1_info0_page_cfg_1_en_1_we;
+ logic bank1_info0_page_cfg_1_rd_en_1_qs;
+ logic bank1_info0_page_cfg_1_rd_en_1_wd;
+ logic bank1_info0_page_cfg_1_rd_en_1_we;
+ logic bank1_info0_page_cfg_1_prog_en_1_qs;
+ logic bank1_info0_page_cfg_1_prog_en_1_wd;
+ logic bank1_info0_page_cfg_1_prog_en_1_we;
+ logic bank1_info0_page_cfg_1_erase_en_1_qs;
+ logic bank1_info0_page_cfg_1_erase_en_1_wd;
+ logic bank1_info0_page_cfg_1_erase_en_1_we;
+ logic bank1_info0_page_cfg_1_scramble_en_1_qs;
+ logic bank1_info0_page_cfg_1_scramble_en_1_wd;
+ logic bank1_info0_page_cfg_1_scramble_en_1_we;
+ logic bank1_info0_page_cfg_2_en_2_qs;
+ logic bank1_info0_page_cfg_2_en_2_wd;
+ logic bank1_info0_page_cfg_2_en_2_we;
+ logic bank1_info0_page_cfg_2_rd_en_2_qs;
+ logic bank1_info0_page_cfg_2_rd_en_2_wd;
+ logic bank1_info0_page_cfg_2_rd_en_2_we;
+ logic bank1_info0_page_cfg_2_prog_en_2_qs;
+ logic bank1_info0_page_cfg_2_prog_en_2_wd;
+ logic bank1_info0_page_cfg_2_prog_en_2_we;
+ logic bank1_info0_page_cfg_2_erase_en_2_qs;
+ logic bank1_info0_page_cfg_2_erase_en_2_wd;
+ logic bank1_info0_page_cfg_2_erase_en_2_we;
+ logic bank1_info0_page_cfg_2_scramble_en_2_qs;
+ logic bank1_info0_page_cfg_2_scramble_en_2_wd;
+ logic bank1_info0_page_cfg_2_scramble_en_2_we;
+ logic bank1_info0_page_cfg_3_en_3_qs;
+ logic bank1_info0_page_cfg_3_en_3_wd;
+ logic bank1_info0_page_cfg_3_en_3_we;
+ logic bank1_info0_page_cfg_3_rd_en_3_qs;
+ logic bank1_info0_page_cfg_3_rd_en_3_wd;
+ logic bank1_info0_page_cfg_3_rd_en_3_we;
+ logic bank1_info0_page_cfg_3_prog_en_3_qs;
+ logic bank1_info0_page_cfg_3_prog_en_3_wd;
+ logic bank1_info0_page_cfg_3_prog_en_3_we;
+ logic bank1_info0_page_cfg_3_erase_en_3_qs;
+ logic bank1_info0_page_cfg_3_erase_en_3_wd;
+ logic bank1_info0_page_cfg_3_erase_en_3_we;
+ logic bank1_info0_page_cfg_3_scramble_en_3_qs;
+ logic bank1_info0_page_cfg_3_scramble_en_3_wd;
+ logic bank1_info0_page_cfg_3_scramble_en_3_we;
+ logic bank1_info1_regwen_0_qs;
+ logic bank1_info1_regwen_0_wd;
+ logic bank1_info1_regwen_0_we;
+ logic bank1_info1_regwen_1_qs;
+ logic bank1_info1_regwen_1_wd;
+ logic bank1_info1_regwen_1_we;
+ logic bank1_info1_regwen_2_qs;
+ logic bank1_info1_regwen_2_wd;
+ logic bank1_info1_regwen_2_we;
+ logic bank1_info1_regwen_3_qs;
+ logic bank1_info1_regwen_3_wd;
+ logic bank1_info1_regwen_3_we;
+ logic bank1_info1_page_cfg_0_en_0_qs;
+ logic bank1_info1_page_cfg_0_en_0_wd;
+ logic bank1_info1_page_cfg_0_en_0_we;
+ logic bank1_info1_page_cfg_0_rd_en_0_qs;
+ logic bank1_info1_page_cfg_0_rd_en_0_wd;
+ logic bank1_info1_page_cfg_0_rd_en_0_we;
+ logic bank1_info1_page_cfg_0_prog_en_0_qs;
+ logic bank1_info1_page_cfg_0_prog_en_0_wd;
+ logic bank1_info1_page_cfg_0_prog_en_0_we;
+ logic bank1_info1_page_cfg_0_erase_en_0_qs;
+ logic bank1_info1_page_cfg_0_erase_en_0_wd;
+ logic bank1_info1_page_cfg_0_erase_en_0_we;
+ logic bank1_info1_page_cfg_0_scramble_en_0_qs;
+ logic bank1_info1_page_cfg_0_scramble_en_0_wd;
+ logic bank1_info1_page_cfg_0_scramble_en_0_we;
+ logic bank1_info1_page_cfg_1_en_1_qs;
+ logic bank1_info1_page_cfg_1_en_1_wd;
+ logic bank1_info1_page_cfg_1_en_1_we;
+ logic bank1_info1_page_cfg_1_rd_en_1_qs;
+ logic bank1_info1_page_cfg_1_rd_en_1_wd;
+ logic bank1_info1_page_cfg_1_rd_en_1_we;
+ logic bank1_info1_page_cfg_1_prog_en_1_qs;
+ logic bank1_info1_page_cfg_1_prog_en_1_wd;
+ logic bank1_info1_page_cfg_1_prog_en_1_we;
+ logic bank1_info1_page_cfg_1_erase_en_1_qs;
+ logic bank1_info1_page_cfg_1_erase_en_1_wd;
+ logic bank1_info1_page_cfg_1_erase_en_1_we;
+ logic bank1_info1_page_cfg_1_scramble_en_1_qs;
+ logic bank1_info1_page_cfg_1_scramble_en_1_wd;
+ logic bank1_info1_page_cfg_1_scramble_en_1_we;
+ logic bank1_info1_page_cfg_2_en_2_qs;
+ logic bank1_info1_page_cfg_2_en_2_wd;
+ logic bank1_info1_page_cfg_2_en_2_we;
+ logic bank1_info1_page_cfg_2_rd_en_2_qs;
+ logic bank1_info1_page_cfg_2_rd_en_2_wd;
+ logic bank1_info1_page_cfg_2_rd_en_2_we;
+ logic bank1_info1_page_cfg_2_prog_en_2_qs;
+ logic bank1_info1_page_cfg_2_prog_en_2_wd;
+ logic bank1_info1_page_cfg_2_prog_en_2_we;
+ logic bank1_info1_page_cfg_2_erase_en_2_qs;
+ logic bank1_info1_page_cfg_2_erase_en_2_wd;
+ logic bank1_info1_page_cfg_2_erase_en_2_we;
+ logic bank1_info1_page_cfg_2_scramble_en_2_qs;
+ logic bank1_info1_page_cfg_2_scramble_en_2_wd;
+ logic bank1_info1_page_cfg_2_scramble_en_2_we;
+ logic bank1_info1_page_cfg_3_en_3_qs;
+ logic bank1_info1_page_cfg_3_en_3_wd;
+ logic bank1_info1_page_cfg_3_en_3_we;
+ logic bank1_info1_page_cfg_3_rd_en_3_qs;
+ logic bank1_info1_page_cfg_3_rd_en_3_wd;
+ logic bank1_info1_page_cfg_3_rd_en_3_we;
+ logic bank1_info1_page_cfg_3_prog_en_3_qs;
+ logic bank1_info1_page_cfg_3_prog_en_3_wd;
+ logic bank1_info1_page_cfg_3_prog_en_3_we;
+ logic bank1_info1_page_cfg_3_erase_en_3_qs;
+ logic bank1_info1_page_cfg_3_erase_en_3_wd;
+ logic bank1_info1_page_cfg_3_erase_en_3_we;
+ logic bank1_info1_page_cfg_3_scramble_en_3_qs;
+ logic bank1_info1_page_cfg_3_scramble_en_3_wd;
+ logic bank1_info1_page_cfg_3_scramble_en_3_we;
+ logic bank_cfg_regwen_qs;
+ logic bank_cfg_regwen_wd;
+ logic bank_cfg_regwen_we;
+ logic mp_bank_cfg_erase_en_0_qs;
+ logic mp_bank_cfg_erase_en_0_wd;
+ logic mp_bank_cfg_erase_en_0_we;
+ logic mp_bank_cfg_erase_en_1_qs;
+ logic mp_bank_cfg_erase_en_1_wd;
+ logic mp_bank_cfg_erase_en_1_we;
+ logic op_status_done_qs;
+ logic op_status_done_wd;
+ logic op_status_done_we;
+ logic op_status_err_qs;
+ logic op_status_err_wd;
+ logic op_status_err_we;
+ logic status_rd_full_qs;
+ logic status_rd_empty_qs;
+ logic status_prog_full_qs;
+ logic status_prog_empty_qs;
+ logic status_init_wip_qs;
+ logic [8:0] status_error_addr_qs;
+ logic phy_status_init_wip_qs;
+ logic phy_status_prog_normal_avail_qs;
+ logic phy_status_prog_repair_avail_qs;
+ logic [31:0] scratch_qs;
+ logic [31:0] scratch_wd;
+ logic scratch_we;
+ logic [4:0] fifo_lvl_prog_qs;
+ logic [4:0] fifo_lvl_prog_wd;
+ logic fifo_lvl_prog_we;
+ logic [4:0] fifo_lvl_rd_qs;
+ logic [4:0] fifo_lvl_rd_wd;
+ logic fifo_lvl_rd_we;
+ logic fifo_rst_qs;
+ logic fifo_rst_wd;
+ logic fifo_rst_we;
+
+ // Register instances
+ // R[intr_state]: V(False)
+
+ // F[prog_empty]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_prog_empty (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_prog_empty_we),
+ .wd (intr_state_prog_empty_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.prog_empty.de),
+ .d (hw2reg.intr_state.prog_empty.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.prog_empty.q ),
+
+ // to register interface (read)
+ .qs (intr_state_prog_empty_qs)
+ );
+
+
+ // F[prog_lvl]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_prog_lvl (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_prog_lvl_we),
+ .wd (intr_state_prog_lvl_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.prog_lvl.de),
+ .d (hw2reg.intr_state.prog_lvl.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.prog_lvl.q ),
+
+ // to register interface (read)
+ .qs (intr_state_prog_lvl_qs)
+ );
+
+
+ // F[rd_full]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_rd_full (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_rd_full_we),
+ .wd (intr_state_rd_full_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.rd_full.de),
+ .d (hw2reg.intr_state.rd_full.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.rd_full.q ),
+
+ // to register interface (read)
+ .qs (intr_state_rd_full_qs)
+ );
+
+
+ // F[rd_lvl]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_rd_lvl (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_rd_lvl_we),
+ .wd (intr_state_rd_lvl_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.rd_lvl.de),
+ .d (hw2reg.intr_state.rd_lvl.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.rd_lvl.q ),
+
+ // to register interface (read)
+ .qs (intr_state_rd_lvl_qs)
+ );
+
+
+ // F[op_done]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_op_done (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_op_done_we),
+ .wd (intr_state_op_done_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.op_done.de),
+ .d (hw2reg.intr_state.op_done.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.op_done.q ),
+
+ // to register interface (read)
+ .qs (intr_state_op_done_qs)
+ );
+
+
+ // F[op_error]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_op_error (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_op_error_we),
+ .wd (intr_state_op_error_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.op_error.de),
+ .d (hw2reg.intr_state.op_error.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.op_error.q ),
+
+ // to register interface (read)
+ .qs (intr_state_op_error_qs)
+ );
+
+
+ // R[intr_enable]: V(False)
+
+ // F[prog_empty]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_prog_empty (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_prog_empty_we),
+ .wd (intr_enable_prog_empty_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.prog_empty.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_prog_empty_qs)
+ );
+
+
+ // F[prog_lvl]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_prog_lvl (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_prog_lvl_we),
+ .wd (intr_enable_prog_lvl_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.prog_lvl.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_prog_lvl_qs)
+ );
+
+
+ // F[rd_full]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_rd_full (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_rd_full_we),
+ .wd (intr_enable_rd_full_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.rd_full.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_rd_full_qs)
+ );
+
+
+ // F[rd_lvl]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_rd_lvl (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_rd_lvl_we),
+ .wd (intr_enable_rd_lvl_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.rd_lvl.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_rd_lvl_qs)
+ );
+
+
+ // F[op_done]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_op_done (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_op_done_we),
+ .wd (intr_enable_op_done_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.op_done.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_op_done_qs)
+ );
+
+
+ // F[op_error]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_op_error (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_op_error_we),
+ .wd (intr_enable_op_error_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.op_error.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_op_error_qs)
+ );
+
+
+ // R[intr_test]: V(True)
+
+ // F[prog_empty]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_prog_empty (
+ .re (1'b0),
+ .we (intr_test_prog_empty_we),
+ .wd (intr_test_prog_empty_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.prog_empty.qe),
+ .q (reg2hw.intr_test.prog_empty.q ),
+ .qs ()
+ );
+
+
+ // F[prog_lvl]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_prog_lvl (
+ .re (1'b0),
+ .we (intr_test_prog_lvl_we),
+ .wd (intr_test_prog_lvl_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.prog_lvl.qe),
+ .q (reg2hw.intr_test.prog_lvl.q ),
+ .qs ()
+ );
+
+
+ // F[rd_full]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_rd_full (
+ .re (1'b0),
+ .we (intr_test_rd_full_we),
+ .wd (intr_test_rd_full_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.rd_full.qe),
+ .q (reg2hw.intr_test.rd_full.q ),
+ .qs ()
+ );
+
+
+ // F[rd_lvl]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_rd_lvl (
+ .re (1'b0),
+ .we (intr_test_rd_lvl_we),
+ .wd (intr_test_rd_lvl_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.rd_lvl.qe),
+ .q (reg2hw.intr_test.rd_lvl.q ),
+ .qs ()
+ );
+
+
+ // F[op_done]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_op_done (
+ .re (1'b0),
+ .we (intr_test_op_done_we),
+ .wd (intr_test_op_done_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.op_done.qe),
+ .q (reg2hw.intr_test.op_done.q ),
+ .qs ()
+ );
+
+
+ // F[op_error]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_op_error (
+ .re (1'b0),
+ .we (intr_test_op_error_we),
+ .wd (intr_test_op_error_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.op_error.qe),
+ .q (reg2hw.intr_test.op_error.q ),
+ .qs ()
+ );
+
+
+ // R[ctrl_regwen]: V(True)
+
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_ctrl_regwen (
+ .re (ctrl_regwen_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.ctrl_regwen.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (ctrl_regwen_qs)
+ );
+
+
+ // R[control]: V(False)
+
+ // F[start]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_control_start (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (control_start_we & ctrl_regwen_qs),
+ .wd (control_start_wd),
+
+ // from internal hardware
+ .de (hw2reg.control.start.de),
+ .d (hw2reg.control.start.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.control.start.q ),
+
+ // to register interface (read)
+ .qs (control_start_qs)
+ );
+
+
+ // F[op]: 5:4
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_control_op (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (control_op_we & ctrl_regwen_qs),
+ .wd (control_op_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.control.op.q ),
+
+ // to register interface (read)
+ .qs (control_op_qs)
+ );
+
+
+ // F[prog_sel]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_control_prog_sel (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (control_prog_sel_we & ctrl_regwen_qs),
+ .wd (control_prog_sel_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.control.prog_sel.q ),
+
+ // to register interface (read)
+ .qs (control_prog_sel_qs)
+ );
+
+
+ // F[erase_sel]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_control_erase_sel (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (control_erase_sel_we & ctrl_regwen_qs),
+ .wd (control_erase_sel_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.control.erase_sel.q ),
+
+ // to register interface (read)
+ .qs (control_erase_sel_qs)
+ );
+
+
+ // F[partition_sel]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_control_partition_sel (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (control_partition_sel_we & ctrl_regwen_qs),
+ .wd (control_partition_sel_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.control.partition_sel.q ),
+
+ // to register interface (read)
+ .qs (control_partition_sel_qs)
+ );
+
+
+ // F[info_sel]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_control_info_sel (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (control_info_sel_we & ctrl_regwen_qs),
+ .wd (control_info_sel_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.control.info_sel.q ),
+
+ // to register interface (read)
+ .qs (control_info_sel_qs)
+ );
+
+
+ // F[num]: 27:16
+ prim_subreg #(
+ .DW (12),
+ .SWACCESS("RW"),
+ .RESVAL (12'h0)
+ ) u_control_num (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (control_num_we & ctrl_regwen_qs),
+ .wd (control_num_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.control.num.q ),
+
+ // to register interface (read)
+ .qs (control_num_qs)
+ );
+
+
+ // R[addr]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_addr (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (addr_we),
+ .wd (addr_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.addr.q ),
+
+ // to register interface (read)
+ .qs (addr_qs)
+ );
+
+
+
+ // Subregister 0 of Multireg region_cfg_regwen
+ // R[region_cfg_regwen_0]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (region_cfg_regwen_0_we),
+ .wd (region_cfg_regwen_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_0_qs)
+ );
+
+ // Subregister 1 of Multireg region_cfg_regwen
+ // R[region_cfg_regwen_1]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (region_cfg_regwen_1_we),
+ .wd (region_cfg_regwen_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_1_qs)
+ );
+
+ // Subregister 2 of Multireg region_cfg_regwen
+ // R[region_cfg_regwen_2]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (region_cfg_regwen_2_we),
+ .wd (region_cfg_regwen_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_2_qs)
+ );
+
+ // Subregister 3 of Multireg region_cfg_regwen
+ // R[region_cfg_regwen_3]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (region_cfg_regwen_3_we),
+ .wd (region_cfg_regwen_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_3_qs)
+ );
+
+ // Subregister 4 of Multireg region_cfg_regwen
+ // R[region_cfg_regwen_4]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_4 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (region_cfg_regwen_4_we),
+ .wd (region_cfg_regwen_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_4_qs)
+ );
+
+ // Subregister 5 of Multireg region_cfg_regwen
+ // R[region_cfg_regwen_5]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_5 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (region_cfg_regwen_5_we),
+ .wd (region_cfg_regwen_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_5_qs)
+ );
+
+ // Subregister 6 of Multireg region_cfg_regwen
+ // R[region_cfg_regwen_6]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_6 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (region_cfg_regwen_6_we),
+ .wd (region_cfg_regwen_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_6_qs)
+ );
+
+ // Subregister 7 of Multireg region_cfg_regwen
+ // R[region_cfg_regwen_7]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_7 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (region_cfg_regwen_7_we),
+ .wd (region_cfg_regwen_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_7_qs)
+ );
+
+
+
+ // Subregister 0 of Multireg mp_region_cfg
+ // R[mp_region_cfg_0]: V(False)
+
+ // F[en_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_0_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_0_en_0_we & region_cfg_regwen_0_qs),
+ .wd (mp_region_cfg_0_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[0].en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_0_en_0_qs)
+ );
+
+
+ // F[rd_en_0]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_0_rd_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_0_rd_en_0_we & region_cfg_regwen_0_qs),
+ .wd (mp_region_cfg_0_rd_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[0].rd_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_0_rd_en_0_qs)
+ );
+
+
+ // F[prog_en_0]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_0_prog_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_0_prog_en_0_we & region_cfg_regwen_0_qs),
+ .wd (mp_region_cfg_0_prog_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[0].prog_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_0_prog_en_0_qs)
+ );
+
+
+ // F[erase_en_0]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_0_erase_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_0_erase_en_0_we & region_cfg_regwen_0_qs),
+ .wd (mp_region_cfg_0_erase_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[0].erase_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_0_erase_en_0_qs)
+ );
+
+
+ // F[scramble_en_0]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_0_scramble_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_0_scramble_en_0_we & region_cfg_regwen_0_qs),
+ .wd (mp_region_cfg_0_scramble_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[0].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_0_scramble_en_0_qs)
+ );
+
+
+ // F[base_0]: 16:8
+ prim_subreg #(
+ .DW (9),
+ .SWACCESS("RW"),
+ .RESVAL (9'h0)
+ ) u_mp_region_cfg_0_base_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_0_base_0_we & region_cfg_regwen_0_qs),
+ .wd (mp_region_cfg_0_base_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[0].base.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_0_base_0_qs)
+ );
+
+
+ // F[size_0]: 29:20
+ prim_subreg #(
+ .DW (10),
+ .SWACCESS("RW"),
+ .RESVAL (10'h0)
+ ) u_mp_region_cfg_0_size_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_0_size_0_we & region_cfg_regwen_0_qs),
+ .wd (mp_region_cfg_0_size_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[0].size.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_0_size_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg mp_region_cfg
+ // R[mp_region_cfg_1]: V(False)
+
+ // F[en_1]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_1_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_1_en_1_we & region_cfg_regwen_1_qs),
+ .wd (mp_region_cfg_1_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[1].en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_1_en_1_qs)
+ );
+
+
+ // F[rd_en_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_1_rd_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_1_rd_en_1_we & region_cfg_regwen_1_qs),
+ .wd (mp_region_cfg_1_rd_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[1].rd_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_1_rd_en_1_qs)
+ );
+
+
+ // F[prog_en_1]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_1_prog_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_1_prog_en_1_we & region_cfg_regwen_1_qs),
+ .wd (mp_region_cfg_1_prog_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[1].prog_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_1_prog_en_1_qs)
+ );
+
+
+ // F[erase_en_1]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_1_erase_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_1_erase_en_1_we & region_cfg_regwen_1_qs),
+ .wd (mp_region_cfg_1_erase_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[1].erase_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_1_erase_en_1_qs)
+ );
+
+
+ // F[scramble_en_1]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_1_scramble_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_1_scramble_en_1_we & region_cfg_regwen_1_qs),
+ .wd (mp_region_cfg_1_scramble_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[1].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_1_scramble_en_1_qs)
+ );
+
+
+ // F[base_1]: 16:8
+ prim_subreg #(
+ .DW (9),
+ .SWACCESS("RW"),
+ .RESVAL (9'h0)
+ ) u_mp_region_cfg_1_base_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_1_base_1_we & region_cfg_regwen_1_qs),
+ .wd (mp_region_cfg_1_base_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[1].base.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_1_base_1_qs)
+ );
+
+
+ // F[size_1]: 29:20
+ prim_subreg #(
+ .DW (10),
+ .SWACCESS("RW"),
+ .RESVAL (10'h0)
+ ) u_mp_region_cfg_1_size_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_1_size_1_we & region_cfg_regwen_1_qs),
+ .wd (mp_region_cfg_1_size_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[1].size.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_1_size_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg mp_region_cfg
+ // R[mp_region_cfg_2]: V(False)
+
+ // F[en_2]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_2_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_2_en_2_we & region_cfg_regwen_2_qs),
+ .wd (mp_region_cfg_2_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[2].en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_2_en_2_qs)
+ );
+
+
+ // F[rd_en_2]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_2_rd_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_2_rd_en_2_we & region_cfg_regwen_2_qs),
+ .wd (mp_region_cfg_2_rd_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[2].rd_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_2_rd_en_2_qs)
+ );
+
+
+ // F[prog_en_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_2_prog_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_2_prog_en_2_we & region_cfg_regwen_2_qs),
+ .wd (mp_region_cfg_2_prog_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[2].prog_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_2_prog_en_2_qs)
+ );
+
+
+ // F[erase_en_2]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_2_erase_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_2_erase_en_2_we & region_cfg_regwen_2_qs),
+ .wd (mp_region_cfg_2_erase_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[2].erase_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_2_erase_en_2_qs)
+ );
+
+
+ // F[scramble_en_2]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_2_scramble_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_2_scramble_en_2_we & region_cfg_regwen_2_qs),
+ .wd (mp_region_cfg_2_scramble_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[2].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_2_scramble_en_2_qs)
+ );
+
+
+ // F[base_2]: 16:8
+ prim_subreg #(
+ .DW (9),
+ .SWACCESS("RW"),
+ .RESVAL (9'h0)
+ ) u_mp_region_cfg_2_base_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_2_base_2_we & region_cfg_regwen_2_qs),
+ .wd (mp_region_cfg_2_base_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[2].base.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_2_base_2_qs)
+ );
+
+
+ // F[size_2]: 29:20
+ prim_subreg #(
+ .DW (10),
+ .SWACCESS("RW"),
+ .RESVAL (10'h0)
+ ) u_mp_region_cfg_2_size_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_2_size_2_we & region_cfg_regwen_2_qs),
+ .wd (mp_region_cfg_2_size_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[2].size.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_2_size_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg mp_region_cfg
+ // R[mp_region_cfg_3]: V(False)
+
+ // F[en_3]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_3_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_3_en_3_we & region_cfg_regwen_3_qs),
+ .wd (mp_region_cfg_3_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[3].en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_3_en_3_qs)
+ );
+
+
+ // F[rd_en_3]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_3_rd_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_3_rd_en_3_we & region_cfg_regwen_3_qs),
+ .wd (mp_region_cfg_3_rd_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[3].rd_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_3_rd_en_3_qs)
+ );
+
+
+ // F[prog_en_3]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_3_prog_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_3_prog_en_3_we & region_cfg_regwen_3_qs),
+ .wd (mp_region_cfg_3_prog_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[3].prog_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_3_prog_en_3_qs)
+ );
+
+
+ // F[erase_en_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_3_erase_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_3_erase_en_3_we & region_cfg_regwen_3_qs),
+ .wd (mp_region_cfg_3_erase_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[3].erase_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_3_erase_en_3_qs)
+ );
+
+
+ // F[scramble_en_3]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_3_scramble_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_3_scramble_en_3_we & region_cfg_regwen_3_qs),
+ .wd (mp_region_cfg_3_scramble_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[3].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_3_scramble_en_3_qs)
+ );
+
+
+ // F[base_3]: 16:8
+ prim_subreg #(
+ .DW (9),
+ .SWACCESS("RW"),
+ .RESVAL (9'h0)
+ ) u_mp_region_cfg_3_base_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_3_base_3_we & region_cfg_regwen_3_qs),
+ .wd (mp_region_cfg_3_base_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[3].base.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_3_base_3_qs)
+ );
+
+
+ // F[size_3]: 29:20
+ prim_subreg #(
+ .DW (10),
+ .SWACCESS("RW"),
+ .RESVAL (10'h0)
+ ) u_mp_region_cfg_3_size_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_3_size_3_we & region_cfg_regwen_3_qs),
+ .wd (mp_region_cfg_3_size_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[3].size.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_3_size_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg mp_region_cfg
+ // R[mp_region_cfg_4]: V(False)
+
+ // F[en_4]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_4_en_4 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_4_en_4_we & region_cfg_regwen_4_qs),
+ .wd (mp_region_cfg_4_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[4].en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_4_en_4_qs)
+ );
+
+
+ // F[rd_en_4]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_4_rd_en_4 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_4_rd_en_4_we & region_cfg_regwen_4_qs),
+ .wd (mp_region_cfg_4_rd_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[4].rd_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_4_rd_en_4_qs)
+ );
+
+
+ // F[prog_en_4]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_4_prog_en_4 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_4_prog_en_4_we & region_cfg_regwen_4_qs),
+ .wd (mp_region_cfg_4_prog_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[4].prog_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_4_prog_en_4_qs)
+ );
+
+
+ // F[erase_en_4]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_4_erase_en_4 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_4_erase_en_4_we & region_cfg_regwen_4_qs),
+ .wd (mp_region_cfg_4_erase_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[4].erase_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_4_erase_en_4_qs)
+ );
+
+
+ // F[scramble_en_4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_4_scramble_en_4 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_4_scramble_en_4_we & region_cfg_regwen_4_qs),
+ .wd (mp_region_cfg_4_scramble_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[4].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_4_scramble_en_4_qs)
+ );
+
+
+ // F[base_4]: 16:8
+ prim_subreg #(
+ .DW (9),
+ .SWACCESS("RW"),
+ .RESVAL (9'h0)
+ ) u_mp_region_cfg_4_base_4 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_4_base_4_we & region_cfg_regwen_4_qs),
+ .wd (mp_region_cfg_4_base_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[4].base.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_4_base_4_qs)
+ );
+
+
+ // F[size_4]: 29:20
+ prim_subreg #(
+ .DW (10),
+ .SWACCESS("RW"),
+ .RESVAL (10'h0)
+ ) u_mp_region_cfg_4_size_4 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_4_size_4_we & region_cfg_regwen_4_qs),
+ .wd (mp_region_cfg_4_size_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[4].size.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_4_size_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg mp_region_cfg
+ // R[mp_region_cfg_5]: V(False)
+
+ // F[en_5]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_5_en_5 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_5_en_5_we & region_cfg_regwen_5_qs),
+ .wd (mp_region_cfg_5_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[5].en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_5_en_5_qs)
+ );
+
+
+ // F[rd_en_5]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_5_rd_en_5 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_5_rd_en_5_we & region_cfg_regwen_5_qs),
+ .wd (mp_region_cfg_5_rd_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[5].rd_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_5_rd_en_5_qs)
+ );
+
+
+ // F[prog_en_5]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_5_prog_en_5 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_5_prog_en_5_we & region_cfg_regwen_5_qs),
+ .wd (mp_region_cfg_5_prog_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[5].prog_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_5_prog_en_5_qs)
+ );
+
+
+ // F[erase_en_5]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_5_erase_en_5 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_5_erase_en_5_we & region_cfg_regwen_5_qs),
+ .wd (mp_region_cfg_5_erase_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[5].erase_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_5_erase_en_5_qs)
+ );
+
+
+ // F[scramble_en_5]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_5_scramble_en_5 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_5_scramble_en_5_we & region_cfg_regwen_5_qs),
+ .wd (mp_region_cfg_5_scramble_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[5].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_5_scramble_en_5_qs)
+ );
+
+
+ // F[base_5]: 16:8
+ prim_subreg #(
+ .DW (9),
+ .SWACCESS("RW"),
+ .RESVAL (9'h0)
+ ) u_mp_region_cfg_5_base_5 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_5_base_5_we & region_cfg_regwen_5_qs),
+ .wd (mp_region_cfg_5_base_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[5].base.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_5_base_5_qs)
+ );
+
+
+ // F[size_5]: 29:20
+ prim_subreg #(
+ .DW (10),
+ .SWACCESS("RW"),
+ .RESVAL (10'h0)
+ ) u_mp_region_cfg_5_size_5 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_5_size_5_we & region_cfg_regwen_5_qs),
+ .wd (mp_region_cfg_5_size_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[5].size.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_5_size_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg mp_region_cfg
+ // R[mp_region_cfg_6]: V(False)
+
+ // F[en_6]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_6_en_6 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_6_en_6_we & region_cfg_regwen_6_qs),
+ .wd (mp_region_cfg_6_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[6].en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_6_en_6_qs)
+ );
+
+
+ // F[rd_en_6]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_6_rd_en_6 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_6_rd_en_6_we & region_cfg_regwen_6_qs),
+ .wd (mp_region_cfg_6_rd_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[6].rd_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_6_rd_en_6_qs)
+ );
+
+
+ // F[prog_en_6]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_6_prog_en_6 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_6_prog_en_6_we & region_cfg_regwen_6_qs),
+ .wd (mp_region_cfg_6_prog_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[6].prog_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_6_prog_en_6_qs)
+ );
+
+
+ // F[erase_en_6]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_6_erase_en_6 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_6_erase_en_6_we & region_cfg_regwen_6_qs),
+ .wd (mp_region_cfg_6_erase_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[6].erase_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_6_erase_en_6_qs)
+ );
+
+
+ // F[scramble_en_6]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_6_scramble_en_6 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_6_scramble_en_6_we & region_cfg_regwen_6_qs),
+ .wd (mp_region_cfg_6_scramble_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[6].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_6_scramble_en_6_qs)
+ );
+
+
+ // F[base_6]: 16:8
+ prim_subreg #(
+ .DW (9),
+ .SWACCESS("RW"),
+ .RESVAL (9'h0)
+ ) u_mp_region_cfg_6_base_6 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_6_base_6_we & region_cfg_regwen_6_qs),
+ .wd (mp_region_cfg_6_base_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[6].base.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_6_base_6_qs)
+ );
+
+
+ // F[size_6]: 29:20
+ prim_subreg #(
+ .DW (10),
+ .SWACCESS("RW"),
+ .RESVAL (10'h0)
+ ) u_mp_region_cfg_6_size_6 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_6_size_6_we & region_cfg_regwen_6_qs),
+ .wd (mp_region_cfg_6_size_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[6].size.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_6_size_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg mp_region_cfg
+ // R[mp_region_cfg_7]: V(False)
+
+ // F[en_7]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_7_en_7 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_7_en_7_we & region_cfg_regwen_7_qs),
+ .wd (mp_region_cfg_7_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[7].en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_7_en_7_qs)
+ );
+
+
+ // F[rd_en_7]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_7_rd_en_7 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_7_rd_en_7_we & region_cfg_regwen_7_qs),
+ .wd (mp_region_cfg_7_rd_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[7].rd_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_7_rd_en_7_qs)
+ );
+
+
+ // F[prog_en_7]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_7_prog_en_7 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_7_prog_en_7_we & region_cfg_regwen_7_qs),
+ .wd (mp_region_cfg_7_prog_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[7].prog_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_7_prog_en_7_qs)
+ );
+
+
+ // F[erase_en_7]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_7_erase_en_7 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_7_erase_en_7_we & region_cfg_regwen_7_qs),
+ .wd (mp_region_cfg_7_erase_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[7].erase_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_7_erase_en_7_qs)
+ );
+
+
+ // F[scramble_en_7]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_7_scramble_en_7 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_7_scramble_en_7_we & region_cfg_regwen_7_qs),
+ .wd (mp_region_cfg_7_scramble_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[7].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_7_scramble_en_7_qs)
+ );
+
+
+ // F[base_7]: 16:8
+ prim_subreg #(
+ .DW (9),
+ .SWACCESS("RW"),
+ .RESVAL (9'h0)
+ ) u_mp_region_cfg_7_base_7 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_7_base_7_we & region_cfg_regwen_7_qs),
+ .wd (mp_region_cfg_7_base_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[7].base.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_7_base_7_qs)
+ );
+
+
+ // F[size_7]: 29:20
+ prim_subreg #(
+ .DW (10),
+ .SWACCESS("RW"),
+ .RESVAL (10'h0)
+ ) u_mp_region_cfg_7_size_7 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_7_size_7_we & region_cfg_regwen_7_qs),
+ .wd (mp_region_cfg_7_size_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[7].size.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_7_size_7_qs)
+ );
+
+
+
+ // R[default_region]: V(False)
+
+ // F[rd_en]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_default_region_rd_en (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (default_region_rd_en_we),
+ .wd (default_region_rd_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.default_region.rd_en.q ),
+
+ // to register interface (read)
+ .qs (default_region_rd_en_qs)
+ );
+
+
+ // F[prog_en]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_default_region_prog_en (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (default_region_prog_en_we),
+ .wd (default_region_prog_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.default_region.prog_en.q ),
+
+ // to register interface (read)
+ .qs (default_region_prog_en_qs)
+ );
+
+
+ // F[erase_en]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_default_region_erase_en (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (default_region_erase_en_we),
+ .wd (default_region_erase_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.default_region.erase_en.q ),
+
+ // to register interface (read)
+ .qs (default_region_erase_en_qs)
+ );
+
+
+ // F[scramble_en]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_default_region_scramble_en (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (default_region_scramble_en_we),
+ .wd (default_region_scramble_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.default_region.scramble_en.q ),
+
+ // to register interface (read)
+ .qs (default_region_scramble_en_qs)
+ );
+
+
+
+ // Subregister 0 of Multireg bank0_info0_regwen
+ // R[bank0_info0_regwen_0]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_bank0_info0_regwen_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (bank0_info0_regwen_0_we),
+ .wd (bank0_info0_regwen_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (bank0_info0_regwen_0_qs)
+ );
+
+ // Subregister 1 of Multireg bank0_info0_regwen
+ // R[bank0_info0_regwen_1]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_bank0_info0_regwen_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (bank0_info0_regwen_1_we),
+ .wd (bank0_info0_regwen_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (bank0_info0_regwen_1_qs)
+ );
+
+ // Subregister 2 of Multireg bank0_info0_regwen
+ // R[bank0_info0_regwen_2]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_bank0_info0_regwen_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (bank0_info0_regwen_2_we),
+ .wd (bank0_info0_regwen_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (bank0_info0_regwen_2_qs)
+ );
+
+ // Subregister 3 of Multireg bank0_info0_regwen
+ // R[bank0_info0_regwen_3]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_bank0_info0_regwen_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (bank0_info0_regwen_3_we),
+ .wd (bank0_info0_regwen_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (bank0_info0_regwen_3_qs)
+ );
+
+
+
+ // Subregister 0 of Multireg bank0_info0_page_cfg
+ // R[bank0_info0_page_cfg_0]: V(False)
+
+ // F[en_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_0_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_0_en_0_we & bank0_info0_regwen_0_qs),
+ .wd (bank0_info0_page_cfg_0_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[0].en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_0_en_0_qs)
+ );
+
+
+ // F[rd_en_0]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_0_rd_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_0_rd_en_0_we & bank0_info0_regwen_0_qs),
+ .wd (bank0_info0_page_cfg_0_rd_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[0].rd_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_0_rd_en_0_qs)
+ );
+
+
+ // F[prog_en_0]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_0_prog_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_0_prog_en_0_we & bank0_info0_regwen_0_qs),
+ .wd (bank0_info0_page_cfg_0_prog_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[0].prog_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_0_prog_en_0_qs)
+ );
+
+
+ // F[erase_en_0]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_0_erase_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_0_erase_en_0_we & bank0_info0_regwen_0_qs),
+ .wd (bank0_info0_page_cfg_0_erase_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[0].erase_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_0_erase_en_0_qs)
+ );
+
+
+ // F[scramble_en_0]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_0_scramble_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_0_scramble_en_0_we & bank0_info0_regwen_0_qs),
+ .wd (bank0_info0_page_cfg_0_scramble_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[0].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_0_scramble_en_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg bank0_info0_page_cfg
+ // R[bank0_info0_page_cfg_1]: V(False)
+
+ // F[en_1]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_1_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_1_en_1_we & bank0_info0_regwen_1_qs),
+ .wd (bank0_info0_page_cfg_1_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[1].en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_1_en_1_qs)
+ );
+
+
+ // F[rd_en_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_1_rd_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_1_rd_en_1_we & bank0_info0_regwen_1_qs),
+ .wd (bank0_info0_page_cfg_1_rd_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[1].rd_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_1_rd_en_1_qs)
+ );
+
+
+ // F[prog_en_1]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_1_prog_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_1_prog_en_1_we & bank0_info0_regwen_1_qs),
+ .wd (bank0_info0_page_cfg_1_prog_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[1].prog_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_1_prog_en_1_qs)
+ );
+
+
+ // F[erase_en_1]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_1_erase_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_1_erase_en_1_we & bank0_info0_regwen_1_qs),
+ .wd (bank0_info0_page_cfg_1_erase_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[1].erase_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_1_erase_en_1_qs)
+ );
+
+
+ // F[scramble_en_1]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_1_scramble_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_1_scramble_en_1_we & bank0_info0_regwen_1_qs),
+ .wd (bank0_info0_page_cfg_1_scramble_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[1].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_1_scramble_en_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg bank0_info0_page_cfg
+ // R[bank0_info0_page_cfg_2]: V(False)
+
+ // F[en_2]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_2_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_2_en_2_we & bank0_info0_regwen_2_qs),
+ .wd (bank0_info0_page_cfg_2_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[2].en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_2_en_2_qs)
+ );
+
+
+ // F[rd_en_2]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_2_rd_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_2_rd_en_2_we & bank0_info0_regwen_2_qs),
+ .wd (bank0_info0_page_cfg_2_rd_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[2].rd_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_2_rd_en_2_qs)
+ );
+
+
+ // F[prog_en_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_2_prog_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_2_prog_en_2_we & bank0_info0_regwen_2_qs),
+ .wd (bank0_info0_page_cfg_2_prog_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[2].prog_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_2_prog_en_2_qs)
+ );
+
+
+ // F[erase_en_2]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_2_erase_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_2_erase_en_2_we & bank0_info0_regwen_2_qs),
+ .wd (bank0_info0_page_cfg_2_erase_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[2].erase_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_2_erase_en_2_qs)
+ );
+
+
+ // F[scramble_en_2]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_2_scramble_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_2_scramble_en_2_we & bank0_info0_regwen_2_qs),
+ .wd (bank0_info0_page_cfg_2_scramble_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[2].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_2_scramble_en_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg bank0_info0_page_cfg
+ // R[bank0_info0_page_cfg_3]: V(False)
+
+ // F[en_3]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_3_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_3_en_3_we & bank0_info0_regwen_3_qs),
+ .wd (bank0_info0_page_cfg_3_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[3].en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_3_en_3_qs)
+ );
+
+
+ // F[rd_en_3]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_3_rd_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_3_rd_en_3_we & bank0_info0_regwen_3_qs),
+ .wd (bank0_info0_page_cfg_3_rd_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[3].rd_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_3_rd_en_3_qs)
+ );
+
+
+ // F[prog_en_3]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_3_prog_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_3_prog_en_3_we & bank0_info0_regwen_3_qs),
+ .wd (bank0_info0_page_cfg_3_prog_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[3].prog_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_3_prog_en_3_qs)
+ );
+
+
+ // F[erase_en_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_3_erase_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_3_erase_en_3_we & bank0_info0_regwen_3_qs),
+ .wd (bank0_info0_page_cfg_3_erase_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[3].erase_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_3_erase_en_3_qs)
+ );
+
+
+ // F[scramble_en_3]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_3_scramble_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_3_scramble_en_3_we & bank0_info0_regwen_3_qs),
+ .wd (bank0_info0_page_cfg_3_scramble_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[3].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_3_scramble_en_3_qs)
+ );
+
+
+
+
+ // Subregister 0 of Multireg bank0_info1_regwen
+ // R[bank0_info1_regwen_0]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_bank0_info1_regwen_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (bank0_info1_regwen_0_we),
+ .wd (bank0_info1_regwen_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (bank0_info1_regwen_0_qs)
+ );
+
+ // Subregister 1 of Multireg bank0_info1_regwen
+ // R[bank0_info1_regwen_1]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_bank0_info1_regwen_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (bank0_info1_regwen_1_we),
+ .wd (bank0_info1_regwen_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (bank0_info1_regwen_1_qs)
+ );
+
+ // Subregister 2 of Multireg bank0_info1_regwen
+ // R[bank0_info1_regwen_2]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_bank0_info1_regwen_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (bank0_info1_regwen_2_we),
+ .wd (bank0_info1_regwen_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (bank0_info1_regwen_2_qs)
+ );
+
+ // Subregister 3 of Multireg bank0_info1_regwen
+ // R[bank0_info1_regwen_3]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_bank0_info1_regwen_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (bank0_info1_regwen_3_we),
+ .wd (bank0_info1_regwen_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (bank0_info1_regwen_3_qs)
+ );
+
+
+
+ // Subregister 0 of Multireg bank0_info1_page_cfg
+ // R[bank0_info1_page_cfg_0]: V(False)
+
+ // F[en_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_0_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_0_en_0_we & bank0_info1_regwen_0_qs),
+ .wd (bank0_info1_page_cfg_0_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[0].en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_0_en_0_qs)
+ );
+
+
+ // F[rd_en_0]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_0_rd_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_0_rd_en_0_we & bank0_info1_regwen_0_qs),
+ .wd (bank0_info1_page_cfg_0_rd_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[0].rd_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_0_rd_en_0_qs)
+ );
+
+
+ // F[prog_en_0]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_0_prog_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_0_prog_en_0_we & bank0_info1_regwen_0_qs),
+ .wd (bank0_info1_page_cfg_0_prog_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[0].prog_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_0_prog_en_0_qs)
+ );
+
+
+ // F[erase_en_0]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_0_erase_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_0_erase_en_0_we & bank0_info1_regwen_0_qs),
+ .wd (bank0_info1_page_cfg_0_erase_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[0].erase_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_0_erase_en_0_qs)
+ );
+
+
+ // F[scramble_en_0]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_0_scramble_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_0_scramble_en_0_we & bank0_info1_regwen_0_qs),
+ .wd (bank0_info1_page_cfg_0_scramble_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[0].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_0_scramble_en_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg bank0_info1_page_cfg
+ // R[bank0_info1_page_cfg_1]: V(False)
+
+ // F[en_1]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_1_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_1_en_1_we & bank0_info1_regwen_1_qs),
+ .wd (bank0_info1_page_cfg_1_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[1].en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_1_en_1_qs)
+ );
+
+
+ // F[rd_en_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_1_rd_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_1_rd_en_1_we & bank0_info1_regwen_1_qs),
+ .wd (bank0_info1_page_cfg_1_rd_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[1].rd_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_1_rd_en_1_qs)
+ );
+
+
+ // F[prog_en_1]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_1_prog_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_1_prog_en_1_we & bank0_info1_regwen_1_qs),
+ .wd (bank0_info1_page_cfg_1_prog_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[1].prog_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_1_prog_en_1_qs)
+ );
+
+
+ // F[erase_en_1]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_1_erase_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_1_erase_en_1_we & bank0_info1_regwen_1_qs),
+ .wd (bank0_info1_page_cfg_1_erase_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[1].erase_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_1_erase_en_1_qs)
+ );
+
+
+ // F[scramble_en_1]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_1_scramble_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_1_scramble_en_1_we & bank0_info1_regwen_1_qs),
+ .wd (bank0_info1_page_cfg_1_scramble_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[1].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_1_scramble_en_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg bank0_info1_page_cfg
+ // R[bank0_info1_page_cfg_2]: V(False)
+
+ // F[en_2]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_2_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_2_en_2_we & bank0_info1_regwen_2_qs),
+ .wd (bank0_info1_page_cfg_2_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[2].en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_2_en_2_qs)
+ );
+
+
+ // F[rd_en_2]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_2_rd_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_2_rd_en_2_we & bank0_info1_regwen_2_qs),
+ .wd (bank0_info1_page_cfg_2_rd_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[2].rd_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_2_rd_en_2_qs)
+ );
+
+
+ // F[prog_en_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_2_prog_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_2_prog_en_2_we & bank0_info1_regwen_2_qs),
+ .wd (bank0_info1_page_cfg_2_prog_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[2].prog_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_2_prog_en_2_qs)
+ );
+
+
+ // F[erase_en_2]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_2_erase_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_2_erase_en_2_we & bank0_info1_regwen_2_qs),
+ .wd (bank0_info1_page_cfg_2_erase_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[2].erase_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_2_erase_en_2_qs)
+ );
+
+
+ // F[scramble_en_2]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_2_scramble_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_2_scramble_en_2_we & bank0_info1_regwen_2_qs),
+ .wd (bank0_info1_page_cfg_2_scramble_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[2].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_2_scramble_en_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg bank0_info1_page_cfg
+ // R[bank0_info1_page_cfg_3]: V(False)
+
+ // F[en_3]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_3_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_3_en_3_we & bank0_info1_regwen_3_qs),
+ .wd (bank0_info1_page_cfg_3_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[3].en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_3_en_3_qs)
+ );
+
+
+ // F[rd_en_3]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_3_rd_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_3_rd_en_3_we & bank0_info1_regwen_3_qs),
+ .wd (bank0_info1_page_cfg_3_rd_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[3].rd_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_3_rd_en_3_qs)
+ );
+
+
+ // F[prog_en_3]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_3_prog_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_3_prog_en_3_we & bank0_info1_regwen_3_qs),
+ .wd (bank0_info1_page_cfg_3_prog_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[3].prog_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_3_prog_en_3_qs)
+ );
+
+
+ // F[erase_en_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_3_erase_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_3_erase_en_3_we & bank0_info1_regwen_3_qs),
+ .wd (bank0_info1_page_cfg_3_erase_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[3].erase_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_3_erase_en_3_qs)
+ );
+
+
+ // F[scramble_en_3]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_3_scramble_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_3_scramble_en_3_we & bank0_info1_regwen_3_qs),
+ .wd (bank0_info1_page_cfg_3_scramble_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[3].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_3_scramble_en_3_qs)
+ );
+
+
+
+
+ // Subregister 0 of Multireg bank1_info0_regwen
+ // R[bank1_info0_regwen_0]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_bank1_info0_regwen_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (bank1_info0_regwen_0_we),
+ .wd (bank1_info0_regwen_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (bank1_info0_regwen_0_qs)
+ );
+
+ // Subregister 1 of Multireg bank1_info0_regwen
+ // R[bank1_info0_regwen_1]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_bank1_info0_regwen_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (bank1_info0_regwen_1_we),
+ .wd (bank1_info0_regwen_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (bank1_info0_regwen_1_qs)
+ );
+
+ // Subregister 2 of Multireg bank1_info0_regwen
+ // R[bank1_info0_regwen_2]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_bank1_info0_regwen_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (bank1_info0_regwen_2_we),
+ .wd (bank1_info0_regwen_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (bank1_info0_regwen_2_qs)
+ );
+
+ // Subregister 3 of Multireg bank1_info0_regwen
+ // R[bank1_info0_regwen_3]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_bank1_info0_regwen_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (bank1_info0_regwen_3_we),
+ .wd (bank1_info0_regwen_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (bank1_info0_regwen_3_qs)
+ );
+
+
+
+ // Subregister 0 of Multireg bank1_info0_page_cfg
+ // R[bank1_info0_page_cfg_0]: V(False)
+
+ // F[en_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_0_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_0_en_0_we & bank1_info0_regwen_0_qs),
+ .wd (bank1_info0_page_cfg_0_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[0].en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_0_en_0_qs)
+ );
+
+
+ // F[rd_en_0]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_0_rd_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_0_rd_en_0_we & bank1_info0_regwen_0_qs),
+ .wd (bank1_info0_page_cfg_0_rd_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[0].rd_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_0_rd_en_0_qs)
+ );
+
+
+ // F[prog_en_0]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_0_prog_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_0_prog_en_0_we & bank1_info0_regwen_0_qs),
+ .wd (bank1_info0_page_cfg_0_prog_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[0].prog_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_0_prog_en_0_qs)
+ );
+
+
+ // F[erase_en_0]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_0_erase_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_0_erase_en_0_we & bank1_info0_regwen_0_qs),
+ .wd (bank1_info0_page_cfg_0_erase_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[0].erase_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_0_erase_en_0_qs)
+ );
+
+
+ // F[scramble_en_0]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_0_scramble_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_0_scramble_en_0_we & bank1_info0_regwen_0_qs),
+ .wd (bank1_info0_page_cfg_0_scramble_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[0].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_0_scramble_en_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg bank1_info0_page_cfg
+ // R[bank1_info0_page_cfg_1]: V(False)
+
+ // F[en_1]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_1_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_1_en_1_we & bank1_info0_regwen_1_qs),
+ .wd (bank1_info0_page_cfg_1_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[1].en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_1_en_1_qs)
+ );
+
+
+ // F[rd_en_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_1_rd_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_1_rd_en_1_we & bank1_info0_regwen_1_qs),
+ .wd (bank1_info0_page_cfg_1_rd_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[1].rd_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_1_rd_en_1_qs)
+ );
+
+
+ // F[prog_en_1]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_1_prog_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_1_prog_en_1_we & bank1_info0_regwen_1_qs),
+ .wd (bank1_info0_page_cfg_1_prog_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[1].prog_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_1_prog_en_1_qs)
+ );
+
+
+ // F[erase_en_1]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_1_erase_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_1_erase_en_1_we & bank1_info0_regwen_1_qs),
+ .wd (bank1_info0_page_cfg_1_erase_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[1].erase_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_1_erase_en_1_qs)
+ );
+
+
+ // F[scramble_en_1]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_1_scramble_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_1_scramble_en_1_we & bank1_info0_regwen_1_qs),
+ .wd (bank1_info0_page_cfg_1_scramble_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[1].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_1_scramble_en_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg bank1_info0_page_cfg
+ // R[bank1_info0_page_cfg_2]: V(False)
+
+ // F[en_2]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_2_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_2_en_2_we & bank1_info0_regwen_2_qs),
+ .wd (bank1_info0_page_cfg_2_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[2].en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_2_en_2_qs)
+ );
+
+
+ // F[rd_en_2]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_2_rd_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_2_rd_en_2_we & bank1_info0_regwen_2_qs),
+ .wd (bank1_info0_page_cfg_2_rd_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[2].rd_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_2_rd_en_2_qs)
+ );
+
+
+ // F[prog_en_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_2_prog_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_2_prog_en_2_we & bank1_info0_regwen_2_qs),
+ .wd (bank1_info0_page_cfg_2_prog_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[2].prog_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_2_prog_en_2_qs)
+ );
+
+
+ // F[erase_en_2]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_2_erase_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_2_erase_en_2_we & bank1_info0_regwen_2_qs),
+ .wd (bank1_info0_page_cfg_2_erase_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[2].erase_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_2_erase_en_2_qs)
+ );
+
+
+ // F[scramble_en_2]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_2_scramble_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_2_scramble_en_2_we & bank1_info0_regwen_2_qs),
+ .wd (bank1_info0_page_cfg_2_scramble_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[2].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_2_scramble_en_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg bank1_info0_page_cfg
+ // R[bank1_info0_page_cfg_3]: V(False)
+
+ // F[en_3]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_3_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_3_en_3_we & bank1_info0_regwen_3_qs),
+ .wd (bank1_info0_page_cfg_3_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[3].en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_3_en_3_qs)
+ );
+
+
+ // F[rd_en_3]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_3_rd_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_3_rd_en_3_we & bank1_info0_regwen_3_qs),
+ .wd (bank1_info0_page_cfg_3_rd_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[3].rd_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_3_rd_en_3_qs)
+ );
+
+
+ // F[prog_en_3]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_3_prog_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_3_prog_en_3_we & bank1_info0_regwen_3_qs),
+ .wd (bank1_info0_page_cfg_3_prog_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[3].prog_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_3_prog_en_3_qs)
+ );
+
+
+ // F[erase_en_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_3_erase_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_3_erase_en_3_we & bank1_info0_regwen_3_qs),
+ .wd (bank1_info0_page_cfg_3_erase_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[3].erase_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_3_erase_en_3_qs)
+ );
+
+
+ // F[scramble_en_3]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_3_scramble_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_3_scramble_en_3_we & bank1_info0_regwen_3_qs),
+ .wd (bank1_info0_page_cfg_3_scramble_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[3].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_3_scramble_en_3_qs)
+ );
+
+
+
+
+ // Subregister 0 of Multireg bank1_info1_regwen
+ // R[bank1_info1_regwen_0]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_bank1_info1_regwen_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (bank1_info1_regwen_0_we),
+ .wd (bank1_info1_regwen_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (bank1_info1_regwen_0_qs)
+ );
+
+ // Subregister 1 of Multireg bank1_info1_regwen
+ // R[bank1_info1_regwen_1]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_bank1_info1_regwen_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (bank1_info1_regwen_1_we),
+ .wd (bank1_info1_regwen_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (bank1_info1_regwen_1_qs)
+ );
+
+ // Subregister 2 of Multireg bank1_info1_regwen
+ // R[bank1_info1_regwen_2]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_bank1_info1_regwen_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (bank1_info1_regwen_2_we),
+ .wd (bank1_info1_regwen_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (bank1_info1_regwen_2_qs)
+ );
+
+ // Subregister 3 of Multireg bank1_info1_regwen
+ // R[bank1_info1_regwen_3]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_bank1_info1_regwen_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (bank1_info1_regwen_3_we),
+ .wd (bank1_info1_regwen_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (bank1_info1_regwen_3_qs)
+ );
+
+
+
+ // Subregister 0 of Multireg bank1_info1_page_cfg
+ // R[bank1_info1_page_cfg_0]: V(False)
+
+ // F[en_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_0_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_0_en_0_we & bank1_info1_regwen_0_qs),
+ .wd (bank1_info1_page_cfg_0_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[0].en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_0_en_0_qs)
+ );
+
+
+ // F[rd_en_0]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_0_rd_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_0_rd_en_0_we & bank1_info1_regwen_0_qs),
+ .wd (bank1_info1_page_cfg_0_rd_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[0].rd_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_0_rd_en_0_qs)
+ );
+
+
+ // F[prog_en_0]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_0_prog_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_0_prog_en_0_we & bank1_info1_regwen_0_qs),
+ .wd (bank1_info1_page_cfg_0_prog_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[0].prog_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_0_prog_en_0_qs)
+ );
+
+
+ // F[erase_en_0]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_0_erase_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_0_erase_en_0_we & bank1_info1_regwen_0_qs),
+ .wd (bank1_info1_page_cfg_0_erase_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[0].erase_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_0_erase_en_0_qs)
+ );
+
+
+ // F[scramble_en_0]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_0_scramble_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_0_scramble_en_0_we & bank1_info1_regwen_0_qs),
+ .wd (bank1_info1_page_cfg_0_scramble_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[0].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_0_scramble_en_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg bank1_info1_page_cfg
+ // R[bank1_info1_page_cfg_1]: V(False)
+
+ // F[en_1]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_1_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_1_en_1_we & bank1_info1_regwen_1_qs),
+ .wd (bank1_info1_page_cfg_1_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[1].en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_1_en_1_qs)
+ );
+
+
+ // F[rd_en_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_1_rd_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_1_rd_en_1_we & bank1_info1_regwen_1_qs),
+ .wd (bank1_info1_page_cfg_1_rd_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[1].rd_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_1_rd_en_1_qs)
+ );
+
+
+ // F[prog_en_1]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_1_prog_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_1_prog_en_1_we & bank1_info1_regwen_1_qs),
+ .wd (bank1_info1_page_cfg_1_prog_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[1].prog_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_1_prog_en_1_qs)
+ );
+
+
+ // F[erase_en_1]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_1_erase_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_1_erase_en_1_we & bank1_info1_regwen_1_qs),
+ .wd (bank1_info1_page_cfg_1_erase_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[1].erase_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_1_erase_en_1_qs)
+ );
+
+
+ // F[scramble_en_1]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_1_scramble_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_1_scramble_en_1_we & bank1_info1_regwen_1_qs),
+ .wd (bank1_info1_page_cfg_1_scramble_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[1].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_1_scramble_en_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg bank1_info1_page_cfg
+ // R[bank1_info1_page_cfg_2]: V(False)
+
+ // F[en_2]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_2_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_2_en_2_we & bank1_info1_regwen_2_qs),
+ .wd (bank1_info1_page_cfg_2_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[2].en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_2_en_2_qs)
+ );
+
+
+ // F[rd_en_2]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_2_rd_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_2_rd_en_2_we & bank1_info1_regwen_2_qs),
+ .wd (bank1_info1_page_cfg_2_rd_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[2].rd_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_2_rd_en_2_qs)
+ );
+
+
+ // F[prog_en_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_2_prog_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_2_prog_en_2_we & bank1_info1_regwen_2_qs),
+ .wd (bank1_info1_page_cfg_2_prog_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[2].prog_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_2_prog_en_2_qs)
+ );
+
+
+ // F[erase_en_2]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_2_erase_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_2_erase_en_2_we & bank1_info1_regwen_2_qs),
+ .wd (bank1_info1_page_cfg_2_erase_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[2].erase_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_2_erase_en_2_qs)
+ );
+
+
+ // F[scramble_en_2]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_2_scramble_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_2_scramble_en_2_we & bank1_info1_regwen_2_qs),
+ .wd (bank1_info1_page_cfg_2_scramble_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[2].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_2_scramble_en_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg bank1_info1_page_cfg
+ // R[bank1_info1_page_cfg_3]: V(False)
+
+ // F[en_3]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_3_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_3_en_3_we & bank1_info1_regwen_3_qs),
+ .wd (bank1_info1_page_cfg_3_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[3].en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_3_en_3_qs)
+ );
+
+
+ // F[rd_en_3]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_3_rd_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_3_rd_en_3_we & bank1_info1_regwen_3_qs),
+ .wd (bank1_info1_page_cfg_3_rd_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[3].rd_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_3_rd_en_3_qs)
+ );
+
+
+ // F[prog_en_3]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_3_prog_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_3_prog_en_3_we & bank1_info1_regwen_3_qs),
+ .wd (bank1_info1_page_cfg_3_prog_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[3].prog_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_3_prog_en_3_qs)
+ );
+
+
+ // F[erase_en_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_3_erase_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_3_erase_en_3_we & bank1_info1_regwen_3_qs),
+ .wd (bank1_info1_page_cfg_3_erase_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[3].erase_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_3_erase_en_3_qs)
+ );
+
+
+ // F[scramble_en_3]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_3_scramble_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_3_scramble_en_3_we & bank1_info1_regwen_3_qs),
+ .wd (bank1_info1_page_cfg_3_scramble_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[3].scramble_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_3_scramble_en_3_qs)
+ );
+
+
+
+ // R[bank_cfg_regwen]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_bank_cfg_regwen (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (bank_cfg_regwen_we),
+ .wd (bank_cfg_regwen_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (bank_cfg_regwen_qs)
+ );
+
+
+
+ // Subregister 0 of Multireg mp_bank_cfg
+ // R[mp_bank_cfg]: V(False)
+
+ // F[erase_en_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_bank_cfg_erase_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_bank_cfg_erase_en_0_we & bank_cfg_regwen_qs),
+ .wd (mp_bank_cfg_erase_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_bank_cfg[0].q ),
+
+ // to register interface (read)
+ .qs (mp_bank_cfg_erase_en_0_qs)
+ );
+
+
+ // F[erase_en_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_bank_cfg_erase_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_bank_cfg_erase_en_1_we & bank_cfg_regwen_qs),
+ .wd (mp_bank_cfg_erase_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_bank_cfg[1].q ),
+
+ // to register interface (read)
+ .qs (mp_bank_cfg_erase_en_1_qs)
+ );
+
+
+
+ // R[op_status]: V(False)
+
+ // F[done]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_op_status_done (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (op_status_done_we),
+ .wd (op_status_done_wd),
+
+ // from internal hardware
+ .de (hw2reg.op_status.done.de),
+ .d (hw2reg.op_status.done.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (op_status_done_qs)
+ );
+
+
+ // F[err]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_op_status_err (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (op_status_err_we),
+ .wd (op_status_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.op_status.err.de),
+ .d (hw2reg.op_status.err.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (op_status_err_qs)
+ );
+
+
+ // R[status]: V(False)
+
+ // F[rd_full]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_status_rd_full (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.status.rd_full.de),
+ .d (hw2reg.status.rd_full.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (status_rd_full_qs)
+ );
+
+
+ // F[rd_empty]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h1)
+ ) u_status_rd_empty (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.status.rd_empty.de),
+ .d (hw2reg.status.rd_empty.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (status_rd_empty_qs)
+ );
+
+
+ // F[prog_full]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_status_prog_full (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.status.prog_full.de),
+ .d (hw2reg.status.prog_full.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (status_prog_full_qs)
+ );
+
+
+ // F[prog_empty]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h1)
+ ) u_status_prog_empty (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.status.prog_empty.de),
+ .d (hw2reg.status.prog_empty.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (status_prog_empty_qs)
+ );
+
+
+ // F[init_wip]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_status_init_wip (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.status.init_wip.de),
+ .d (hw2reg.status.init_wip.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (status_init_wip_qs)
+ );
+
+
+ // F[error_addr]: 16:8
+ prim_subreg #(
+ .DW (9),
+ .SWACCESS("RO"),
+ .RESVAL (9'h0)
+ ) u_status_error_addr (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.status.error_addr.de),
+ .d (hw2reg.status.error_addr.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (status_error_addr_qs)
+ );
+
+
+ // R[phy_status]: V(False)
+
+ // F[init_wip]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_phy_status_init_wip (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.phy_status.init_wip.de),
+ .d (hw2reg.phy_status.init_wip.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (phy_status_init_wip_qs)
+ );
+
+
+ // F[prog_normal_avail]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h1)
+ ) u_phy_status_prog_normal_avail (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.phy_status.prog_normal_avail.de),
+ .d (hw2reg.phy_status.prog_normal_avail.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (phy_status_prog_normal_avail_qs)
+ );
+
+
+ // F[prog_repair_avail]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h1)
+ ) u_phy_status_prog_repair_avail (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.phy_status.prog_repair_avail.de),
+ .d (hw2reg.phy_status.prog_repair_avail.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (phy_status_prog_repair_avail_qs)
+ );
+
+
+ // R[scratch]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_scratch (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (scratch_we),
+ .wd (scratch_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.scratch.q ),
+
+ // to register interface (read)
+ .qs (scratch_qs)
+ );
+
+
+ // R[fifo_lvl]: V(False)
+
+ // F[prog]: 4:0
+ prim_subreg #(
+ .DW (5),
+ .SWACCESS("RW"),
+ .RESVAL (5'hf)
+ ) u_fifo_lvl_prog (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (fifo_lvl_prog_we),
+ .wd (fifo_lvl_prog_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fifo_lvl.prog.q ),
+
+ // to register interface (read)
+ .qs (fifo_lvl_prog_qs)
+ );
+
+
+ // F[rd]: 12:8
+ prim_subreg #(
+ .DW (5),
+ .SWACCESS("RW"),
+ .RESVAL (5'hf)
+ ) u_fifo_lvl_rd (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (fifo_lvl_rd_we),
+ .wd (fifo_lvl_rd_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fifo_lvl.rd.q ),
+
+ // to register interface (read)
+ .qs (fifo_lvl_rd_qs)
+ );
+
+
+ // R[fifo_rst]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_fifo_rst (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (fifo_rst_we),
+ .wd (fifo_rst_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fifo_rst.q ),
+
+ // to register interface (read)
+ .qs (fifo_rst_qs)
+ );
+
+
+
+
+ logic [62:0] addr_hit;
+ always_comb begin
+ addr_hit = '0;
+ addr_hit[ 0] = (reg_addr == FLASH_CTRL_INTR_STATE_OFFSET);
+ addr_hit[ 1] = (reg_addr == FLASH_CTRL_INTR_ENABLE_OFFSET);
+ addr_hit[ 2] = (reg_addr == FLASH_CTRL_INTR_TEST_OFFSET);
+ addr_hit[ 3] = (reg_addr == FLASH_CTRL_CTRL_REGWEN_OFFSET);
+ addr_hit[ 4] = (reg_addr == FLASH_CTRL_CONTROL_OFFSET);
+ addr_hit[ 5] = (reg_addr == FLASH_CTRL_ADDR_OFFSET);
+ addr_hit[ 6] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET);
+ addr_hit[ 7] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET);
+ addr_hit[ 8] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET);
+ addr_hit[ 9] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET);
+ addr_hit[10] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET);
+ addr_hit[11] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET);
+ addr_hit[12] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET);
+ addr_hit[13] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET);
+ addr_hit[14] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_0_OFFSET);
+ addr_hit[15] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_1_OFFSET);
+ addr_hit[16] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_2_OFFSET);
+ addr_hit[17] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_3_OFFSET);
+ addr_hit[18] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_4_OFFSET);
+ addr_hit[19] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_5_OFFSET);
+ addr_hit[20] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_6_OFFSET);
+ addr_hit[21] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_7_OFFSET);
+ addr_hit[22] = (reg_addr == FLASH_CTRL_DEFAULT_REGION_OFFSET);
+ addr_hit[23] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET);
+ addr_hit[24] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET);
+ addr_hit[25] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET);
+ addr_hit[26] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET);
+ addr_hit[27] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_OFFSET);
+ addr_hit[28] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_OFFSET);
+ addr_hit[29] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_OFFSET);
+ addr_hit[30] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_OFFSET);
+ addr_hit[31] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_0_OFFSET);
+ addr_hit[32] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_1_OFFSET);
+ addr_hit[33] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_2_OFFSET);
+ addr_hit[34] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_3_OFFSET);
+ addr_hit[35] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_0_OFFSET);
+ addr_hit[36] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_1_OFFSET);
+ addr_hit[37] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_2_OFFSET);
+ addr_hit[38] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_3_OFFSET);
+ addr_hit[39] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET);
+ addr_hit[40] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET);
+ addr_hit[41] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET);
+ addr_hit[42] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET);
+ addr_hit[43] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_OFFSET);
+ addr_hit[44] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_OFFSET);
+ addr_hit[45] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_OFFSET);
+ addr_hit[46] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_OFFSET);
+ addr_hit[47] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_0_OFFSET);
+ addr_hit[48] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_1_OFFSET);
+ addr_hit[49] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_2_OFFSET);
+ addr_hit[50] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_3_OFFSET);
+ addr_hit[51] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_0_OFFSET);
+ addr_hit[52] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_1_OFFSET);
+ addr_hit[53] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_2_OFFSET);
+ addr_hit[54] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_3_OFFSET);
+ addr_hit[55] = (reg_addr == FLASH_CTRL_BANK_CFG_REGWEN_OFFSET);
+ addr_hit[56] = (reg_addr == FLASH_CTRL_MP_BANK_CFG_OFFSET);
+ addr_hit[57] = (reg_addr == FLASH_CTRL_OP_STATUS_OFFSET);
+ addr_hit[58] = (reg_addr == FLASH_CTRL_STATUS_OFFSET);
+ addr_hit[59] = (reg_addr == FLASH_CTRL_PHY_STATUS_OFFSET);
+ addr_hit[60] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET);
+ addr_hit[61] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET);
+ addr_hit[62] = (reg_addr == FLASH_CTRL_FIFO_RST_OFFSET);
+ end
+
+ assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
+
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = 1'b0;
+ if (addr_hit[ 0] && reg_we && (FLASH_CTRL_PERMIT[ 0] != (FLASH_CTRL_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 1] && reg_we && (FLASH_CTRL_PERMIT[ 1] != (FLASH_CTRL_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 2] && reg_we && (FLASH_CTRL_PERMIT[ 2] != (FLASH_CTRL_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 3] && reg_we && (FLASH_CTRL_PERMIT[ 3] != (FLASH_CTRL_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 4] && reg_we && (FLASH_CTRL_PERMIT[ 4] != (FLASH_CTRL_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 5] && reg_we && (FLASH_CTRL_PERMIT[ 5] != (FLASH_CTRL_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 6] && reg_we && (FLASH_CTRL_PERMIT[ 6] != (FLASH_CTRL_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 7] && reg_we && (FLASH_CTRL_PERMIT[ 7] != (FLASH_CTRL_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 8] && reg_we && (FLASH_CTRL_PERMIT[ 8] != (FLASH_CTRL_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 9] && reg_we && (FLASH_CTRL_PERMIT[ 9] != (FLASH_CTRL_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[10] && reg_we && (FLASH_CTRL_PERMIT[10] != (FLASH_CTRL_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[11] && reg_we && (FLASH_CTRL_PERMIT[11] != (FLASH_CTRL_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[12] && reg_we && (FLASH_CTRL_PERMIT[12] != (FLASH_CTRL_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[13] && reg_we && (FLASH_CTRL_PERMIT[13] != (FLASH_CTRL_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[14] && reg_we && (FLASH_CTRL_PERMIT[14] != (FLASH_CTRL_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[15] && reg_we && (FLASH_CTRL_PERMIT[15] != (FLASH_CTRL_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[16] && reg_we && (FLASH_CTRL_PERMIT[16] != (FLASH_CTRL_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[17] && reg_we && (FLASH_CTRL_PERMIT[17] != (FLASH_CTRL_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[18] && reg_we && (FLASH_CTRL_PERMIT[18] != (FLASH_CTRL_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[19] && reg_we && (FLASH_CTRL_PERMIT[19] != (FLASH_CTRL_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[20] && reg_we && (FLASH_CTRL_PERMIT[20] != (FLASH_CTRL_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[21] && reg_we && (FLASH_CTRL_PERMIT[21] != (FLASH_CTRL_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[22] && reg_we && (FLASH_CTRL_PERMIT[22] != (FLASH_CTRL_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[23] && reg_we && (FLASH_CTRL_PERMIT[23] != (FLASH_CTRL_PERMIT[23] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[24] && reg_we && (FLASH_CTRL_PERMIT[24] != (FLASH_CTRL_PERMIT[24] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[25] && reg_we && (FLASH_CTRL_PERMIT[25] != (FLASH_CTRL_PERMIT[25] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[26] && reg_we && (FLASH_CTRL_PERMIT[26] != (FLASH_CTRL_PERMIT[26] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[27] && reg_we && (FLASH_CTRL_PERMIT[27] != (FLASH_CTRL_PERMIT[27] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[28] && reg_we && (FLASH_CTRL_PERMIT[28] != (FLASH_CTRL_PERMIT[28] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[29] && reg_we && (FLASH_CTRL_PERMIT[29] != (FLASH_CTRL_PERMIT[29] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[30] && reg_we && (FLASH_CTRL_PERMIT[30] != (FLASH_CTRL_PERMIT[30] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[31] && reg_we && (FLASH_CTRL_PERMIT[31] != (FLASH_CTRL_PERMIT[31] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[32] && reg_we && (FLASH_CTRL_PERMIT[32] != (FLASH_CTRL_PERMIT[32] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[33] && reg_we && (FLASH_CTRL_PERMIT[33] != (FLASH_CTRL_PERMIT[33] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[34] && reg_we && (FLASH_CTRL_PERMIT[34] != (FLASH_CTRL_PERMIT[34] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[35] && reg_we && (FLASH_CTRL_PERMIT[35] != (FLASH_CTRL_PERMIT[35] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[36] && reg_we && (FLASH_CTRL_PERMIT[36] != (FLASH_CTRL_PERMIT[36] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[37] && reg_we && (FLASH_CTRL_PERMIT[37] != (FLASH_CTRL_PERMIT[37] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[38] && reg_we && (FLASH_CTRL_PERMIT[38] != (FLASH_CTRL_PERMIT[38] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[39] && reg_we && (FLASH_CTRL_PERMIT[39] != (FLASH_CTRL_PERMIT[39] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[40] && reg_we && (FLASH_CTRL_PERMIT[40] != (FLASH_CTRL_PERMIT[40] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[41] && reg_we && (FLASH_CTRL_PERMIT[41] != (FLASH_CTRL_PERMIT[41] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[42] && reg_we && (FLASH_CTRL_PERMIT[42] != (FLASH_CTRL_PERMIT[42] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[43] && reg_we && (FLASH_CTRL_PERMIT[43] != (FLASH_CTRL_PERMIT[43] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[44] && reg_we && (FLASH_CTRL_PERMIT[44] != (FLASH_CTRL_PERMIT[44] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[45] && reg_we && (FLASH_CTRL_PERMIT[45] != (FLASH_CTRL_PERMIT[45] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[46] && reg_we && (FLASH_CTRL_PERMIT[46] != (FLASH_CTRL_PERMIT[46] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[47] && reg_we && (FLASH_CTRL_PERMIT[47] != (FLASH_CTRL_PERMIT[47] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[48] && reg_we && (FLASH_CTRL_PERMIT[48] != (FLASH_CTRL_PERMIT[48] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[49] && reg_we && (FLASH_CTRL_PERMIT[49] != (FLASH_CTRL_PERMIT[49] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[50] && reg_we && (FLASH_CTRL_PERMIT[50] != (FLASH_CTRL_PERMIT[50] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[51] && reg_we && (FLASH_CTRL_PERMIT[51] != (FLASH_CTRL_PERMIT[51] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[52] && reg_we && (FLASH_CTRL_PERMIT[52] != (FLASH_CTRL_PERMIT[52] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[53] && reg_we && (FLASH_CTRL_PERMIT[53] != (FLASH_CTRL_PERMIT[53] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[54] && reg_we && (FLASH_CTRL_PERMIT[54] != (FLASH_CTRL_PERMIT[54] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[55] && reg_we && (FLASH_CTRL_PERMIT[55] != (FLASH_CTRL_PERMIT[55] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[56] && reg_we && (FLASH_CTRL_PERMIT[56] != (FLASH_CTRL_PERMIT[56] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[57] && reg_we && (FLASH_CTRL_PERMIT[57] != (FLASH_CTRL_PERMIT[57] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[58] && reg_we && (FLASH_CTRL_PERMIT[58] != (FLASH_CTRL_PERMIT[58] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[59] && reg_we && (FLASH_CTRL_PERMIT[59] != (FLASH_CTRL_PERMIT[59] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[60] && reg_we && (FLASH_CTRL_PERMIT[60] != (FLASH_CTRL_PERMIT[60] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[61] && reg_we && (FLASH_CTRL_PERMIT[61] != (FLASH_CTRL_PERMIT[61] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[62] && reg_we && (FLASH_CTRL_PERMIT[62] != (FLASH_CTRL_PERMIT[62] & reg_be))) wr_err = 1'b1 ;
+ end
+
+ assign intr_state_prog_empty_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_prog_empty_wd = reg_wdata[0];
+
+ assign intr_state_prog_lvl_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_prog_lvl_wd = reg_wdata[1];
+
+ assign intr_state_rd_full_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_rd_full_wd = reg_wdata[2];
+
+ assign intr_state_rd_lvl_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_rd_lvl_wd = reg_wdata[3];
+
+ assign intr_state_op_done_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_op_done_wd = reg_wdata[4];
+
+ assign intr_state_op_error_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_op_error_wd = reg_wdata[5];
+
+ assign intr_enable_prog_empty_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_prog_empty_wd = reg_wdata[0];
+
+ assign intr_enable_prog_lvl_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_prog_lvl_wd = reg_wdata[1];
+
+ assign intr_enable_rd_full_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_rd_full_wd = reg_wdata[2];
+
+ assign intr_enable_rd_lvl_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_rd_lvl_wd = reg_wdata[3];
+
+ assign intr_enable_op_done_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_op_done_wd = reg_wdata[4];
+
+ assign intr_enable_op_error_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_op_error_wd = reg_wdata[5];
+
+ assign intr_test_prog_empty_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_prog_empty_wd = reg_wdata[0];
+
+ assign intr_test_prog_lvl_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_prog_lvl_wd = reg_wdata[1];
+
+ assign intr_test_rd_full_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_rd_full_wd = reg_wdata[2];
+
+ assign intr_test_rd_lvl_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_rd_lvl_wd = reg_wdata[3];
+
+ assign intr_test_op_done_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_op_done_wd = reg_wdata[4];
+
+ assign intr_test_op_error_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_op_error_wd = reg_wdata[5];
+
+ assign ctrl_regwen_re = addr_hit[3] && reg_re;
+
+ assign control_start_we = addr_hit[4] & reg_we & ~wr_err;
+ assign control_start_wd = reg_wdata[0];
+
+ assign control_op_we = addr_hit[4] & reg_we & ~wr_err;
+ assign control_op_wd = reg_wdata[5:4];
+
+ assign control_prog_sel_we = addr_hit[4] & reg_we & ~wr_err;
+ assign control_prog_sel_wd = reg_wdata[6];
+
+ assign control_erase_sel_we = addr_hit[4] & reg_we & ~wr_err;
+ assign control_erase_sel_wd = reg_wdata[7];
+
+ assign control_partition_sel_we = addr_hit[4] & reg_we & ~wr_err;
+ assign control_partition_sel_wd = reg_wdata[8];
+
+ assign control_info_sel_we = addr_hit[4] & reg_we & ~wr_err;
+ assign control_info_sel_wd = reg_wdata[9];
+
+ assign control_num_we = addr_hit[4] & reg_we & ~wr_err;
+ assign control_num_wd = reg_wdata[27:16];
+
+ assign addr_we = addr_hit[5] & reg_we & ~wr_err;
+ assign addr_wd = reg_wdata[31:0];
+
+ assign region_cfg_regwen_0_we = addr_hit[6] & reg_we & ~wr_err;
+ assign region_cfg_regwen_0_wd = reg_wdata[0];
+
+ assign region_cfg_regwen_1_we = addr_hit[7] & reg_we & ~wr_err;
+ assign region_cfg_regwen_1_wd = reg_wdata[0];
+
+ assign region_cfg_regwen_2_we = addr_hit[8] & reg_we & ~wr_err;
+ assign region_cfg_regwen_2_wd = reg_wdata[0];
+
+ assign region_cfg_regwen_3_we = addr_hit[9] & reg_we & ~wr_err;
+ assign region_cfg_regwen_3_wd = reg_wdata[0];
+
+ assign region_cfg_regwen_4_we = addr_hit[10] & reg_we & ~wr_err;
+ assign region_cfg_regwen_4_wd = reg_wdata[0];
+
+ assign region_cfg_regwen_5_we = addr_hit[11] & reg_we & ~wr_err;
+ assign region_cfg_regwen_5_wd = reg_wdata[0];
+
+ assign region_cfg_regwen_6_we = addr_hit[12] & reg_we & ~wr_err;
+ assign region_cfg_regwen_6_wd = reg_wdata[0];
+
+ assign region_cfg_regwen_7_we = addr_hit[13] & reg_we & ~wr_err;
+ assign region_cfg_regwen_7_wd = reg_wdata[0];
+
+ assign mp_region_cfg_0_en_0_we = addr_hit[14] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_en_0_wd = reg_wdata[0];
+
+ assign mp_region_cfg_0_rd_en_0_we = addr_hit[14] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_rd_en_0_wd = reg_wdata[1];
+
+ assign mp_region_cfg_0_prog_en_0_we = addr_hit[14] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_prog_en_0_wd = reg_wdata[2];
+
+ assign mp_region_cfg_0_erase_en_0_we = addr_hit[14] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_erase_en_0_wd = reg_wdata[3];
+
+ assign mp_region_cfg_0_scramble_en_0_we = addr_hit[14] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_scramble_en_0_wd = reg_wdata[4];
+
+ assign mp_region_cfg_0_base_0_we = addr_hit[14] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_base_0_wd = reg_wdata[16:8];
+
+ assign mp_region_cfg_0_size_0_we = addr_hit[14] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_size_0_wd = reg_wdata[29:20];
+
+ assign mp_region_cfg_1_en_1_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_en_1_wd = reg_wdata[0];
+
+ assign mp_region_cfg_1_rd_en_1_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_rd_en_1_wd = reg_wdata[1];
+
+ assign mp_region_cfg_1_prog_en_1_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_prog_en_1_wd = reg_wdata[2];
+
+ assign mp_region_cfg_1_erase_en_1_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_erase_en_1_wd = reg_wdata[3];
+
+ assign mp_region_cfg_1_scramble_en_1_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_scramble_en_1_wd = reg_wdata[4];
+
+ assign mp_region_cfg_1_base_1_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_base_1_wd = reg_wdata[16:8];
+
+ assign mp_region_cfg_1_size_1_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_size_1_wd = reg_wdata[29:20];
+
+ assign mp_region_cfg_2_en_2_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_en_2_wd = reg_wdata[0];
+
+ assign mp_region_cfg_2_rd_en_2_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_rd_en_2_wd = reg_wdata[1];
+
+ assign mp_region_cfg_2_prog_en_2_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_prog_en_2_wd = reg_wdata[2];
+
+ assign mp_region_cfg_2_erase_en_2_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_erase_en_2_wd = reg_wdata[3];
+
+ assign mp_region_cfg_2_scramble_en_2_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_scramble_en_2_wd = reg_wdata[4];
+
+ assign mp_region_cfg_2_base_2_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_base_2_wd = reg_wdata[16:8];
+
+ assign mp_region_cfg_2_size_2_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_size_2_wd = reg_wdata[29:20];
+
+ assign mp_region_cfg_3_en_3_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_en_3_wd = reg_wdata[0];
+
+ assign mp_region_cfg_3_rd_en_3_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_rd_en_3_wd = reg_wdata[1];
+
+ assign mp_region_cfg_3_prog_en_3_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_prog_en_3_wd = reg_wdata[2];
+
+ assign mp_region_cfg_3_erase_en_3_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_erase_en_3_wd = reg_wdata[3];
+
+ assign mp_region_cfg_3_scramble_en_3_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_scramble_en_3_wd = reg_wdata[4];
+
+ assign mp_region_cfg_3_base_3_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_base_3_wd = reg_wdata[16:8];
+
+ assign mp_region_cfg_3_size_3_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_size_3_wd = reg_wdata[29:20];
+
+ assign mp_region_cfg_4_en_4_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_en_4_wd = reg_wdata[0];
+
+ assign mp_region_cfg_4_rd_en_4_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_rd_en_4_wd = reg_wdata[1];
+
+ assign mp_region_cfg_4_prog_en_4_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_prog_en_4_wd = reg_wdata[2];
+
+ assign mp_region_cfg_4_erase_en_4_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_erase_en_4_wd = reg_wdata[3];
+
+ assign mp_region_cfg_4_scramble_en_4_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_scramble_en_4_wd = reg_wdata[4];
+
+ assign mp_region_cfg_4_base_4_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_base_4_wd = reg_wdata[16:8];
+
+ assign mp_region_cfg_4_size_4_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_size_4_wd = reg_wdata[29:20];
+
+ assign mp_region_cfg_5_en_5_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_en_5_wd = reg_wdata[0];
+
+ assign mp_region_cfg_5_rd_en_5_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_rd_en_5_wd = reg_wdata[1];
+
+ assign mp_region_cfg_5_prog_en_5_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_prog_en_5_wd = reg_wdata[2];
+
+ assign mp_region_cfg_5_erase_en_5_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_erase_en_5_wd = reg_wdata[3];
+
+ assign mp_region_cfg_5_scramble_en_5_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_scramble_en_5_wd = reg_wdata[4];
+
+ assign mp_region_cfg_5_base_5_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_base_5_wd = reg_wdata[16:8];
+
+ assign mp_region_cfg_5_size_5_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_size_5_wd = reg_wdata[29:20];
+
+ assign mp_region_cfg_6_en_6_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_en_6_wd = reg_wdata[0];
+
+ assign mp_region_cfg_6_rd_en_6_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_rd_en_6_wd = reg_wdata[1];
+
+ assign mp_region_cfg_6_prog_en_6_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_prog_en_6_wd = reg_wdata[2];
+
+ assign mp_region_cfg_6_erase_en_6_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_erase_en_6_wd = reg_wdata[3];
+
+ assign mp_region_cfg_6_scramble_en_6_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_scramble_en_6_wd = reg_wdata[4];
+
+ assign mp_region_cfg_6_base_6_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_base_6_wd = reg_wdata[16:8];
+
+ assign mp_region_cfg_6_size_6_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_size_6_wd = reg_wdata[29:20];
+
+ assign mp_region_cfg_7_en_7_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_en_7_wd = reg_wdata[0];
+
+ assign mp_region_cfg_7_rd_en_7_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_rd_en_7_wd = reg_wdata[1];
+
+ assign mp_region_cfg_7_prog_en_7_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_prog_en_7_wd = reg_wdata[2];
+
+ assign mp_region_cfg_7_erase_en_7_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_erase_en_7_wd = reg_wdata[3];
+
+ assign mp_region_cfg_7_scramble_en_7_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_scramble_en_7_wd = reg_wdata[4];
+
+ assign mp_region_cfg_7_base_7_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_base_7_wd = reg_wdata[16:8];
+
+ assign mp_region_cfg_7_size_7_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_size_7_wd = reg_wdata[29:20];
+
+ assign default_region_rd_en_we = addr_hit[22] & reg_we & ~wr_err;
+ assign default_region_rd_en_wd = reg_wdata[0];
+
+ assign default_region_prog_en_we = addr_hit[22] & reg_we & ~wr_err;
+ assign default_region_prog_en_wd = reg_wdata[1];
+
+ assign default_region_erase_en_we = addr_hit[22] & reg_we & ~wr_err;
+ assign default_region_erase_en_wd = reg_wdata[2];
+
+ assign default_region_scramble_en_we = addr_hit[22] & reg_we & ~wr_err;
+ assign default_region_scramble_en_wd = reg_wdata[3];
+
+ assign bank0_info0_regwen_0_we = addr_hit[23] & reg_we & ~wr_err;
+ assign bank0_info0_regwen_0_wd = reg_wdata[0];
+
+ assign bank0_info0_regwen_1_we = addr_hit[24] & reg_we & ~wr_err;
+ assign bank0_info0_regwen_1_wd = reg_wdata[0];
+
+ assign bank0_info0_regwen_2_we = addr_hit[25] & reg_we & ~wr_err;
+ assign bank0_info0_regwen_2_wd = reg_wdata[0];
+
+ assign bank0_info0_regwen_3_we = addr_hit[26] & reg_we & ~wr_err;
+ assign bank0_info0_regwen_3_wd = reg_wdata[0];
+
+ assign bank0_info0_page_cfg_0_en_0_we = addr_hit[27] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_en_0_wd = reg_wdata[0];
+
+ assign bank0_info0_page_cfg_0_rd_en_0_we = addr_hit[27] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_rd_en_0_wd = reg_wdata[1];
+
+ assign bank0_info0_page_cfg_0_prog_en_0_we = addr_hit[27] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_prog_en_0_wd = reg_wdata[2];
+
+ assign bank0_info0_page_cfg_0_erase_en_0_we = addr_hit[27] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_erase_en_0_wd = reg_wdata[3];
+
+ assign bank0_info0_page_cfg_0_scramble_en_0_we = addr_hit[27] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_scramble_en_0_wd = reg_wdata[4];
+
+ assign bank0_info0_page_cfg_1_en_1_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_en_1_wd = reg_wdata[0];
+
+ assign bank0_info0_page_cfg_1_rd_en_1_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_rd_en_1_wd = reg_wdata[1];
+
+ assign bank0_info0_page_cfg_1_prog_en_1_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_prog_en_1_wd = reg_wdata[2];
+
+ assign bank0_info0_page_cfg_1_erase_en_1_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_erase_en_1_wd = reg_wdata[3];
+
+ assign bank0_info0_page_cfg_1_scramble_en_1_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_scramble_en_1_wd = reg_wdata[4];
+
+ assign bank0_info0_page_cfg_2_en_2_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_en_2_wd = reg_wdata[0];
+
+ assign bank0_info0_page_cfg_2_rd_en_2_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_rd_en_2_wd = reg_wdata[1];
+
+ assign bank0_info0_page_cfg_2_prog_en_2_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_prog_en_2_wd = reg_wdata[2];
+
+ assign bank0_info0_page_cfg_2_erase_en_2_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_erase_en_2_wd = reg_wdata[3];
+
+ assign bank0_info0_page_cfg_2_scramble_en_2_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_scramble_en_2_wd = reg_wdata[4];
+
+ assign bank0_info0_page_cfg_3_en_3_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_en_3_wd = reg_wdata[0];
+
+ assign bank0_info0_page_cfg_3_rd_en_3_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_rd_en_3_wd = reg_wdata[1];
+
+ assign bank0_info0_page_cfg_3_prog_en_3_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_prog_en_3_wd = reg_wdata[2];
+
+ assign bank0_info0_page_cfg_3_erase_en_3_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_erase_en_3_wd = reg_wdata[3];
+
+ assign bank0_info0_page_cfg_3_scramble_en_3_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_scramble_en_3_wd = reg_wdata[4];
+
+ assign bank0_info1_regwen_0_we = addr_hit[31] & reg_we & ~wr_err;
+ assign bank0_info1_regwen_0_wd = reg_wdata[0];
+
+ assign bank0_info1_regwen_1_we = addr_hit[32] & reg_we & ~wr_err;
+ assign bank0_info1_regwen_1_wd = reg_wdata[0];
+
+ assign bank0_info1_regwen_2_we = addr_hit[33] & reg_we & ~wr_err;
+ assign bank0_info1_regwen_2_wd = reg_wdata[0];
+
+ assign bank0_info1_regwen_3_we = addr_hit[34] & reg_we & ~wr_err;
+ assign bank0_info1_regwen_3_wd = reg_wdata[0];
+
+ assign bank0_info1_page_cfg_0_en_0_we = addr_hit[35] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_en_0_wd = reg_wdata[0];
+
+ assign bank0_info1_page_cfg_0_rd_en_0_we = addr_hit[35] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_rd_en_0_wd = reg_wdata[1];
+
+ assign bank0_info1_page_cfg_0_prog_en_0_we = addr_hit[35] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_prog_en_0_wd = reg_wdata[2];
+
+ assign bank0_info1_page_cfg_0_erase_en_0_we = addr_hit[35] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_erase_en_0_wd = reg_wdata[3];
+
+ assign bank0_info1_page_cfg_0_scramble_en_0_we = addr_hit[35] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_scramble_en_0_wd = reg_wdata[4];
+
+ assign bank0_info1_page_cfg_1_en_1_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_en_1_wd = reg_wdata[0];
+
+ assign bank0_info1_page_cfg_1_rd_en_1_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_rd_en_1_wd = reg_wdata[1];
+
+ assign bank0_info1_page_cfg_1_prog_en_1_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_prog_en_1_wd = reg_wdata[2];
+
+ assign bank0_info1_page_cfg_1_erase_en_1_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_erase_en_1_wd = reg_wdata[3];
+
+ assign bank0_info1_page_cfg_1_scramble_en_1_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_scramble_en_1_wd = reg_wdata[4];
+
+ assign bank0_info1_page_cfg_2_en_2_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_en_2_wd = reg_wdata[0];
+
+ assign bank0_info1_page_cfg_2_rd_en_2_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_rd_en_2_wd = reg_wdata[1];
+
+ assign bank0_info1_page_cfg_2_prog_en_2_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_prog_en_2_wd = reg_wdata[2];
+
+ assign bank0_info1_page_cfg_2_erase_en_2_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_erase_en_2_wd = reg_wdata[3];
+
+ assign bank0_info1_page_cfg_2_scramble_en_2_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_scramble_en_2_wd = reg_wdata[4];
+
+ assign bank0_info1_page_cfg_3_en_3_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_en_3_wd = reg_wdata[0];
+
+ assign bank0_info1_page_cfg_3_rd_en_3_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_rd_en_3_wd = reg_wdata[1];
+
+ assign bank0_info1_page_cfg_3_prog_en_3_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_prog_en_3_wd = reg_wdata[2];
+
+ assign bank0_info1_page_cfg_3_erase_en_3_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_erase_en_3_wd = reg_wdata[3];
+
+ assign bank0_info1_page_cfg_3_scramble_en_3_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_scramble_en_3_wd = reg_wdata[4];
+
+ assign bank1_info0_regwen_0_we = addr_hit[39] & reg_we & ~wr_err;
+ assign bank1_info0_regwen_0_wd = reg_wdata[0];
+
+ assign bank1_info0_regwen_1_we = addr_hit[40] & reg_we & ~wr_err;
+ assign bank1_info0_regwen_1_wd = reg_wdata[0];
+
+ assign bank1_info0_regwen_2_we = addr_hit[41] & reg_we & ~wr_err;
+ assign bank1_info0_regwen_2_wd = reg_wdata[0];
+
+ assign bank1_info0_regwen_3_we = addr_hit[42] & reg_we & ~wr_err;
+ assign bank1_info0_regwen_3_wd = reg_wdata[0];
+
+ assign bank1_info0_page_cfg_0_en_0_we = addr_hit[43] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_en_0_wd = reg_wdata[0];
+
+ assign bank1_info0_page_cfg_0_rd_en_0_we = addr_hit[43] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_rd_en_0_wd = reg_wdata[1];
+
+ assign bank1_info0_page_cfg_0_prog_en_0_we = addr_hit[43] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_prog_en_0_wd = reg_wdata[2];
+
+ assign bank1_info0_page_cfg_0_erase_en_0_we = addr_hit[43] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_erase_en_0_wd = reg_wdata[3];
+
+ assign bank1_info0_page_cfg_0_scramble_en_0_we = addr_hit[43] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_scramble_en_0_wd = reg_wdata[4];
+
+ assign bank1_info0_page_cfg_1_en_1_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_en_1_wd = reg_wdata[0];
+
+ assign bank1_info0_page_cfg_1_rd_en_1_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_rd_en_1_wd = reg_wdata[1];
+
+ assign bank1_info0_page_cfg_1_prog_en_1_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_prog_en_1_wd = reg_wdata[2];
+
+ assign bank1_info0_page_cfg_1_erase_en_1_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_erase_en_1_wd = reg_wdata[3];
+
+ assign bank1_info0_page_cfg_1_scramble_en_1_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_scramble_en_1_wd = reg_wdata[4];
+
+ assign bank1_info0_page_cfg_2_en_2_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_en_2_wd = reg_wdata[0];
+
+ assign bank1_info0_page_cfg_2_rd_en_2_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_rd_en_2_wd = reg_wdata[1];
+
+ assign bank1_info0_page_cfg_2_prog_en_2_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_prog_en_2_wd = reg_wdata[2];
+
+ assign bank1_info0_page_cfg_2_erase_en_2_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_erase_en_2_wd = reg_wdata[3];
+
+ assign bank1_info0_page_cfg_2_scramble_en_2_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_scramble_en_2_wd = reg_wdata[4];
+
+ assign bank1_info0_page_cfg_3_en_3_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_en_3_wd = reg_wdata[0];
+
+ assign bank1_info0_page_cfg_3_rd_en_3_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_rd_en_3_wd = reg_wdata[1];
+
+ assign bank1_info0_page_cfg_3_prog_en_3_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_prog_en_3_wd = reg_wdata[2];
+
+ assign bank1_info0_page_cfg_3_erase_en_3_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_erase_en_3_wd = reg_wdata[3];
+
+ assign bank1_info0_page_cfg_3_scramble_en_3_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_scramble_en_3_wd = reg_wdata[4];
+
+ assign bank1_info1_regwen_0_we = addr_hit[47] & reg_we & ~wr_err;
+ assign bank1_info1_regwen_0_wd = reg_wdata[0];
+
+ assign bank1_info1_regwen_1_we = addr_hit[48] & reg_we & ~wr_err;
+ assign bank1_info1_regwen_1_wd = reg_wdata[0];
+
+ assign bank1_info1_regwen_2_we = addr_hit[49] & reg_we & ~wr_err;
+ assign bank1_info1_regwen_2_wd = reg_wdata[0];
+
+ assign bank1_info1_regwen_3_we = addr_hit[50] & reg_we & ~wr_err;
+ assign bank1_info1_regwen_3_wd = reg_wdata[0];
+
+ assign bank1_info1_page_cfg_0_en_0_we = addr_hit[51] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_en_0_wd = reg_wdata[0];
+
+ assign bank1_info1_page_cfg_0_rd_en_0_we = addr_hit[51] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_rd_en_0_wd = reg_wdata[1];
+
+ assign bank1_info1_page_cfg_0_prog_en_0_we = addr_hit[51] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_prog_en_0_wd = reg_wdata[2];
+
+ assign bank1_info1_page_cfg_0_erase_en_0_we = addr_hit[51] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_erase_en_0_wd = reg_wdata[3];
+
+ assign bank1_info1_page_cfg_0_scramble_en_0_we = addr_hit[51] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_scramble_en_0_wd = reg_wdata[4];
+
+ assign bank1_info1_page_cfg_1_en_1_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_en_1_wd = reg_wdata[0];
+
+ assign bank1_info1_page_cfg_1_rd_en_1_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_rd_en_1_wd = reg_wdata[1];
+
+ assign bank1_info1_page_cfg_1_prog_en_1_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_prog_en_1_wd = reg_wdata[2];
+
+ assign bank1_info1_page_cfg_1_erase_en_1_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_erase_en_1_wd = reg_wdata[3];
+
+ assign bank1_info1_page_cfg_1_scramble_en_1_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_scramble_en_1_wd = reg_wdata[4];
+
+ assign bank1_info1_page_cfg_2_en_2_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_en_2_wd = reg_wdata[0];
+
+ assign bank1_info1_page_cfg_2_rd_en_2_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_rd_en_2_wd = reg_wdata[1];
+
+ assign bank1_info1_page_cfg_2_prog_en_2_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_prog_en_2_wd = reg_wdata[2];
+
+ assign bank1_info1_page_cfg_2_erase_en_2_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_erase_en_2_wd = reg_wdata[3];
+
+ assign bank1_info1_page_cfg_2_scramble_en_2_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_scramble_en_2_wd = reg_wdata[4];
+
+ assign bank1_info1_page_cfg_3_en_3_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_en_3_wd = reg_wdata[0];
+
+ assign bank1_info1_page_cfg_3_rd_en_3_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_rd_en_3_wd = reg_wdata[1];
+
+ assign bank1_info1_page_cfg_3_prog_en_3_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_prog_en_3_wd = reg_wdata[2];
+
+ assign bank1_info1_page_cfg_3_erase_en_3_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_erase_en_3_wd = reg_wdata[3];
+
+ assign bank1_info1_page_cfg_3_scramble_en_3_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_scramble_en_3_wd = reg_wdata[4];
+
+ assign bank_cfg_regwen_we = addr_hit[55] & reg_we & ~wr_err;
+ assign bank_cfg_regwen_wd = reg_wdata[0];
+
+ assign mp_bank_cfg_erase_en_0_we = addr_hit[56] & reg_we & ~wr_err;
+ assign mp_bank_cfg_erase_en_0_wd = reg_wdata[0];
+
+ assign mp_bank_cfg_erase_en_1_we = addr_hit[56] & reg_we & ~wr_err;
+ assign mp_bank_cfg_erase_en_1_wd = reg_wdata[1];
+
+ assign op_status_done_we = addr_hit[57] & reg_we & ~wr_err;
+ assign op_status_done_wd = reg_wdata[0];
+
+ assign op_status_err_we = addr_hit[57] & reg_we & ~wr_err;
+ assign op_status_err_wd = reg_wdata[1];
+
+
+
+
+
+
+
+
+
+
+ assign scratch_we = addr_hit[60] & reg_we & ~wr_err;
+ assign scratch_wd = reg_wdata[31:0];
+
+ assign fifo_lvl_prog_we = addr_hit[61] & reg_we & ~wr_err;
+ assign fifo_lvl_prog_wd = reg_wdata[4:0];
+
+ assign fifo_lvl_rd_we = addr_hit[61] & reg_we & ~wr_err;
+ assign fifo_lvl_rd_wd = reg_wdata[12:8];
+
+ assign fifo_rst_we = addr_hit[62] & reg_we & ~wr_err;
+ assign fifo_rst_wd = reg_wdata[0];
+
+ // Read data return
+ always_comb begin
+ reg_rdata_next = '0;
+ unique case (1'b1)
+ addr_hit[0]: begin
+ reg_rdata_next[0] = intr_state_prog_empty_qs;
+ reg_rdata_next[1] = intr_state_prog_lvl_qs;
+ reg_rdata_next[2] = intr_state_rd_full_qs;
+ reg_rdata_next[3] = intr_state_rd_lvl_qs;
+ reg_rdata_next[4] = intr_state_op_done_qs;
+ reg_rdata_next[5] = intr_state_op_error_qs;
+ end
+
+ addr_hit[1]: begin
+ reg_rdata_next[0] = intr_enable_prog_empty_qs;
+ reg_rdata_next[1] = intr_enable_prog_lvl_qs;
+ reg_rdata_next[2] = intr_enable_rd_full_qs;
+ reg_rdata_next[3] = intr_enable_rd_lvl_qs;
+ reg_rdata_next[4] = intr_enable_op_done_qs;
+ reg_rdata_next[5] = intr_enable_op_error_qs;
+ end
+
+ addr_hit[2]: begin
+ reg_rdata_next[0] = '0;
+ reg_rdata_next[1] = '0;
+ reg_rdata_next[2] = '0;
+ reg_rdata_next[3] = '0;
+ reg_rdata_next[4] = '0;
+ reg_rdata_next[5] = '0;
+ end
+
+ addr_hit[3]: begin
+ reg_rdata_next[0] = ctrl_regwen_qs;
+ end
+
+ addr_hit[4]: begin
+ reg_rdata_next[0] = control_start_qs;
+ reg_rdata_next[5:4] = control_op_qs;
+ reg_rdata_next[6] = control_prog_sel_qs;
+ reg_rdata_next[7] = control_erase_sel_qs;
+ reg_rdata_next[8] = control_partition_sel_qs;
+ reg_rdata_next[9] = control_info_sel_qs;
+ reg_rdata_next[27:16] = control_num_qs;
+ end
+
+ addr_hit[5]: begin
+ reg_rdata_next[31:0] = addr_qs;
+ end
+
+ addr_hit[6]: begin
+ reg_rdata_next[0] = region_cfg_regwen_0_qs;
+ end
+
+ addr_hit[7]: begin
+ reg_rdata_next[0] = region_cfg_regwen_1_qs;
+ end
+
+ addr_hit[8]: begin
+ reg_rdata_next[0] = region_cfg_regwen_2_qs;
+ end
+
+ addr_hit[9]: begin
+ reg_rdata_next[0] = region_cfg_regwen_3_qs;
+ end
+
+ addr_hit[10]: begin
+ reg_rdata_next[0] = region_cfg_regwen_4_qs;
+ end
+
+ addr_hit[11]: begin
+ reg_rdata_next[0] = region_cfg_regwen_5_qs;
+ end
+
+ addr_hit[12]: begin
+ reg_rdata_next[0] = region_cfg_regwen_6_qs;
+ end
+
+ addr_hit[13]: begin
+ reg_rdata_next[0] = region_cfg_regwen_7_qs;
+ end
+
+ addr_hit[14]: begin
+ reg_rdata_next[0] = mp_region_cfg_0_en_0_qs;
+ reg_rdata_next[1] = mp_region_cfg_0_rd_en_0_qs;
+ reg_rdata_next[2] = mp_region_cfg_0_prog_en_0_qs;
+ reg_rdata_next[3] = mp_region_cfg_0_erase_en_0_qs;
+ reg_rdata_next[4] = mp_region_cfg_0_scramble_en_0_qs;
+ reg_rdata_next[16:8] = mp_region_cfg_0_base_0_qs;
+ reg_rdata_next[29:20] = mp_region_cfg_0_size_0_qs;
+ end
+
+ addr_hit[15]: begin
+ reg_rdata_next[0] = mp_region_cfg_1_en_1_qs;
+ reg_rdata_next[1] = mp_region_cfg_1_rd_en_1_qs;
+ reg_rdata_next[2] = mp_region_cfg_1_prog_en_1_qs;
+ reg_rdata_next[3] = mp_region_cfg_1_erase_en_1_qs;
+ reg_rdata_next[4] = mp_region_cfg_1_scramble_en_1_qs;
+ reg_rdata_next[16:8] = mp_region_cfg_1_base_1_qs;
+ reg_rdata_next[29:20] = mp_region_cfg_1_size_1_qs;
+ end
+
+ addr_hit[16]: begin
+ reg_rdata_next[0] = mp_region_cfg_2_en_2_qs;
+ reg_rdata_next[1] = mp_region_cfg_2_rd_en_2_qs;
+ reg_rdata_next[2] = mp_region_cfg_2_prog_en_2_qs;
+ reg_rdata_next[3] = mp_region_cfg_2_erase_en_2_qs;
+ reg_rdata_next[4] = mp_region_cfg_2_scramble_en_2_qs;
+ reg_rdata_next[16:8] = mp_region_cfg_2_base_2_qs;
+ reg_rdata_next[29:20] = mp_region_cfg_2_size_2_qs;
+ end
+
+ addr_hit[17]: begin
+ reg_rdata_next[0] = mp_region_cfg_3_en_3_qs;
+ reg_rdata_next[1] = mp_region_cfg_3_rd_en_3_qs;
+ reg_rdata_next[2] = mp_region_cfg_3_prog_en_3_qs;
+ reg_rdata_next[3] = mp_region_cfg_3_erase_en_3_qs;
+ reg_rdata_next[4] = mp_region_cfg_3_scramble_en_3_qs;
+ reg_rdata_next[16:8] = mp_region_cfg_3_base_3_qs;
+ reg_rdata_next[29:20] = mp_region_cfg_3_size_3_qs;
+ end
+
+ addr_hit[18]: begin
+ reg_rdata_next[0] = mp_region_cfg_4_en_4_qs;
+ reg_rdata_next[1] = mp_region_cfg_4_rd_en_4_qs;
+ reg_rdata_next[2] = mp_region_cfg_4_prog_en_4_qs;
+ reg_rdata_next[3] = mp_region_cfg_4_erase_en_4_qs;
+ reg_rdata_next[4] = mp_region_cfg_4_scramble_en_4_qs;
+ reg_rdata_next[16:8] = mp_region_cfg_4_base_4_qs;
+ reg_rdata_next[29:20] = mp_region_cfg_4_size_4_qs;
+ end
+
+ addr_hit[19]: begin
+ reg_rdata_next[0] = mp_region_cfg_5_en_5_qs;
+ reg_rdata_next[1] = mp_region_cfg_5_rd_en_5_qs;
+ reg_rdata_next[2] = mp_region_cfg_5_prog_en_5_qs;
+ reg_rdata_next[3] = mp_region_cfg_5_erase_en_5_qs;
+ reg_rdata_next[4] = mp_region_cfg_5_scramble_en_5_qs;
+ reg_rdata_next[16:8] = mp_region_cfg_5_base_5_qs;
+ reg_rdata_next[29:20] = mp_region_cfg_5_size_5_qs;
+ end
+
+ addr_hit[20]: begin
+ reg_rdata_next[0] = mp_region_cfg_6_en_6_qs;
+ reg_rdata_next[1] = mp_region_cfg_6_rd_en_6_qs;
+ reg_rdata_next[2] = mp_region_cfg_6_prog_en_6_qs;
+ reg_rdata_next[3] = mp_region_cfg_6_erase_en_6_qs;
+ reg_rdata_next[4] = mp_region_cfg_6_scramble_en_6_qs;
+ reg_rdata_next[16:8] = mp_region_cfg_6_base_6_qs;
+ reg_rdata_next[29:20] = mp_region_cfg_6_size_6_qs;
+ end
+
+ addr_hit[21]: begin
+ reg_rdata_next[0] = mp_region_cfg_7_en_7_qs;
+ reg_rdata_next[1] = mp_region_cfg_7_rd_en_7_qs;
+ reg_rdata_next[2] = mp_region_cfg_7_prog_en_7_qs;
+ reg_rdata_next[3] = mp_region_cfg_7_erase_en_7_qs;
+ reg_rdata_next[4] = mp_region_cfg_7_scramble_en_7_qs;
+ reg_rdata_next[16:8] = mp_region_cfg_7_base_7_qs;
+ reg_rdata_next[29:20] = mp_region_cfg_7_size_7_qs;
+ end
+
+ addr_hit[22]: begin
+ reg_rdata_next[0] = default_region_rd_en_qs;
+ reg_rdata_next[1] = default_region_prog_en_qs;
+ reg_rdata_next[2] = default_region_erase_en_qs;
+ reg_rdata_next[3] = default_region_scramble_en_qs;
+ end
+
+ addr_hit[23]: begin
+ reg_rdata_next[0] = bank0_info0_regwen_0_qs;
+ end
+
+ addr_hit[24]: begin
+ reg_rdata_next[0] = bank0_info0_regwen_1_qs;
+ end
+
+ addr_hit[25]: begin
+ reg_rdata_next[0] = bank0_info0_regwen_2_qs;
+ end
+
+ addr_hit[26]: begin
+ reg_rdata_next[0] = bank0_info0_regwen_3_qs;
+ end
+
+ addr_hit[27]: begin
+ reg_rdata_next[0] = bank0_info0_page_cfg_0_en_0_qs;
+ reg_rdata_next[1] = bank0_info0_page_cfg_0_rd_en_0_qs;
+ reg_rdata_next[2] = bank0_info0_page_cfg_0_prog_en_0_qs;
+ reg_rdata_next[3] = bank0_info0_page_cfg_0_erase_en_0_qs;
+ reg_rdata_next[4] = bank0_info0_page_cfg_0_scramble_en_0_qs;
+ end
+
+ addr_hit[28]: begin
+ reg_rdata_next[0] = bank0_info0_page_cfg_1_en_1_qs;
+ reg_rdata_next[1] = bank0_info0_page_cfg_1_rd_en_1_qs;
+ reg_rdata_next[2] = bank0_info0_page_cfg_1_prog_en_1_qs;
+ reg_rdata_next[3] = bank0_info0_page_cfg_1_erase_en_1_qs;
+ reg_rdata_next[4] = bank0_info0_page_cfg_1_scramble_en_1_qs;
+ end
+
+ addr_hit[29]: begin
+ reg_rdata_next[0] = bank0_info0_page_cfg_2_en_2_qs;
+ reg_rdata_next[1] = bank0_info0_page_cfg_2_rd_en_2_qs;
+ reg_rdata_next[2] = bank0_info0_page_cfg_2_prog_en_2_qs;
+ reg_rdata_next[3] = bank0_info0_page_cfg_2_erase_en_2_qs;
+ reg_rdata_next[4] = bank0_info0_page_cfg_2_scramble_en_2_qs;
+ end
+
+ addr_hit[30]: begin
+ reg_rdata_next[0] = bank0_info0_page_cfg_3_en_3_qs;
+ reg_rdata_next[1] = bank0_info0_page_cfg_3_rd_en_3_qs;
+ reg_rdata_next[2] = bank0_info0_page_cfg_3_prog_en_3_qs;
+ reg_rdata_next[3] = bank0_info0_page_cfg_3_erase_en_3_qs;
+ reg_rdata_next[4] = bank0_info0_page_cfg_3_scramble_en_3_qs;
+ end
+
+ addr_hit[31]: begin
+ reg_rdata_next[0] = bank0_info1_regwen_0_qs;
+ end
+
+ addr_hit[32]: begin
+ reg_rdata_next[0] = bank0_info1_regwen_1_qs;
+ end
+
+ addr_hit[33]: begin
+ reg_rdata_next[0] = bank0_info1_regwen_2_qs;
+ end
+
+ addr_hit[34]: begin
+ reg_rdata_next[0] = bank0_info1_regwen_3_qs;
+ end
+
+ addr_hit[35]: begin
+ reg_rdata_next[0] = bank0_info1_page_cfg_0_en_0_qs;
+ reg_rdata_next[1] = bank0_info1_page_cfg_0_rd_en_0_qs;
+ reg_rdata_next[2] = bank0_info1_page_cfg_0_prog_en_0_qs;
+ reg_rdata_next[3] = bank0_info1_page_cfg_0_erase_en_0_qs;
+ reg_rdata_next[4] = bank0_info1_page_cfg_0_scramble_en_0_qs;
+ end
+
+ addr_hit[36]: begin
+ reg_rdata_next[0] = bank0_info1_page_cfg_1_en_1_qs;
+ reg_rdata_next[1] = bank0_info1_page_cfg_1_rd_en_1_qs;
+ reg_rdata_next[2] = bank0_info1_page_cfg_1_prog_en_1_qs;
+ reg_rdata_next[3] = bank0_info1_page_cfg_1_erase_en_1_qs;
+ reg_rdata_next[4] = bank0_info1_page_cfg_1_scramble_en_1_qs;
+ end
+
+ addr_hit[37]: begin
+ reg_rdata_next[0] = bank0_info1_page_cfg_2_en_2_qs;
+ reg_rdata_next[1] = bank0_info1_page_cfg_2_rd_en_2_qs;
+ reg_rdata_next[2] = bank0_info1_page_cfg_2_prog_en_2_qs;
+ reg_rdata_next[3] = bank0_info1_page_cfg_2_erase_en_2_qs;
+ reg_rdata_next[4] = bank0_info1_page_cfg_2_scramble_en_2_qs;
+ end
+
+ addr_hit[38]: begin
+ reg_rdata_next[0] = bank0_info1_page_cfg_3_en_3_qs;
+ reg_rdata_next[1] = bank0_info1_page_cfg_3_rd_en_3_qs;
+ reg_rdata_next[2] = bank0_info1_page_cfg_3_prog_en_3_qs;
+ reg_rdata_next[3] = bank0_info1_page_cfg_3_erase_en_3_qs;
+ reg_rdata_next[4] = bank0_info1_page_cfg_3_scramble_en_3_qs;
+ end
+
+ addr_hit[39]: begin
+ reg_rdata_next[0] = bank1_info0_regwen_0_qs;
+ end
+
+ addr_hit[40]: begin
+ reg_rdata_next[0] = bank1_info0_regwen_1_qs;
+ end
+
+ addr_hit[41]: begin
+ reg_rdata_next[0] = bank1_info0_regwen_2_qs;
+ end
+
+ addr_hit[42]: begin
+ reg_rdata_next[0] = bank1_info0_regwen_3_qs;
+ end
+
+ addr_hit[43]: begin
+ reg_rdata_next[0] = bank1_info0_page_cfg_0_en_0_qs;
+ reg_rdata_next[1] = bank1_info0_page_cfg_0_rd_en_0_qs;
+ reg_rdata_next[2] = bank1_info0_page_cfg_0_prog_en_0_qs;
+ reg_rdata_next[3] = bank1_info0_page_cfg_0_erase_en_0_qs;
+ reg_rdata_next[4] = bank1_info0_page_cfg_0_scramble_en_0_qs;
+ end
+
+ addr_hit[44]: begin
+ reg_rdata_next[0] = bank1_info0_page_cfg_1_en_1_qs;
+ reg_rdata_next[1] = bank1_info0_page_cfg_1_rd_en_1_qs;
+ reg_rdata_next[2] = bank1_info0_page_cfg_1_prog_en_1_qs;
+ reg_rdata_next[3] = bank1_info0_page_cfg_1_erase_en_1_qs;
+ reg_rdata_next[4] = bank1_info0_page_cfg_1_scramble_en_1_qs;
+ end
+
+ addr_hit[45]: begin
+ reg_rdata_next[0] = bank1_info0_page_cfg_2_en_2_qs;
+ reg_rdata_next[1] = bank1_info0_page_cfg_2_rd_en_2_qs;
+ reg_rdata_next[2] = bank1_info0_page_cfg_2_prog_en_2_qs;
+ reg_rdata_next[3] = bank1_info0_page_cfg_2_erase_en_2_qs;
+ reg_rdata_next[4] = bank1_info0_page_cfg_2_scramble_en_2_qs;
+ end
+
+ addr_hit[46]: begin
+ reg_rdata_next[0] = bank1_info0_page_cfg_3_en_3_qs;
+ reg_rdata_next[1] = bank1_info0_page_cfg_3_rd_en_3_qs;
+ reg_rdata_next[2] = bank1_info0_page_cfg_3_prog_en_3_qs;
+ reg_rdata_next[3] = bank1_info0_page_cfg_3_erase_en_3_qs;
+ reg_rdata_next[4] = bank1_info0_page_cfg_3_scramble_en_3_qs;
+ end
+
+ addr_hit[47]: begin
+ reg_rdata_next[0] = bank1_info1_regwen_0_qs;
+ end
+
+ addr_hit[48]: begin
+ reg_rdata_next[0] = bank1_info1_regwen_1_qs;
+ end
+
+ addr_hit[49]: begin
+ reg_rdata_next[0] = bank1_info1_regwen_2_qs;
+ end
+
+ addr_hit[50]: begin
+ reg_rdata_next[0] = bank1_info1_regwen_3_qs;
+ end
+
+ addr_hit[51]: begin
+ reg_rdata_next[0] = bank1_info1_page_cfg_0_en_0_qs;
+ reg_rdata_next[1] = bank1_info1_page_cfg_0_rd_en_0_qs;
+ reg_rdata_next[2] = bank1_info1_page_cfg_0_prog_en_0_qs;
+ reg_rdata_next[3] = bank1_info1_page_cfg_0_erase_en_0_qs;
+ reg_rdata_next[4] = bank1_info1_page_cfg_0_scramble_en_0_qs;
+ end
+
+ addr_hit[52]: begin
+ reg_rdata_next[0] = bank1_info1_page_cfg_1_en_1_qs;
+ reg_rdata_next[1] = bank1_info1_page_cfg_1_rd_en_1_qs;
+ reg_rdata_next[2] = bank1_info1_page_cfg_1_prog_en_1_qs;
+ reg_rdata_next[3] = bank1_info1_page_cfg_1_erase_en_1_qs;
+ reg_rdata_next[4] = bank1_info1_page_cfg_1_scramble_en_1_qs;
+ end
+
+ addr_hit[53]: begin
+ reg_rdata_next[0] = bank1_info1_page_cfg_2_en_2_qs;
+ reg_rdata_next[1] = bank1_info1_page_cfg_2_rd_en_2_qs;
+ reg_rdata_next[2] = bank1_info1_page_cfg_2_prog_en_2_qs;
+ reg_rdata_next[3] = bank1_info1_page_cfg_2_erase_en_2_qs;
+ reg_rdata_next[4] = bank1_info1_page_cfg_2_scramble_en_2_qs;
+ end
+
+ addr_hit[54]: begin
+ reg_rdata_next[0] = bank1_info1_page_cfg_3_en_3_qs;
+ reg_rdata_next[1] = bank1_info1_page_cfg_3_rd_en_3_qs;
+ reg_rdata_next[2] = bank1_info1_page_cfg_3_prog_en_3_qs;
+ reg_rdata_next[3] = bank1_info1_page_cfg_3_erase_en_3_qs;
+ reg_rdata_next[4] = bank1_info1_page_cfg_3_scramble_en_3_qs;
+ end
+
+ addr_hit[55]: begin
+ reg_rdata_next[0] = bank_cfg_regwen_qs;
+ end
+
+ addr_hit[56]: begin
+ reg_rdata_next[0] = mp_bank_cfg_erase_en_0_qs;
+ reg_rdata_next[1] = mp_bank_cfg_erase_en_1_qs;
+ end
+
+ addr_hit[57]: begin
+ reg_rdata_next[0] = op_status_done_qs;
+ reg_rdata_next[1] = op_status_err_qs;
+ end
+
+ addr_hit[58]: begin
+ reg_rdata_next[0] = status_rd_full_qs;
+ reg_rdata_next[1] = status_rd_empty_qs;
+ reg_rdata_next[2] = status_prog_full_qs;
+ reg_rdata_next[3] = status_prog_empty_qs;
+ reg_rdata_next[4] = status_init_wip_qs;
+ reg_rdata_next[16:8] = status_error_addr_qs;
+ end
+
+ addr_hit[59]: begin
+ reg_rdata_next[0] = phy_status_init_wip_qs;
+ reg_rdata_next[1] = phy_status_prog_normal_avail_qs;
+ reg_rdata_next[2] = phy_status_prog_repair_avail_qs;
+ end
+
+ addr_hit[60]: begin
+ reg_rdata_next[31:0] = scratch_qs;
+ end
+
+ addr_hit[61]: begin
+ reg_rdata_next[4:0] = fifo_lvl_prog_qs;
+ reg_rdata_next[12:8] = fifo_lvl_rd_qs;
+ end
+
+ addr_hit[62]: begin
+ reg_rdata_next[0] = fifo_rst_qs;
+ end
+
+ default: begin
+ reg_rdata_next = '1;
+ end
+ endcase
+ end
+
+ // Assertions for Register Interface
+ `ASSERT_PULSE(wePulse, reg_we)
+ `ASSERT_PULSE(rePulse, reg_re)
+
+ `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid)
+
+ `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
+
+ // this is formulated as an assumption such that the FPV testbenches do disprove this
+ // property by mistake
+ `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0)
+
+endmodule
