[dv] Add sub RAL block creation knobs
This commit was an attempt at a fix for #9323 which was unsuccessful.
The idea was to provide per-sub-RAL block creation knobs which are
controlled at runtime instead. So for instance, the generic AST register
block within the chip RAL model could be skipped from creation at
runtime. The provided callback functions `pre|post_build_ral_settings()`
would be used to achieve this. The extended (external) chip env cfg
class could skip the generic RAL blocks for instance and maintain
separate actual RAL blocks in their env instead. Chose to keep these
updates but not execute this idea.
Signed-off-by: Srikrishna Iyer <sriyer@google.com>
diff --git a/hw/dv/sv/dv_lib/dv_base_env_cfg.sv b/hw/dv/sv/dv_lib/dv_base_env_cfg.sv
index dc77b9a..60989f6 100644
--- a/hw/dv/sv/dv_lib/dv_base_env_cfg.sv
+++ b/hw/dv/sv/dv_lib/dv_base_env_cfg.sv
@@ -85,10 +85,18 @@
end
endfunction
- // ral flow is limited in terms of setting correct field access policies and reset values
- // We apply those fixes here - please note these fixes need to be reflected in the scoreboard
- protected virtual function void apply_ral_fixes();
- // fix access policies & reset values
+ // Set pre-build RAL knobs.
+ //
+ // This method enables setting pre-build config knobs that can be used to control how the RAL
+ // sub-structures are created.
+ protected virtual function void pre_build_ral_settings(dv_base_reg_block ral);
+ endfunction
+
+ // Perform post-build, pre-lock modifications to the RAL.
+ //
+ // For some registers / fields, the correct access policies or reset values may not be set. Fixes
+ // like those can be made with this method.
+ protected virtual function void post_build_ral_settings(dv_base_reg_block ral);
endfunction
virtual function void reset_asserted();
@@ -112,8 +120,9 @@
// Build the register block with an arbitrary base address (we choose 0). We'll change it
// later.
+ pre_build_ral_settings(reg_blk);
reg_blk.build(.base_addr(0), .csr_excl(null));
- apply_ral_fixes();
+ post_build_ral_settings(reg_blk);
reg_blk.lock_model();
// Now the model is locked, we know its layout. Set the base address for the register block.
diff --git a/hw/ip/usbdev/dv/env/usbdev_env.core b/hw/ip/usbdev/dv/env/usbdev_env.core
index 4a566ef..1b4b6c3 100644
--- a/hw/ip/usbdev/dv/env/usbdev_env.core
+++ b/hw/ip/usbdev/dv/env/usbdev_env.core
@@ -10,6 +10,7 @@
- lowrisc:dv:ralgen
- lowrisc:dv:cip_lib
- lowrisc:dv:usb20_agent
+ - lowrisc:dv:dv_base_reg
files:
- usbdev_env_pkg.sv
- usbdev_env_cfg.sv: {is_include_file: true}
diff --git a/hw/ip/usbdev/dv/env/usbdev_env_cfg.sv b/hw/ip/usbdev/dv/env/usbdev_env_cfg.sv
index 12e9904..f9271e4 100644
--- a/hw/ip/usbdev/dv/env/usbdev_env_cfg.sv
+++ b/hw/ip/usbdev/dv/env/usbdev_env_cfg.sv
@@ -42,10 +42,12 @@
// ral flow is limited in terms of setting correct field access policies and reset values
// We apply those fixes here - please note these fixes need to be reflected in the scoreboard
- protected virtual function void apply_ral_fixes();
+ protected virtual function void post_build_ral_settings(dv_base_reg_block ral);
+ usbdev_reg_block usbdev_ral;
+ if (!$cast(usbdev_ral, ral)) return;
// fix access policies
// Out of reset, the link is in disconnected state.
- ral.intr_state.disconnected.set_reset(1'b1);
+ usbdev_ral.intr_state.disconnected.set_reset(1'b1);
endfunction
endclass
diff --git a/hw/ip/usbdev/dv/env/usbdev_env_pkg.sv b/hw/ip/usbdev/dv/env/usbdev_env_pkg.sv
index fa3099c..10c7f94 100644
--- a/hw/ip/usbdev/dv/env/usbdev_env_pkg.sv
+++ b/hw/ip/usbdev/dv/env/usbdev_env_pkg.sv
@@ -7,6 +7,7 @@
import uvm_pkg::*;
import top_pkg::*;
import dv_utils_pkg::*;
+ import dv_base_reg_pkg::*;
import csr_utils_pkg::*;
import tl_agent_pkg::*;
import usb20_agent_pkg::*;
diff --git a/hw/top_earlgrey/dv/env/chip_env_cfg.sv b/hw/top_earlgrey/dv/env/chip_env_cfg.sv
index 4eee190..a07f8ab 100644
--- a/hw/top_earlgrey/dv/env/chip_env_cfg.sv
+++ b/hw/top_earlgrey/dv/env/chip_env_cfg.sv
@@ -113,11 +113,12 @@
`DV_CHECK_LE_FATAL(num_ram_ret_tiles, 16)
endfunction
- // ral flow is limited in terms of setting correct field access policies and reset values
- // We apply those fixes here - please note these fixes need to be reflected in the scoreboard
- protected virtual function void apply_ral_fixes();
+ // Apply RAL fixes before it is locked.
+ protected virtual function void post_build_ral_settings(dv_base_reg_block ral);
+ RAL_T chip_ral;
+ if (!$cast(chip_ral, ral)) return;
// Out of reset, the link is in disconnected state.
- ral.usbdev.intr_state.disconnected.set_reset(1'b1);
+ chip_ral.usbdev.intr_state.disconnected.set_reset(1'b1);
endfunction
// Parse a space-separated list of sw_images supplied as a string.
diff --git a/util/topgen/top_uvm_reg.sv.tpl b/util/topgen/top_uvm_reg.sv.tpl
index 2bb742b..95c8bfa 100644
--- a/util/topgen/top_uvm_reg.sv.tpl
+++ b/util/topgen/top_uvm_reg.sv.tpl
@@ -84,6 +84,7 @@
esc_if_name = block_name.lower() + if_suffix
if_inst = inst_name + if_suffix
%>\
+ bit create_${if_inst} = 1'b1;
rand ${bcname(esc_if_name)} ${if_inst};
% endfor
% endfor
@@ -133,19 +134,21 @@
hpr_indent = (len(if_inst) + len('.set_hdl_path_root(')) * ' '
%>\
- ${if_inst} =
- ${bcname(esc_if_name)}::type_id::create("${if_inst}");
- ${if_inst}.set_ip_name("${inst_name}");
- ${if_inst}.configure(.parent(this));
- ${if_inst}.build(.base_addr(base_addr + ${base_addr_txt}), .csr_excl(csr_excl));
- ${if_inst}.set_hdl_path_root("${hdl_path}",
- ${hpr_indent}"BkdrRegPathRtl");
- ${if_inst}.set_hdl_path_root("${hdl_path}",
- ${hpr_indent}"BkdrRegPathRtlCommitted");
- ${if_inst}.set_hdl_path_root("${hdl_path}",
- ${hpr_indent}"BkdrRegPathRtlShadow");
- default_map.add_submap(.child_map(${if_inst}.default_map),
- .offset(base_addr + ${base_addr_txt}));
+ if (create_${if_inst}) begin
+ ${if_inst} =
+ ${bcname(esc_if_name)}::type_id::create("${if_inst}");
+ ${if_inst}.set_ip_name("${inst_name}");
+ ${if_inst}.configure(.parent(this));
+ ${if_inst}.build(.base_addr(base_addr + ${base_addr_txt}), .csr_excl(csr_excl));
+ ${if_inst}.set_hdl_path_root("${hdl_path}",
+ ${hpr_indent}"BkdrRegPathRtl");
+ ${if_inst}.set_hdl_path_root("${hdl_path}",
+ ${hpr_indent}"BkdrRegPathRtlCommitted");
+ ${if_inst}.set_hdl_path_root("${hdl_path}",
+ ${hpr_indent}"BkdrRegPathRtlShadow");
+ default_map.add_submap(.child_map(${if_inst}.default_map),
+ .offset(base_addr + ${base_addr_txt}));
+ end
% endfor
% endfor
% endfor
