commit | fc9ce22c1c836951396af5af0cb9306ca9ba09f8 | [log] [tgz] |
---|---|---|
author | Moritz Wettermann <moritz.wettermann@gi-de.com> | Wed Aug 10 11:27:40 2022 +0200 |
committer | Pirmin Vogel <vogelpi@lowrisc.org> | Thu Aug 11 09:18:57 2022 +0200 |
tree | eeac12c96b779262a3eb2a5c0828135a21a3ab19 | |
parent | ca7f4841917235e26c9c69ef673bb453804ecaad [diff] |
[aes/pre_syn] Added missing files to re-enable Yosys synthesis for AES The following errors occured during Yosys synthesis: ERROR: Module `\prim_reg_we_check' referenced in module `\aes_reg_top' in cell `\u_prim_reg_we_check' is not part of the design. ERROR: Module `\prim_onehot_check' referenced in module `\prim_reg_we_check' in cell `\u_prim_onehot_check' is not part of the design. Solution was to add the corresponding files to the Yosys synthesis script. Signed-off-by: Moritz Wettermann <moritz.wettermann@gi-de.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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