[ast] Ast lint fixes and waiver file update
Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/hw/top_earlgrey/ip/ast/ast.core b/hw/top_earlgrey/ip/ast/ast.core
index 20fffb8..ef53966 100644
--- a/hw/top_earlgrey/ip/ast/ast.core
+++ b/hw/top_earlgrey/ip/ast/ast.core
@@ -99,6 +99,7 @@
default_tool: verilator
parameters:
- SYNTHESIS=true
+ - AST_BYPASS_CLK=true
tools:
verilator:
mode: lint-only
diff --git a/hw/top_earlgrey/ip/ast/lint/ast.waiver b/hw/top_earlgrey/ip/ast/lint/ast.waiver
index d2b4de2..6be3653 100644
--- a/hw/top_earlgrey/ip/ast/lint/ast.waiver
+++ b/hw/top_earlgrey/ip/ast/lint/ast.waiver
@@ -12,6 +12,14 @@
-msg {Assignment to 'unused_analog_sigs' contained within `ifndef 'ANALOGSIM' block at} \
-comment {This ifdef statement is used for assigning "unused" signals and is OK.}
+waive -rules IFDEF_CODE -location {ast.sv} \
+ -regexp {Assignment to 'clk_(sys|usb|aon|io)_ext' contained within `ifdef 'AST_BYPASS_CLK' block at} \
+ -comment {This ifdef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.}
+
+waive -rules IFDEF_CODE -location {aon_osc.sv io_osc.sv sys_osc.sv usb_osc.sv} \
+ -regexp {Assignment to '(sys|usb|aon|io)_clk_dly' contained within `else block at} \
+ -comment {This ifdef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.}
+
waive -rules CLOCK_EDGE -location {aon_osc.sv io_osc.sv sys_osc.sv usb_osc.sv} \
-msg {Falling edge of clock 'clk' used here, should use rising edge} \
-comment {This negedge trigger is done on purpose.}
@@ -32,6 +40,10 @@
-msg {'rst_val_n' is driven here, and used as an asynchronous reset} \
-comment {This is reset generation logic, hence it needs to drive this reset signal.}
+waive -rules RESET_DRIVER -location {aon_clk.sv io_clk.sv sys_clk.sv usb_clk.sv} \
+ -regexp {'(aon|io|sys|usb)_clk_en' is driven here, and used as an asynchronous reset} \
+ -comment {This is reset generation logic, hence it needs to drive this reset signal.}
+
waive -rules RESET_DRIVER -location {rng.sv} \
-msg {'rst_n' is driven here, and used as an asynchronous reset at rng.sv} \
-comment {This is reset generation logic, hence it needs to drive this reset signal.}
@@ -104,6 +116,10 @@
-regexp {('rst_sys_clk_n'|'rst_usb_clk_n') is connected to ('sys_clk'|'usb_clk') port ('rst_sys_clk_ni'|'rst_usb_clk_ni'), and used as an asynchronous reset or set} \
-comment {This is a valid reset connection.}
+waive -rules RESET_USE -location {aon_clk.sv io_clk.sv sys_clk.sv usb_clk.sv} \
+ -regexp {'(aon|io|sys|usb)_clk_en' is connected to '(aon|io|sys|usb)_osc' port '(aon|io|sys|usb)_en_i', and used as an asynchronous reset or set} \
+ -comment {This is reset / clock generation logic, hence special reset usage is allowed.}
+
waive -rules {TRI_DRIVER} -location {ast.sv} \
-regexp {'ast2pad_(t0|t1)_ao' is driven by a tristate driver} \
-comment {This part models a tristate driver.}
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast.sv b/hw/top_earlgrey/ip/ast/rtl/ast.sv
index 4507340..6fc8d28 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast.sv
@@ -9,12 +9,12 @@
`include "prim_assert.sv"
module ast #(
- parameter int AdcChannels = 2,
- parameter int AdcDataWidth = 10,
- parameter int EntropyStreams = 4,
- parameter int UsbCalibWidth = 20,
- parameter int Ast2PadOutWidth = 9,
- parameter int Pad2AstInWidth = 6
+ parameter int unsigned AdcChannels = 2,
+ parameter int unsigned AdcDataWidth = 10,
+ parameter int unsigned EntropyStreams = 4,
+ parameter int unsigned UsbCalibWidth = 20,
+ parameter int unsigned Ast2PadOutWidth = 9,
+ parameter int unsigned Pad2AstInWidth = 6
) (
// tlul if
input tlul_pkg::tl_h2d_t tl_i, // TLUL H2D
@@ -183,6 +183,8 @@
assign vcc_pok_h = vcc_pok; // "Level Shifter"
assign ast_pwst_h_o.vcc_pok = vcc_pok_h;
+// TODO: double check this.
+assign ast_pwst_o.vcc_pok = vcc_pok;
///////////////////////////////////////
// VCAON POK (Always ON)
