[dv/sysrst_ctrl] Fix constraints and reduce reseed number
This pr:
1). Fix a constraint in combo_detect directed test.
The wait_cycles_c are evaluated in decimal but debounce_timer and
detect timer are in hex.
So I updated them to all use decimal numbers.
2). Reduce nightly reseed for the direct test.
Signed-off-by: Cindy Chen <chencindy@opentitan.org>
diff --git a/hw/ip/sysrst_ctrl/dv/env/seq_lib/sysrst_ctrl_combo_detect_ec_rst_vseq.sv b/hw/ip/sysrst_ctrl/dv/env/seq_lib/sysrst_ctrl_combo_detect_ec_rst_vseq.sv
index 9b731cc..b10d7f8 100644
--- a/hw/ip/sysrst_ctrl/dv/env/seq_lib/sysrst_ctrl_combo_detect_ec_rst_vseq.sv
+++ b/hw/ip/sysrst_ctrl/dv/env/seq_lib/sysrst_ctrl_combo_detect_ec_rst_vseq.sv
@@ -12,16 +12,17 @@
rand int wait_cycles;
rand uvm_reg_data_t detect_timer, debounce_timer;
+ // This constraint gives 50% chance the combo will be triggered.
constraint wait_cycles_c {wait_cycles dist {
- [15 : 25] :/5,
- 25 :/95
+ [1 : debounce_timer] :/ 1,
+ (debounce_timer + detect_timer + 2) :/ 1
};
}
- constraint detect_timer_c {detect_timer == 'h5;}
- constraint debounce_timer_c {debounce_timer == 'h20;}
+ constraint detect_timer_c {detect_timer == 5;}
+ constraint debounce_timer_c {debounce_timer == 20;}
- task drive_input();
+ virtual task drive_input();
// Trigger the input pins
cfg.vif.key0_in = 1;
cfg.vif.key1_in = 1;
@@ -66,7 +67,7 @@
drive_input();
`uvm_info(`gfn, $sformatf("Value of wait_cycles:%0d", wait_cycles), UVM_LOW)
- if (wait_cycles >= (debounce_timer + detect_timer)) begin
+ if (wait_cycles > (debounce_timer + detect_timer)) begin
// It takes 2-3 clock cycles to sync the interrupt value
// Read the combo status register
cfg.clk_aon_rst_vif.wait_clks(2);
diff --git a/hw/ip/sysrst_ctrl/dv/sysrst_ctrl_sim_cfg.hjson b/hw/ip/sysrst_ctrl/dv/sysrst_ctrl_sim_cfg.hjson
index c459e6a..84a87f2 100644
--- a/hw/ip/sysrst_ctrl/dv/sysrst_ctrl_sim_cfg.hjson
+++ b/hw/ip/sysrst_ctrl/dv/sysrst_ctrl_sim_cfg.hjson
@@ -61,6 +61,8 @@
{
name: sysrst_ctrl_combo_detect_ec_rst
uvm_test_seq: sysrst_ctrl_combo_detect_ec_rst_vseq
+ // This is a directed test with very few random values.
+ reseed: 5
}
{
name: sysrst_ctrl_pin_access_test
