[sysrst_ctrl] Declare the gsc_rst_o signal in the hjson
Declaring this as an inter-signal means that it gets wired up properly
in the auto-generated top_earlgrey.sv
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
diff --git a/hw/ip/sysrst_ctrl/data/sysrst_ctrl.hjson b/hw/ip/sysrst_ctrl/data/sysrst_ctrl.hjson
index 00687ed..ae6d303 100644
--- a/hw/ip/sysrst_ctrl/data/sysrst_ctrl.hjson
+++ b/hw/ip/sysrst_ctrl/data/sysrst_ctrl.hjson
@@ -42,6 +42,15 @@
{ name: "key2_out", desc: "Passthrough from key2_in, can be configured to invert" }
{ name: "pwrb_out", desc: "Passthrough from pwrb_in, can be configured to invert" }
],
+ inter_signal_list: [
+ { name: "gsc_rst",
+ package: "",
+ struct: "logic",
+ act: "req"
+ type: "uni",
+ width: "1"
+ }
+ ],
regwidth: "32",
registers: [
{ name: "REGWEN",
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 7e48b47..88ee8ad 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -2604,6 +2604,15 @@
inter_signal_list:
[
{
+ name: gsc_rst
+ struct: logic
+ type: uni
+ act: req
+ width: 1
+ inst_name: sysrst_ctrl_aon
+ index: -1
+ }
+ {
name: tl
struct: tl
package: tlul_pkg
@@ -12421,6 +12430,15 @@
index: -1
}
{
+ name: gsc_rst
+ struct: logic
+ type: uni
+ act: req
+ width: 1
+ inst_name: sysrst_ctrl_aon
+ index: -1
+ }
+ {
name: tl
struct: tl
package: tlul_pkg
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index b8d7c1e..3d2a58b 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -1701,6 +1701,7 @@
.intr_sysrst_ctrl_o (intr_sysrst_ctrl_aon_sysrst_ctrl),
// Inter-module signals
+ .gsc_rst_o(),
.tl_i(sysrst_ctrl_aon_tl_req),
.tl_o(sysrst_ctrl_aon_tl_rsp),
