[fpga] deploy size reduction script for fpga
This is only a short term solution.
Signed-off-by: Timothy Chen <timothytim@google.com>
Build a separate software tree for NexysVideo
Build the software twice: once for the normal earl grey design, and once
for a slightly modified design where SRAM and flash sizes are modified
by a script.
Signed-off-by: Philipp Wagner <phw@lowrisc.org>
[doc] fix doc instructions
Signed-off-by: Timothy Chen <timothytim@google.com>
[util] Add size_check to dependency
Signed-off-by: Timothy Chen <timothytim@google.com>
[top] Remove cw305 related content from top_earlgrey
- top_englishbreakfast is the separate top for cw305
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/doc/ug/getting_started_fpga.md b/doc/ug/getting_started_fpga.md
index c260877..97ef9c3 100644
--- a/doc/ug/getting_started_fpga.md
+++ b/doc/ug/getting_started_fpga.md
@@ -36,12 +36,23 @@
$ ninja -C build-out sw/device/boot_rom/boot_rom_export_fpga_nexysvideo
```
+Since not all FPGAs are able to fit the full design, there is a separate script that can be invoked to reduce the size of the design.
+
+To reduce the design:
+```console
+$ cd $REPO_TOP
+$ ./hw/top_earlgrey/util/top_earlgrey_reduce.py
+```
+By default, the reduce script targets 'nexysvideo', cw305 is also supported.
+
+
In the following example we synthesize the Earl Grey design for the Nexys Video board using Xilinx Vivado 2020.1.
```console
$ . /tools/xilinx/Vivado/2020.1/settings64.sh
$ cd $REPO_TOP
$ ./meson_init.sh
+$ ./hw/top_earlgrey/util/top_earlgrey_reduce.py
$ ninja -C build-out sw/device/boot_rom/boot_rom_export_fpga_nexysvideo
$ fusesoc --cores-root . run --flag=fileset_top --target=synth lowrisc:systems:top_earlgrey_nexysvideo
```
