commit f7f542f065b473f624997150e7062f90ab00302b
author Alphan Ulusoy <alphan@google.com> Fri Sep 09 17:12:21 2022 -0400
committer Alphan Ulusoy <alphan@google.com> Mon Sep 12 10:27:24 2022 -0400
tree 95c898fa0b2e7a3f9113660f0e552096bc7638ab
parent ee771a30c35b58007421215b2ea69f1e2a57d965

[test] Add rom_e2e_bootstrap_phase1_reset

Fixes #14459

Signed-off-by: Alphan Ulusoy <alphan@google.com>

sw/device/silicon_creator/rom/data/rom_testplan.hjson

diff --git a/sw/device/silicon_creator/rom/data/rom_testplan.hjson b/sw/device/silicon_creator/rom/data/rom_testplan.hjson
index 8593bd9..b45503d 100644
--- a/sw/device/silicon_creator/rom/data/rom_testplan.hjson
+++ b/sw/device/silicon_creator/rom/data/rom_testplan.hjson
@@ -288,18 +288,14 @@
 
     {
       name: rom_e2e_bootstrap_phase1_reset
-      desc: '''Verify that bootstrap phase 1 handles `RESET` (`0x99`) correctly.
+      desc: '''Verify that bootstrap phase 1 ignores `RESET` (`0x99`).
 
             `OWNER_SW_CFG_ROM_BOOTSTRAP_EN` OTP item must be `kHardenedBoolTrue` (`0x739`).
 
             - Apply bootstrap pin strapping.
             - Reset the chip.
-            - Verify that the chip responds to `READ_STATUS` (`0x05`) with `0x00`.
             - Send `RESET` (`0x99`).
-            - Verify that the chip outputs the expected `BFV`: `0142500d` over UART.
-              - ROM will continously reset the chip and output the same `BFV` and `LCV`.
-            - Verify that the chip does not respond to `READ_STATUS` (`0x05`).
-              - The data on the CIPO line must be `0xff`.
+            - Verify that the chip does not output anything over UART for at least 1 s.
             '''
       tags: ["rom", "verilator", "dv", "fpga", "silicon"]
       stage: V2

sw/host/tests/rom/e2e_bootstrap_entry/src/main.rs

diff --git a/sw/host/tests/rom/e2e_bootstrap_entry/src/main.rs b/sw/host/tests/rom/e2e_bootstrap_entry/src/main.rs
index 52a721c..c11d9c5 100644
--- a/sw/host/tests/rom/e2e_bootstrap_entry/src/main.rs
+++ b/sw/host/tests/rom/e2e_bootstrap_entry/src/main.rs
@@ -289,6 +289,28 @@
     Ok(())
 }
 
+fn test_bootstrap_phase1_reset(opts: &Opts, transport: &TransportWrapper) -> Result<()> {
+    let _bs = BootstrapTest::start(transport, opts.init.bootstrap.options.reset_delay)?;
+
+    let spi = transport.spi("0")?;
+    let uart = transport.uart("0")?;
+    // RESET should be ignored and we should not see any messages.
+    let mut console = UartConsole {
+        timeout: Some(Duration::new(1, 0)),
+        exit_failure: Some(Regex::new(".+")?),
+        ..Default::default()
+    };
+    // Discard buffered messages before interacting with the console.
+    uart.clear_rx_buffer()?;
+    SpiFlash::chip_reset(&*spi)?;
+    let result = console.interact(&*uart, None, Some(&mut std::io::stdout()))?;
+    if result != ExitStatus::Timeout {
+        bail!("FAIL: {:?}", result);
+    }
+
+    Ok(())
+}
+
 fn main() -> Result<()> {
     let opts = Opts::from_args();
     opts.init.init_logging();
@@ -307,6 +329,7 @@
     ] {
         execute_test!(test_bootstrap_shutdown, &opts, &transport, cmd, bfv);
     }
+    execute_test!(test_bootstrap_phase1_reset, &opts, &transport);
 
     Ok(())
 }