commit f78146005adae9c0f26e55b7b396542eacd1433a
author Timothy Chen <timothytim@google.com> Wed Sep 15 10:09:33 2021 -0700
committer tjaychen <timothytim@google.com> Mon Sep 20 11:53:25 2021 -0700
tree b3c40b38fed3458d3514aa2f7c1054a64a1a2874
parent dc388075b8dcd699dd15463953d961027d5b3abf

[prim] Change prim_reg_cdc assertions

Do not use the src_req directly as event glitches can cause unexpected behavior.

Signed-off-by: Timothy Chen <timothytim@google.com>

hw/ip/prim/rtl/prim_reg_cdc.sv

diff --git a/hw/ip/prim/rtl/prim_reg_cdc.sv b/hw/ip/prim/rtl/prim_reg_cdc.sv
index 3e0c909..2b01f0a 100644
--- a/hw/ip/prim/rtl/prim_reg_cdc.sv
+++ b/hw/ip/prim/rtl/prim_reg_cdc.sv
@@ -139,9 +139,9 @@
 
   `ifdef SIMULATION
     logic async_flag;
-    always_ff @(posedge src_req or posedge dst_req or
+    always_ff @(posedge clk_dst_i or
       negedge rst_src_ni or negedge rst_dst_ni) begin
-      if (!rst_src_ni && !rst_dst_ni) begin
+      if (!rst_src_ni | !rst_dst_ni) begin
         async_flag <= '0;
       end else if (src_req) begin
         async_flag <= 1'b1;