| commit | f6dbc05e0d5db6f77ef14602c03ac76f6e7ea4b2 | [log] [tgz] |
|---|---|---|
| author | TIM EWINS <tim.ewins@ensilica.com> | Thu Apr 28 16:10:48 2022 +0100 |
| committer | weicaiyang <49293026+weicaiyang@users.noreply.github.com> | Mon May 02 10:43:34 2022 -0700 |
| tree | 21d1b97d185a5fa4653152e0540b9c67253e82f5 | |
| parent | 8b0cccd75ba3d69ca0240a609f42232b509bdf26 [diff] |
[flash_ctrl] DEBUG and Enable the OTP_MODEL For some reason, the OTP_MODEL in the Testbench had been commented out. This left the acknowledge signals floating, and hence the otp interface locked up. I have reviewed the otp_model, and have re-enabled it. This is now working with the test flash_ctrl_hw_sec_otp, and is and is safe to be present in all other tests. The otp_model is accessed through a vif between TB and the base sequence. The model provides random otp keys on demand. Signed-off-by: TIM EWINS <tim.ewins@ensilica.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
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