[mask_rom] Add alert handler test automation.
1. Add the alert handler's functest to systemtest and dvsim.
Signed-off-by: Chris Frantz <cfrantz@google.com>
diff --git a/hw/top_earlgrey/dv/verilator_sim_cfg.hjson b/hw/top_earlgrey/dv/verilator_sim_cfg.hjson
index fb78d56..cb45992 100644
--- a/hw/top_earlgrey/dv/verilator_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/verilator_sim_cfg.hjson
@@ -201,6 +201,10 @@
name: sw_silicon_creator_lib_driver_uart_functest
sw_images: ["sw/device/silicon_creator/testing/sw_silicon_creator_lib_driver_uart_functest:1"]
}
+ {
+ name: sw_silicon_creator_lib_driver_alert_functest
+ sw_images: ["sw/device/silicon_creator/testing/sw_silicon_creator_lib_driver_alert_functest:1"]
+ }
]
// List of regressions.
diff --git a/test/systemtest/config.py b/test/systemtest/config.py
index 8afb648..38e81ae 100644
--- a/test/systemtest/config.py
+++ b/test/systemtest/config.py
@@ -126,4 +126,12 @@
"name": "sw_silicon_creator_lib_driver_uart_functest",
"test_dir": "sw/device/silicon_creator/testing",
},
+ {
+ "name": "sw_silicon_creator_lib_driver_alert_functest",
+ "test_dir": "sw/device/silicon_creator/testing",
+ # TODO(lowRISC/opentitan#6965) This test resets the chip and appears to
+ # cause a test failure on FPGA boards. Restrict this test to
+ # verilator for now.
+ "targets": ["sim_verilator"],
+ },
]
