[prim_generic] Factor out loading for 1p RAM

Similar to 2297a614743c346df4ab5efa90a9347f0475d99a, which should have
included this change as part of the refactoring.

Signed-off-by: Philipp Wagner <phw@lowrisc.org>
diff --git a/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv b/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv
index 4f0080a..4c8085f 100644
--- a/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv
+++ b/hw/ip/prim_generic/rtl/prim_generic_ram_1p.sv
@@ -62,48 +62,5 @@
     end
   end
 
-  `ifdef VERILATOR
-    // Task for loading 'mem' with SystemVerilog system task $readmemh()
-    export "DPI-C" task simutil_verilator_memload;
-
-    task simutil_verilator_memload;
-      input string file;
-      $readmemh(file, mem);
-    endtask
-
-    // Width must be a multiple of 32bit for this function to work
-    // Note that the DPI export and function definition must both be in the same generate
-    // context to get the correct name.
-    if ((Width % 32) == 0) begin : gen_set_mem
-      // Function for setting a specific element in |mem|
-      // Returns 1 (true) for success, 0 (false) for errors.
-      export "DPI-C" function simutil_verilator_set_mem;
-
-      function int simutil_verilator_set_mem(input int index,
-                                             input bit [Width-1:0] val);
-        if (index >= Depth) begin
-          return 0;
-        end
-
-        mem[index] = val;
-        return 1;
-      endfunction
-    end else begin : gen_other
-      // Function doesn't work unless Width % 32 so just return 0
-      export "DPI-C" function simutil_verilator_set_mem;
-
-      function int simutil_verilator_set_mem(input int index,
-                                             input bit [Width-1:0] val);
-        return 0;
-      endfunction
-    end
-  `endif
-
-  `ifdef SRAM_INIT_FILE
-    localparam MEM_FILE = `PRIM_STRINGIFY(`SRAM_INIT_FILE);
-    initial begin
-      $display("Initializing SRAM from %s", MEM_FILE);
-      $readmemh(MEM_FILE, mem);
-    end
-  `endif
+  `include "prim_util_memload.sv"
 endmodule