commit f5063e1e9a418bcfae5f30744a55057e4e5e3dca
author Udi Jonnalagadda <udij@google.com> Wed Jan 20 12:39:17 2021 -0800
committer udinator <udij@google.com> Thu Jan 21 16:52:42 2021 -0800
tree dbc0da4aa1bb13935ebb8eebe45ecc36bbc79f09
parent 32b72eeab13a3b743aaccdfa152437e550ce95c0

[kmac/dv] move to V1 status

Signed-off-by: Udi Jonnalagadda <udij@google.com>

hw/ip/kmac/data/kmac.prj.hjson

diff --git a/hw/ip/kmac/data/kmac.prj.hjson b/hw/ip/kmac/data/kmac.prj.hjson
index 89b9c00..7eeb5c3 100644
--- a/hw/ip/kmac/data/kmac.prj.hjson
+++ b/hw/ip/kmac/data/kmac.prj.hjson
@@ -13,9 +13,9 @@
         version:            "1.0",
         life_stage:         "L1",
         design_stage:       "D1",
-        verification_stage: "V0",
-        commit_id:          "40979092",
-        notes:              "Reaching D1"
+        verification_stage: "V1",
+        commit_id:          "7488dff2",
+        notes:              "Reaching V1"
       }
     ]
 }

hw/ip/kmac/doc/checklist.md

diff --git a/hw/ip/kmac/doc/checklist.md b/hw/ip/kmac/doc/checklist.md
index 4895b65..76d051c 100644
--- a/hw/ip/kmac/doc/checklist.md
+++ b/hw/ip/kmac/doc/checklist.md
@@ -110,7 +110,7 @@
 
  Type         | Item                                  | Resolution  | Note/Collaterals
 --------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][]            | Not Started |
+Documentation | [DV_DOC_DRAFT_COMPLETED][]            | Done        |
 Documentation | [DV_PLAN_COMPLETED][]                 | Done        |
 Testbench     | [TB_TOP_CREATED][]                    | Done        |
 Testbench     | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done        |
@@ -118,7 +118,7 @@
 Testbench     | [SIM_RAL_MODEL_GEN_AUTOMATED][]       | Done        |
 Testbench     | [CSR_CHECK_GEN_AUTOMATED][]           | Done        |
 Testbench     | [TB_GEN_AUTOMATED][]                  | N/A         |
-Tests         | [SIM_SMOKE_TEST_PASSING][]            | Not Started |
+Tests         | [SIM_SMOKE_TEST_PASSING][]            | Done        |
 Tests         | [SIM_CSR_MEM_TEST_SUITE_PASSING][]    | Done        |
 Tests         | [FPV_MAIN_ASSERTIONS_PROVEN][]        | N/A         |
 Tool Setup    | [SIM_ALT_TOOL_SETUP][]                | Done        |