[top] Auto generate files
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index f7bb7fe..c171adb 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -6575,6 +6575,11 @@
otbn
keymgr
kmac
+ otp_ctrl
+ csrng
+ edn0
+ edn1
+ entropy_src
]
interrupt:
[
@@ -7280,6 +7285,175 @@
type: interrupt
module_name: kmac
}
+ {
+ name: otp_ctrl_otp_operation_done
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ module_name: otp_ctrl
+ }
+ {
+ name: otp_ctrl_otp_error
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ module_name: otp_ctrl
+ }
+ {
+ name: csrng_cs_cmd_req_done
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ module_name: csrng
+ }
+ {
+ name: csrng_cs_entropy_req
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ module_name: csrng
+ }
+ {
+ name: csrng_cs_hw_inst_exc
+ width: 1
+ bits: "2"
+ bitinfo:
+ [
+ 4
+ 1
+ 2
+ ]
+ type: interrupt
+ module_name: csrng
+ }
+ {
+ name: csrng_cs_fifo_err
+ width: 1
+ bits: "3"
+ bitinfo:
+ [
+ 8
+ 1
+ 3
+ ]
+ type: interrupt
+ module_name: csrng
+ }
+ {
+ name: edn0_edn_cmd_req_done
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ module_name: edn0
+ }
+ {
+ name: edn0_edn_fifo_err
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ module_name: edn0
+ }
+ {
+ name: edn1_edn_cmd_req_done
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ module_name: edn1
+ }
+ {
+ name: edn1_edn_fifo_err
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ module_name: edn1
+ }
+ {
+ name: entropy_src_es_entropy_valid
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ module_name: entropy_src
+ }
+ {
+ name: entropy_src_es_health_test_failed
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ module_name: entropy_src
+ }
+ {
+ name: entropy_src_es_fifo_err
+ width: 1
+ bits: "2"
+ bitinfo:
+ [
+ 4
+ 1
+ 2
+ ]
+ type: interrupt
+ module_name: entropy_src
+ }
]
alert_module:
[
diff --git a/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson b/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson
index 9f00bad..7659895 100644
--- a/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson
+++ b/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson
@@ -25,7 +25,7 @@
{ name: "NumSrc",
desc: "Number of interrupt sources",
type: "int",
- default: "86",
+ default: "99",
local: "true"
},
{ name: "NumTarget",
@@ -757,6 +757,110 @@
{ bits: "1:0" }
],
}
+ { name: "PRIO86",
+ desc: "Interrupt Source 86 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO87",
+ desc: "Interrupt Source 87 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO88",
+ desc: "Interrupt Source 88 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO89",
+ desc: "Interrupt Source 89 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO90",
+ desc: "Interrupt Source 90 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO91",
+ desc: "Interrupt Source 91 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO92",
+ desc: "Interrupt Source 92 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO93",
+ desc: "Interrupt Source 93 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO94",
+ desc: "Interrupt Source 94 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO95",
+ desc: "Interrupt Source 95 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO96",
+ desc: "Interrupt Source 96 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO97",
+ desc: "Interrupt Source 97 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO98",
+ desc: "Interrupt Source 98 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
{ skipto: "512" }
{ multireg: {
name: "IE0",
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
index c9d3307..5e45d1f 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
@@ -180,11 +180,24 @@
assign prio[83] = reg2hw.prio83.q;
assign prio[84] = reg2hw.prio84.q;
assign prio[85] = reg2hw.prio85.q;
+ assign prio[86] = reg2hw.prio86.q;
+ assign prio[87] = reg2hw.prio87.q;
+ assign prio[88] = reg2hw.prio88.q;
+ assign prio[89] = reg2hw.prio89.q;
+ assign prio[90] = reg2hw.prio90.q;
+ assign prio[91] = reg2hw.prio91.q;
+ assign prio[92] = reg2hw.prio92.q;
+ assign prio[93] = reg2hw.prio93.q;
+ assign prio[94] = reg2hw.prio94.q;
+ assign prio[95] = reg2hw.prio95.q;
+ assign prio[96] = reg2hw.prio96.q;
+ assign prio[97] = reg2hw.prio97.q;
+ assign prio[98] = reg2hw.prio98.q;
//////////////////////
// Interrupt Enable //
//////////////////////
- for (genvar s = 0; s < 86; s++) begin : gen_ie0
+ for (genvar s = 0; s < 99; s++) begin : gen_ie0
assign ie[0][s] = reg2hw.ie0[s].q;
end
@@ -210,7 +223,7 @@
////////
// IP //
////////
- for (genvar s = 0; s < 86; s++) begin : gen_ip
+ for (genvar s = 0; s < 99; s++) begin : gen_ip
assign hw2reg.ip[s].de = 1'b1; // Always write
assign hw2reg.ip[s].d = ip[s];
end
@@ -218,7 +231,7 @@
///////////////////////////////////
// Detection:: 0: Level, 1: Edge //
///////////////////////////////////
- for (genvar s = 0; s < 86; s++) begin : gen_le
+ for (genvar s = 0; s < 99; s++) begin : gen_le
assign le[s] = reg2hw.le[s].q;
end
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv
index be9fdd7..9cffea9 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv
@@ -7,7 +7,7 @@
package rv_plic_reg_pkg;
// Param list
- parameter int NumSrc = 86;
+ parameter int NumSrc = 99;
parameter int NumTarget = 1;
parameter int PrioWidth = 2;
@@ -363,6 +363,58 @@
} rv_plic_reg2hw_prio85_reg_t;
typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio86_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio87_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio88_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio89_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio90_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio91_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio92_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio93_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio94_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio95_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio96_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio97_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio98_reg_t;
+
+ typedef struct packed {
logic q;
} rv_plic_reg2hw_ie0_mreg_t;
@@ -395,94 +447,107 @@
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- rv_plic_reg2hw_le_mreg_t [85:0] le; // [355:270]
- rv_plic_reg2hw_prio0_reg_t prio0; // [269:268]
- rv_plic_reg2hw_prio1_reg_t prio1; // [267:266]
- rv_plic_reg2hw_prio2_reg_t prio2; // [265:264]
- rv_plic_reg2hw_prio3_reg_t prio3; // [263:262]
- rv_plic_reg2hw_prio4_reg_t prio4; // [261:260]
- rv_plic_reg2hw_prio5_reg_t prio5; // [259:258]
- rv_plic_reg2hw_prio6_reg_t prio6; // [257:256]
- rv_plic_reg2hw_prio7_reg_t prio7; // [255:254]
- rv_plic_reg2hw_prio8_reg_t prio8; // [253:252]
- rv_plic_reg2hw_prio9_reg_t prio9; // [251:250]
- rv_plic_reg2hw_prio10_reg_t prio10; // [249:248]
- rv_plic_reg2hw_prio11_reg_t prio11; // [247:246]
- rv_plic_reg2hw_prio12_reg_t prio12; // [245:244]
- rv_plic_reg2hw_prio13_reg_t prio13; // [243:242]
- rv_plic_reg2hw_prio14_reg_t prio14; // [241:240]
- rv_plic_reg2hw_prio15_reg_t prio15; // [239:238]
- rv_plic_reg2hw_prio16_reg_t prio16; // [237:236]
- rv_plic_reg2hw_prio17_reg_t prio17; // [235:234]
- rv_plic_reg2hw_prio18_reg_t prio18; // [233:232]
- rv_plic_reg2hw_prio19_reg_t prio19; // [231:230]
- rv_plic_reg2hw_prio20_reg_t prio20; // [229:228]
- rv_plic_reg2hw_prio21_reg_t prio21; // [227:226]
- rv_plic_reg2hw_prio22_reg_t prio22; // [225:224]
- rv_plic_reg2hw_prio23_reg_t prio23; // [223:222]
- rv_plic_reg2hw_prio24_reg_t prio24; // [221:220]
- rv_plic_reg2hw_prio25_reg_t prio25; // [219:218]
- rv_plic_reg2hw_prio26_reg_t prio26; // [217:216]
- rv_plic_reg2hw_prio27_reg_t prio27; // [215:214]
- rv_plic_reg2hw_prio28_reg_t prio28; // [213:212]
- rv_plic_reg2hw_prio29_reg_t prio29; // [211:210]
- rv_plic_reg2hw_prio30_reg_t prio30; // [209:208]
- rv_plic_reg2hw_prio31_reg_t prio31; // [207:206]
- rv_plic_reg2hw_prio32_reg_t prio32; // [205:204]
- rv_plic_reg2hw_prio33_reg_t prio33; // [203:202]
- rv_plic_reg2hw_prio34_reg_t prio34; // [201:200]
- rv_plic_reg2hw_prio35_reg_t prio35; // [199:198]
- rv_plic_reg2hw_prio36_reg_t prio36; // [197:196]
- rv_plic_reg2hw_prio37_reg_t prio37; // [195:194]
- rv_plic_reg2hw_prio38_reg_t prio38; // [193:192]
- rv_plic_reg2hw_prio39_reg_t prio39; // [191:190]
- rv_plic_reg2hw_prio40_reg_t prio40; // [189:188]
- rv_plic_reg2hw_prio41_reg_t prio41; // [187:186]
- rv_plic_reg2hw_prio42_reg_t prio42; // [185:184]
- rv_plic_reg2hw_prio43_reg_t prio43; // [183:182]
- rv_plic_reg2hw_prio44_reg_t prio44; // [181:180]
- rv_plic_reg2hw_prio45_reg_t prio45; // [179:178]
- rv_plic_reg2hw_prio46_reg_t prio46; // [177:176]
- rv_plic_reg2hw_prio47_reg_t prio47; // [175:174]
- rv_plic_reg2hw_prio48_reg_t prio48; // [173:172]
- rv_plic_reg2hw_prio49_reg_t prio49; // [171:170]
- rv_plic_reg2hw_prio50_reg_t prio50; // [169:168]
- rv_plic_reg2hw_prio51_reg_t prio51; // [167:166]
- rv_plic_reg2hw_prio52_reg_t prio52; // [165:164]
- rv_plic_reg2hw_prio53_reg_t prio53; // [163:162]
- rv_plic_reg2hw_prio54_reg_t prio54; // [161:160]
- rv_plic_reg2hw_prio55_reg_t prio55; // [159:158]
- rv_plic_reg2hw_prio56_reg_t prio56; // [157:156]
- rv_plic_reg2hw_prio57_reg_t prio57; // [155:154]
- rv_plic_reg2hw_prio58_reg_t prio58; // [153:152]
- rv_plic_reg2hw_prio59_reg_t prio59; // [151:150]
- rv_plic_reg2hw_prio60_reg_t prio60; // [149:148]
- rv_plic_reg2hw_prio61_reg_t prio61; // [147:146]
- rv_plic_reg2hw_prio62_reg_t prio62; // [145:144]
- rv_plic_reg2hw_prio63_reg_t prio63; // [143:142]
- rv_plic_reg2hw_prio64_reg_t prio64; // [141:140]
- rv_plic_reg2hw_prio65_reg_t prio65; // [139:138]
- rv_plic_reg2hw_prio66_reg_t prio66; // [137:136]
- rv_plic_reg2hw_prio67_reg_t prio67; // [135:134]
- rv_plic_reg2hw_prio68_reg_t prio68; // [133:132]
- rv_plic_reg2hw_prio69_reg_t prio69; // [131:130]
- rv_plic_reg2hw_prio70_reg_t prio70; // [129:128]
- rv_plic_reg2hw_prio71_reg_t prio71; // [127:126]
- rv_plic_reg2hw_prio72_reg_t prio72; // [125:124]
- rv_plic_reg2hw_prio73_reg_t prio73; // [123:122]
- rv_plic_reg2hw_prio74_reg_t prio74; // [121:120]
- rv_plic_reg2hw_prio75_reg_t prio75; // [119:118]
- rv_plic_reg2hw_prio76_reg_t prio76; // [117:116]
- rv_plic_reg2hw_prio77_reg_t prio77; // [115:114]
- rv_plic_reg2hw_prio78_reg_t prio78; // [113:112]
- rv_plic_reg2hw_prio79_reg_t prio79; // [111:110]
- rv_plic_reg2hw_prio80_reg_t prio80; // [109:108]
- rv_plic_reg2hw_prio81_reg_t prio81; // [107:106]
- rv_plic_reg2hw_prio82_reg_t prio82; // [105:104]
- rv_plic_reg2hw_prio83_reg_t prio83; // [103:102]
- rv_plic_reg2hw_prio84_reg_t prio84; // [101:100]
- rv_plic_reg2hw_prio85_reg_t prio85; // [99:98]
- rv_plic_reg2hw_ie0_mreg_t [85:0] ie0; // [97:12]
+ rv_plic_reg2hw_le_mreg_t [98:0] le; // [407:309]
+ rv_plic_reg2hw_prio0_reg_t prio0; // [308:307]
+ rv_plic_reg2hw_prio1_reg_t prio1; // [306:305]
+ rv_plic_reg2hw_prio2_reg_t prio2; // [304:303]
+ rv_plic_reg2hw_prio3_reg_t prio3; // [302:301]
+ rv_plic_reg2hw_prio4_reg_t prio4; // [300:299]
+ rv_plic_reg2hw_prio5_reg_t prio5; // [298:297]
+ rv_plic_reg2hw_prio6_reg_t prio6; // [296:295]
+ rv_plic_reg2hw_prio7_reg_t prio7; // [294:293]
+ rv_plic_reg2hw_prio8_reg_t prio8; // [292:291]
+ rv_plic_reg2hw_prio9_reg_t prio9; // [290:289]
+ rv_plic_reg2hw_prio10_reg_t prio10; // [288:287]
+ rv_plic_reg2hw_prio11_reg_t prio11; // [286:285]
+ rv_plic_reg2hw_prio12_reg_t prio12; // [284:283]
+ rv_plic_reg2hw_prio13_reg_t prio13; // [282:281]
+ rv_plic_reg2hw_prio14_reg_t prio14; // [280:279]
+ rv_plic_reg2hw_prio15_reg_t prio15; // [278:277]
+ rv_plic_reg2hw_prio16_reg_t prio16; // [276:275]
+ rv_plic_reg2hw_prio17_reg_t prio17; // [274:273]
+ rv_plic_reg2hw_prio18_reg_t prio18; // [272:271]
+ rv_plic_reg2hw_prio19_reg_t prio19; // [270:269]
+ rv_plic_reg2hw_prio20_reg_t prio20; // [268:267]
+ rv_plic_reg2hw_prio21_reg_t prio21; // [266:265]
+ rv_plic_reg2hw_prio22_reg_t prio22; // [264:263]
+ rv_plic_reg2hw_prio23_reg_t prio23; // [262:261]
+ rv_plic_reg2hw_prio24_reg_t prio24; // [260:259]
+ rv_plic_reg2hw_prio25_reg_t prio25; // [258:257]
+ rv_plic_reg2hw_prio26_reg_t prio26; // [256:255]
+ rv_plic_reg2hw_prio27_reg_t prio27; // [254:253]
+ rv_plic_reg2hw_prio28_reg_t prio28; // [252:251]
+ rv_plic_reg2hw_prio29_reg_t prio29; // [250:249]
+ rv_plic_reg2hw_prio30_reg_t prio30; // [248:247]
+ rv_plic_reg2hw_prio31_reg_t prio31; // [246:245]
+ rv_plic_reg2hw_prio32_reg_t prio32; // [244:243]
+ rv_plic_reg2hw_prio33_reg_t prio33; // [242:241]
+ rv_plic_reg2hw_prio34_reg_t prio34; // [240:239]
+ rv_plic_reg2hw_prio35_reg_t prio35; // [238:237]
+ rv_plic_reg2hw_prio36_reg_t prio36; // [236:235]
+ rv_plic_reg2hw_prio37_reg_t prio37; // [234:233]
+ rv_plic_reg2hw_prio38_reg_t prio38; // [232:231]
+ rv_plic_reg2hw_prio39_reg_t prio39; // [230:229]
+ rv_plic_reg2hw_prio40_reg_t prio40; // [228:227]
+ rv_plic_reg2hw_prio41_reg_t prio41; // [226:225]
+ rv_plic_reg2hw_prio42_reg_t prio42; // [224:223]
+ rv_plic_reg2hw_prio43_reg_t prio43; // [222:221]
+ rv_plic_reg2hw_prio44_reg_t prio44; // [220:219]
+ rv_plic_reg2hw_prio45_reg_t prio45; // [218:217]
+ rv_plic_reg2hw_prio46_reg_t prio46; // [216:215]
+ rv_plic_reg2hw_prio47_reg_t prio47; // [214:213]
+ rv_plic_reg2hw_prio48_reg_t prio48; // [212:211]
+ rv_plic_reg2hw_prio49_reg_t prio49; // [210:209]
+ rv_plic_reg2hw_prio50_reg_t prio50; // [208:207]
+ rv_plic_reg2hw_prio51_reg_t prio51; // [206:205]
+ rv_plic_reg2hw_prio52_reg_t prio52; // [204:203]
+ rv_plic_reg2hw_prio53_reg_t prio53; // [202:201]
+ rv_plic_reg2hw_prio54_reg_t prio54; // [200:199]
+ rv_plic_reg2hw_prio55_reg_t prio55; // [198:197]
+ rv_plic_reg2hw_prio56_reg_t prio56; // [196:195]
+ rv_plic_reg2hw_prio57_reg_t prio57; // [194:193]
+ rv_plic_reg2hw_prio58_reg_t prio58; // [192:191]
+ rv_plic_reg2hw_prio59_reg_t prio59; // [190:189]
+ rv_plic_reg2hw_prio60_reg_t prio60; // [188:187]
+ rv_plic_reg2hw_prio61_reg_t prio61; // [186:185]
+ rv_plic_reg2hw_prio62_reg_t prio62; // [184:183]
+ rv_plic_reg2hw_prio63_reg_t prio63; // [182:181]
+ rv_plic_reg2hw_prio64_reg_t prio64; // [180:179]
+ rv_plic_reg2hw_prio65_reg_t prio65; // [178:177]
+ rv_plic_reg2hw_prio66_reg_t prio66; // [176:175]
+ rv_plic_reg2hw_prio67_reg_t prio67; // [174:173]
+ rv_plic_reg2hw_prio68_reg_t prio68; // [172:171]
+ rv_plic_reg2hw_prio69_reg_t prio69; // [170:169]
+ rv_plic_reg2hw_prio70_reg_t prio70; // [168:167]
+ rv_plic_reg2hw_prio71_reg_t prio71; // [166:165]
+ rv_plic_reg2hw_prio72_reg_t prio72; // [164:163]
+ rv_plic_reg2hw_prio73_reg_t prio73; // [162:161]
+ rv_plic_reg2hw_prio74_reg_t prio74; // [160:159]
+ rv_plic_reg2hw_prio75_reg_t prio75; // [158:157]
+ rv_plic_reg2hw_prio76_reg_t prio76; // [156:155]
+ rv_plic_reg2hw_prio77_reg_t prio77; // [154:153]
+ rv_plic_reg2hw_prio78_reg_t prio78; // [152:151]
+ rv_plic_reg2hw_prio79_reg_t prio79; // [150:149]
+ rv_plic_reg2hw_prio80_reg_t prio80; // [148:147]
+ rv_plic_reg2hw_prio81_reg_t prio81; // [146:145]
+ rv_plic_reg2hw_prio82_reg_t prio82; // [144:143]
+ rv_plic_reg2hw_prio83_reg_t prio83; // [142:141]
+ rv_plic_reg2hw_prio84_reg_t prio84; // [140:139]
+ rv_plic_reg2hw_prio85_reg_t prio85; // [138:137]
+ rv_plic_reg2hw_prio86_reg_t prio86; // [136:135]
+ rv_plic_reg2hw_prio87_reg_t prio87; // [134:133]
+ rv_plic_reg2hw_prio88_reg_t prio88; // [132:131]
+ rv_plic_reg2hw_prio89_reg_t prio89; // [130:129]
+ rv_plic_reg2hw_prio90_reg_t prio90; // [128:127]
+ rv_plic_reg2hw_prio91_reg_t prio91; // [126:125]
+ rv_plic_reg2hw_prio92_reg_t prio92; // [124:123]
+ rv_plic_reg2hw_prio93_reg_t prio93; // [122:121]
+ rv_plic_reg2hw_prio94_reg_t prio94; // [120:119]
+ rv_plic_reg2hw_prio95_reg_t prio95; // [118:117]
+ rv_plic_reg2hw_prio96_reg_t prio96; // [116:115]
+ rv_plic_reg2hw_prio97_reg_t prio97; // [114:113]
+ rv_plic_reg2hw_prio98_reg_t prio98; // [112:111]
+ rv_plic_reg2hw_ie0_mreg_t [98:0] ie0; // [110:12]
rv_plic_reg2hw_threshold0_reg_t threshold0; // [11:10]
rv_plic_reg2hw_cc0_reg_t cc0; // [9:1]
rv_plic_reg2hw_msip0_reg_t msip0; // [0:0]
@@ -492,7 +557,7 @@
// Internal design logic to register //
///////////////////////////////////////
typedef struct packed {
- rv_plic_hw2reg_ip_mreg_t [85:0] ip; // [178:7]
+ rv_plic_hw2reg_ip_mreg_t [98:0] ip; // [204:7]
rv_plic_hw2reg_cc0_reg_t cc0; // [6:0]
} rv_plic_hw2reg_t;
@@ -500,101 +565,117 @@
parameter logic [9:0] RV_PLIC_IP_0_OFFSET = 10'h 0;
parameter logic [9:0] RV_PLIC_IP_1_OFFSET = 10'h 4;
parameter logic [9:0] RV_PLIC_IP_2_OFFSET = 10'h 8;
- parameter logic [9:0] RV_PLIC_LE_0_OFFSET = 10'h c;
- parameter logic [9:0] RV_PLIC_LE_1_OFFSET = 10'h 10;
- parameter logic [9:0] RV_PLIC_LE_2_OFFSET = 10'h 14;
- parameter logic [9:0] RV_PLIC_PRIO0_OFFSET = 10'h 18;
- parameter logic [9:0] RV_PLIC_PRIO1_OFFSET = 10'h 1c;
- parameter logic [9:0] RV_PLIC_PRIO2_OFFSET = 10'h 20;
- parameter logic [9:0] RV_PLIC_PRIO3_OFFSET = 10'h 24;
- parameter logic [9:0] RV_PLIC_PRIO4_OFFSET = 10'h 28;
- parameter logic [9:0] RV_PLIC_PRIO5_OFFSET = 10'h 2c;
- parameter logic [9:0] RV_PLIC_PRIO6_OFFSET = 10'h 30;
- parameter logic [9:0] RV_PLIC_PRIO7_OFFSET = 10'h 34;
- parameter logic [9:0] RV_PLIC_PRIO8_OFFSET = 10'h 38;
- parameter logic [9:0] RV_PLIC_PRIO9_OFFSET = 10'h 3c;
- parameter logic [9:0] RV_PLIC_PRIO10_OFFSET = 10'h 40;
- parameter logic [9:0] RV_PLIC_PRIO11_OFFSET = 10'h 44;
- parameter logic [9:0] RV_PLIC_PRIO12_OFFSET = 10'h 48;
- parameter logic [9:0] RV_PLIC_PRIO13_OFFSET = 10'h 4c;
- parameter logic [9:0] RV_PLIC_PRIO14_OFFSET = 10'h 50;
- parameter logic [9:0] RV_PLIC_PRIO15_OFFSET = 10'h 54;
- parameter logic [9:0] RV_PLIC_PRIO16_OFFSET = 10'h 58;
- parameter logic [9:0] RV_PLIC_PRIO17_OFFSET = 10'h 5c;
- parameter logic [9:0] RV_PLIC_PRIO18_OFFSET = 10'h 60;
- parameter logic [9:0] RV_PLIC_PRIO19_OFFSET = 10'h 64;
- parameter logic [9:0] RV_PLIC_PRIO20_OFFSET = 10'h 68;
- parameter logic [9:0] RV_PLIC_PRIO21_OFFSET = 10'h 6c;
- parameter logic [9:0] RV_PLIC_PRIO22_OFFSET = 10'h 70;
- parameter logic [9:0] RV_PLIC_PRIO23_OFFSET = 10'h 74;
- parameter logic [9:0] RV_PLIC_PRIO24_OFFSET = 10'h 78;
- parameter logic [9:0] RV_PLIC_PRIO25_OFFSET = 10'h 7c;
- parameter logic [9:0] RV_PLIC_PRIO26_OFFSET = 10'h 80;
- parameter logic [9:0] RV_PLIC_PRIO27_OFFSET = 10'h 84;
- parameter logic [9:0] RV_PLIC_PRIO28_OFFSET = 10'h 88;
- parameter logic [9:0] RV_PLIC_PRIO29_OFFSET = 10'h 8c;
- parameter logic [9:0] RV_PLIC_PRIO30_OFFSET = 10'h 90;
- parameter logic [9:0] RV_PLIC_PRIO31_OFFSET = 10'h 94;
- parameter logic [9:0] RV_PLIC_PRIO32_OFFSET = 10'h 98;
- parameter logic [9:0] RV_PLIC_PRIO33_OFFSET = 10'h 9c;
- parameter logic [9:0] RV_PLIC_PRIO34_OFFSET = 10'h a0;
- parameter logic [9:0] RV_PLIC_PRIO35_OFFSET = 10'h a4;
- parameter logic [9:0] RV_PLIC_PRIO36_OFFSET = 10'h a8;
- parameter logic [9:0] RV_PLIC_PRIO37_OFFSET = 10'h ac;
- parameter logic [9:0] RV_PLIC_PRIO38_OFFSET = 10'h b0;
- parameter logic [9:0] RV_PLIC_PRIO39_OFFSET = 10'h b4;
- parameter logic [9:0] RV_PLIC_PRIO40_OFFSET = 10'h b8;
- parameter logic [9:0] RV_PLIC_PRIO41_OFFSET = 10'h bc;
- parameter logic [9:0] RV_PLIC_PRIO42_OFFSET = 10'h c0;
- parameter logic [9:0] RV_PLIC_PRIO43_OFFSET = 10'h c4;
- parameter logic [9:0] RV_PLIC_PRIO44_OFFSET = 10'h c8;
- parameter logic [9:0] RV_PLIC_PRIO45_OFFSET = 10'h cc;
- parameter logic [9:0] RV_PLIC_PRIO46_OFFSET = 10'h d0;
- parameter logic [9:0] RV_PLIC_PRIO47_OFFSET = 10'h d4;
- parameter logic [9:0] RV_PLIC_PRIO48_OFFSET = 10'h d8;
- parameter logic [9:0] RV_PLIC_PRIO49_OFFSET = 10'h dc;
- parameter logic [9:0] RV_PLIC_PRIO50_OFFSET = 10'h e0;
- parameter logic [9:0] RV_PLIC_PRIO51_OFFSET = 10'h e4;
- parameter logic [9:0] RV_PLIC_PRIO52_OFFSET = 10'h e8;
- parameter logic [9:0] RV_PLIC_PRIO53_OFFSET = 10'h ec;
- parameter logic [9:0] RV_PLIC_PRIO54_OFFSET = 10'h f0;
- parameter logic [9:0] RV_PLIC_PRIO55_OFFSET = 10'h f4;
- parameter logic [9:0] RV_PLIC_PRIO56_OFFSET = 10'h f8;
- parameter logic [9:0] RV_PLIC_PRIO57_OFFSET = 10'h fc;
- parameter logic [9:0] RV_PLIC_PRIO58_OFFSET = 10'h 100;
- parameter logic [9:0] RV_PLIC_PRIO59_OFFSET = 10'h 104;
- parameter logic [9:0] RV_PLIC_PRIO60_OFFSET = 10'h 108;
- parameter logic [9:0] RV_PLIC_PRIO61_OFFSET = 10'h 10c;
- parameter logic [9:0] RV_PLIC_PRIO62_OFFSET = 10'h 110;
- parameter logic [9:0] RV_PLIC_PRIO63_OFFSET = 10'h 114;
- parameter logic [9:0] RV_PLIC_PRIO64_OFFSET = 10'h 118;
- parameter logic [9:0] RV_PLIC_PRIO65_OFFSET = 10'h 11c;
- parameter logic [9:0] RV_PLIC_PRIO66_OFFSET = 10'h 120;
- parameter logic [9:0] RV_PLIC_PRIO67_OFFSET = 10'h 124;
- parameter logic [9:0] RV_PLIC_PRIO68_OFFSET = 10'h 128;
- parameter logic [9:0] RV_PLIC_PRIO69_OFFSET = 10'h 12c;
- parameter logic [9:0] RV_PLIC_PRIO70_OFFSET = 10'h 130;
- parameter logic [9:0] RV_PLIC_PRIO71_OFFSET = 10'h 134;
- parameter logic [9:0] RV_PLIC_PRIO72_OFFSET = 10'h 138;
- parameter logic [9:0] RV_PLIC_PRIO73_OFFSET = 10'h 13c;
- parameter logic [9:0] RV_PLIC_PRIO74_OFFSET = 10'h 140;
- parameter logic [9:0] RV_PLIC_PRIO75_OFFSET = 10'h 144;
- parameter logic [9:0] RV_PLIC_PRIO76_OFFSET = 10'h 148;
- parameter logic [9:0] RV_PLIC_PRIO77_OFFSET = 10'h 14c;
- parameter logic [9:0] RV_PLIC_PRIO78_OFFSET = 10'h 150;
- parameter logic [9:0] RV_PLIC_PRIO79_OFFSET = 10'h 154;
- parameter logic [9:0] RV_PLIC_PRIO80_OFFSET = 10'h 158;
- parameter logic [9:0] RV_PLIC_PRIO81_OFFSET = 10'h 15c;
- parameter logic [9:0] RV_PLIC_PRIO82_OFFSET = 10'h 160;
- parameter logic [9:0] RV_PLIC_PRIO83_OFFSET = 10'h 164;
- parameter logic [9:0] RV_PLIC_PRIO84_OFFSET = 10'h 168;
- parameter logic [9:0] RV_PLIC_PRIO85_OFFSET = 10'h 16c;
+ parameter logic [9:0] RV_PLIC_IP_3_OFFSET = 10'h c;
+ parameter logic [9:0] RV_PLIC_LE_0_OFFSET = 10'h 10;
+ parameter logic [9:0] RV_PLIC_LE_1_OFFSET = 10'h 14;
+ parameter logic [9:0] RV_PLIC_LE_2_OFFSET = 10'h 18;
+ parameter logic [9:0] RV_PLIC_LE_3_OFFSET = 10'h 1c;
+ parameter logic [9:0] RV_PLIC_PRIO0_OFFSET = 10'h 20;
+ parameter logic [9:0] RV_PLIC_PRIO1_OFFSET = 10'h 24;
+ parameter logic [9:0] RV_PLIC_PRIO2_OFFSET = 10'h 28;
+ parameter logic [9:0] RV_PLIC_PRIO3_OFFSET = 10'h 2c;
+ parameter logic [9:0] RV_PLIC_PRIO4_OFFSET = 10'h 30;
+ parameter logic [9:0] RV_PLIC_PRIO5_OFFSET = 10'h 34;
+ parameter logic [9:0] RV_PLIC_PRIO6_OFFSET = 10'h 38;
+ parameter logic [9:0] RV_PLIC_PRIO7_OFFSET = 10'h 3c;
+ parameter logic [9:0] RV_PLIC_PRIO8_OFFSET = 10'h 40;
+ parameter logic [9:0] RV_PLIC_PRIO9_OFFSET = 10'h 44;
+ parameter logic [9:0] RV_PLIC_PRIO10_OFFSET = 10'h 48;
+ parameter logic [9:0] RV_PLIC_PRIO11_OFFSET = 10'h 4c;
+ parameter logic [9:0] RV_PLIC_PRIO12_OFFSET = 10'h 50;
+ parameter logic [9:0] RV_PLIC_PRIO13_OFFSET = 10'h 54;
+ parameter logic [9:0] RV_PLIC_PRIO14_OFFSET = 10'h 58;
+ parameter logic [9:0] RV_PLIC_PRIO15_OFFSET = 10'h 5c;
+ parameter logic [9:0] RV_PLIC_PRIO16_OFFSET = 10'h 60;
+ parameter logic [9:0] RV_PLIC_PRIO17_OFFSET = 10'h 64;
+ parameter logic [9:0] RV_PLIC_PRIO18_OFFSET = 10'h 68;
+ parameter logic [9:0] RV_PLIC_PRIO19_OFFSET = 10'h 6c;
+ parameter logic [9:0] RV_PLIC_PRIO20_OFFSET = 10'h 70;
+ parameter logic [9:0] RV_PLIC_PRIO21_OFFSET = 10'h 74;
+ parameter logic [9:0] RV_PLIC_PRIO22_OFFSET = 10'h 78;
+ parameter logic [9:0] RV_PLIC_PRIO23_OFFSET = 10'h 7c;
+ parameter logic [9:0] RV_PLIC_PRIO24_OFFSET = 10'h 80;
+ parameter logic [9:0] RV_PLIC_PRIO25_OFFSET = 10'h 84;
+ parameter logic [9:0] RV_PLIC_PRIO26_OFFSET = 10'h 88;
+ parameter logic [9:0] RV_PLIC_PRIO27_OFFSET = 10'h 8c;
+ parameter logic [9:0] RV_PLIC_PRIO28_OFFSET = 10'h 90;
+ parameter logic [9:0] RV_PLIC_PRIO29_OFFSET = 10'h 94;
+ parameter logic [9:0] RV_PLIC_PRIO30_OFFSET = 10'h 98;
+ parameter logic [9:0] RV_PLIC_PRIO31_OFFSET = 10'h 9c;
+ parameter logic [9:0] RV_PLIC_PRIO32_OFFSET = 10'h a0;
+ parameter logic [9:0] RV_PLIC_PRIO33_OFFSET = 10'h a4;
+ parameter logic [9:0] RV_PLIC_PRIO34_OFFSET = 10'h a8;
+ parameter logic [9:0] RV_PLIC_PRIO35_OFFSET = 10'h ac;
+ parameter logic [9:0] RV_PLIC_PRIO36_OFFSET = 10'h b0;
+ parameter logic [9:0] RV_PLIC_PRIO37_OFFSET = 10'h b4;
+ parameter logic [9:0] RV_PLIC_PRIO38_OFFSET = 10'h b8;
+ parameter logic [9:0] RV_PLIC_PRIO39_OFFSET = 10'h bc;
+ parameter logic [9:0] RV_PLIC_PRIO40_OFFSET = 10'h c0;
+ parameter logic [9:0] RV_PLIC_PRIO41_OFFSET = 10'h c4;
+ parameter logic [9:0] RV_PLIC_PRIO42_OFFSET = 10'h c8;
+ parameter logic [9:0] RV_PLIC_PRIO43_OFFSET = 10'h cc;
+ parameter logic [9:0] RV_PLIC_PRIO44_OFFSET = 10'h d0;
+ parameter logic [9:0] RV_PLIC_PRIO45_OFFSET = 10'h d4;
+ parameter logic [9:0] RV_PLIC_PRIO46_OFFSET = 10'h d8;
+ parameter logic [9:0] RV_PLIC_PRIO47_OFFSET = 10'h dc;
+ parameter logic [9:0] RV_PLIC_PRIO48_OFFSET = 10'h e0;
+ parameter logic [9:0] RV_PLIC_PRIO49_OFFSET = 10'h e4;
+ parameter logic [9:0] RV_PLIC_PRIO50_OFFSET = 10'h e8;
+ parameter logic [9:0] RV_PLIC_PRIO51_OFFSET = 10'h ec;
+ parameter logic [9:0] RV_PLIC_PRIO52_OFFSET = 10'h f0;
+ parameter logic [9:0] RV_PLIC_PRIO53_OFFSET = 10'h f4;
+ parameter logic [9:0] RV_PLIC_PRIO54_OFFSET = 10'h f8;
+ parameter logic [9:0] RV_PLIC_PRIO55_OFFSET = 10'h fc;
+ parameter logic [9:0] RV_PLIC_PRIO56_OFFSET = 10'h 100;
+ parameter logic [9:0] RV_PLIC_PRIO57_OFFSET = 10'h 104;
+ parameter logic [9:0] RV_PLIC_PRIO58_OFFSET = 10'h 108;
+ parameter logic [9:0] RV_PLIC_PRIO59_OFFSET = 10'h 10c;
+ parameter logic [9:0] RV_PLIC_PRIO60_OFFSET = 10'h 110;
+ parameter logic [9:0] RV_PLIC_PRIO61_OFFSET = 10'h 114;
+ parameter logic [9:0] RV_PLIC_PRIO62_OFFSET = 10'h 118;
+ parameter logic [9:0] RV_PLIC_PRIO63_OFFSET = 10'h 11c;
+ parameter logic [9:0] RV_PLIC_PRIO64_OFFSET = 10'h 120;
+ parameter logic [9:0] RV_PLIC_PRIO65_OFFSET = 10'h 124;
+ parameter logic [9:0] RV_PLIC_PRIO66_OFFSET = 10'h 128;
+ parameter logic [9:0] RV_PLIC_PRIO67_OFFSET = 10'h 12c;
+ parameter logic [9:0] RV_PLIC_PRIO68_OFFSET = 10'h 130;
+ parameter logic [9:0] RV_PLIC_PRIO69_OFFSET = 10'h 134;
+ parameter logic [9:0] RV_PLIC_PRIO70_OFFSET = 10'h 138;
+ parameter logic [9:0] RV_PLIC_PRIO71_OFFSET = 10'h 13c;
+ parameter logic [9:0] RV_PLIC_PRIO72_OFFSET = 10'h 140;
+ parameter logic [9:0] RV_PLIC_PRIO73_OFFSET = 10'h 144;
+ parameter logic [9:0] RV_PLIC_PRIO74_OFFSET = 10'h 148;
+ parameter logic [9:0] RV_PLIC_PRIO75_OFFSET = 10'h 14c;
+ parameter logic [9:0] RV_PLIC_PRIO76_OFFSET = 10'h 150;
+ parameter logic [9:0] RV_PLIC_PRIO77_OFFSET = 10'h 154;
+ parameter logic [9:0] RV_PLIC_PRIO78_OFFSET = 10'h 158;
+ parameter logic [9:0] RV_PLIC_PRIO79_OFFSET = 10'h 15c;
+ parameter logic [9:0] RV_PLIC_PRIO80_OFFSET = 10'h 160;
+ parameter logic [9:0] RV_PLIC_PRIO81_OFFSET = 10'h 164;
+ parameter logic [9:0] RV_PLIC_PRIO82_OFFSET = 10'h 168;
+ parameter logic [9:0] RV_PLIC_PRIO83_OFFSET = 10'h 16c;
+ parameter logic [9:0] RV_PLIC_PRIO84_OFFSET = 10'h 170;
+ parameter logic [9:0] RV_PLIC_PRIO85_OFFSET = 10'h 174;
+ parameter logic [9:0] RV_PLIC_PRIO86_OFFSET = 10'h 178;
+ parameter logic [9:0] RV_PLIC_PRIO87_OFFSET = 10'h 17c;
+ parameter logic [9:0] RV_PLIC_PRIO88_OFFSET = 10'h 180;
+ parameter logic [9:0] RV_PLIC_PRIO89_OFFSET = 10'h 184;
+ parameter logic [9:0] RV_PLIC_PRIO90_OFFSET = 10'h 188;
+ parameter logic [9:0] RV_PLIC_PRIO91_OFFSET = 10'h 18c;
+ parameter logic [9:0] RV_PLIC_PRIO92_OFFSET = 10'h 190;
+ parameter logic [9:0] RV_PLIC_PRIO93_OFFSET = 10'h 194;
+ parameter logic [9:0] RV_PLIC_PRIO94_OFFSET = 10'h 198;
+ parameter logic [9:0] RV_PLIC_PRIO95_OFFSET = 10'h 19c;
+ parameter logic [9:0] RV_PLIC_PRIO96_OFFSET = 10'h 1a0;
+ parameter logic [9:0] RV_PLIC_PRIO97_OFFSET = 10'h 1a4;
+ parameter logic [9:0] RV_PLIC_PRIO98_OFFSET = 10'h 1a8;
parameter logic [9:0] RV_PLIC_IE0_0_OFFSET = 10'h 200;
parameter logic [9:0] RV_PLIC_IE0_1_OFFSET = 10'h 204;
parameter logic [9:0] RV_PLIC_IE0_2_OFFSET = 10'h 208;
- parameter logic [9:0] RV_PLIC_THRESHOLD0_OFFSET = 10'h 20c;
- parameter logic [9:0] RV_PLIC_CC0_OFFSET = 10'h 210;
- parameter logic [9:0] RV_PLIC_MSIP0_OFFSET = 10'h 214;
+ parameter logic [9:0] RV_PLIC_IE0_3_OFFSET = 10'h 20c;
+ parameter logic [9:0] RV_PLIC_THRESHOLD0_OFFSET = 10'h 210;
+ parameter logic [9:0] RV_PLIC_CC0_OFFSET = 10'h 214;
+ parameter logic [9:0] RV_PLIC_MSIP0_OFFSET = 10'h 218;
// Register Index
@@ -602,9 +683,11 @@
RV_PLIC_IP_0,
RV_PLIC_IP_1,
RV_PLIC_IP_2,
+ RV_PLIC_IP_3,
RV_PLIC_LE_0,
RV_PLIC_LE_1,
RV_PLIC_LE_2,
+ RV_PLIC_LE_3,
RV_PLIC_PRIO0,
RV_PLIC_PRIO1,
RV_PLIC_PRIO2,
@@ -691,114 +774,144 @@
RV_PLIC_PRIO83,
RV_PLIC_PRIO84,
RV_PLIC_PRIO85,
+ RV_PLIC_PRIO86,
+ RV_PLIC_PRIO87,
+ RV_PLIC_PRIO88,
+ RV_PLIC_PRIO89,
+ RV_PLIC_PRIO90,
+ RV_PLIC_PRIO91,
+ RV_PLIC_PRIO92,
+ RV_PLIC_PRIO93,
+ RV_PLIC_PRIO94,
+ RV_PLIC_PRIO95,
+ RV_PLIC_PRIO96,
+ RV_PLIC_PRIO97,
+ RV_PLIC_PRIO98,
RV_PLIC_IE0_0,
RV_PLIC_IE0_1,
RV_PLIC_IE0_2,
+ RV_PLIC_IE0_3,
RV_PLIC_THRESHOLD0,
RV_PLIC_CC0,
RV_PLIC_MSIP0
} rv_plic_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] RV_PLIC_PERMIT [98] = '{
- 4'b 1111, // index[ 0] RV_PLIC_IP_0
- 4'b 1111, // index[ 1] RV_PLIC_IP_1
- 4'b 0111, // index[ 2] RV_PLIC_IP_2
- 4'b 1111, // index[ 3] RV_PLIC_LE_0
- 4'b 1111, // index[ 4] RV_PLIC_LE_1
- 4'b 0111, // index[ 5] RV_PLIC_LE_2
- 4'b 0001, // index[ 6] RV_PLIC_PRIO0
- 4'b 0001, // index[ 7] RV_PLIC_PRIO1
- 4'b 0001, // index[ 8] RV_PLIC_PRIO2
- 4'b 0001, // index[ 9] RV_PLIC_PRIO3
- 4'b 0001, // index[10] RV_PLIC_PRIO4
- 4'b 0001, // index[11] RV_PLIC_PRIO5
- 4'b 0001, // index[12] RV_PLIC_PRIO6
- 4'b 0001, // index[13] RV_PLIC_PRIO7
- 4'b 0001, // index[14] RV_PLIC_PRIO8
- 4'b 0001, // index[15] RV_PLIC_PRIO9
- 4'b 0001, // index[16] RV_PLIC_PRIO10
- 4'b 0001, // index[17] RV_PLIC_PRIO11
- 4'b 0001, // index[18] RV_PLIC_PRIO12
- 4'b 0001, // index[19] RV_PLIC_PRIO13
- 4'b 0001, // index[20] RV_PLIC_PRIO14
- 4'b 0001, // index[21] RV_PLIC_PRIO15
- 4'b 0001, // index[22] RV_PLIC_PRIO16
- 4'b 0001, // index[23] RV_PLIC_PRIO17
- 4'b 0001, // index[24] RV_PLIC_PRIO18
- 4'b 0001, // index[25] RV_PLIC_PRIO19
- 4'b 0001, // index[26] RV_PLIC_PRIO20
- 4'b 0001, // index[27] RV_PLIC_PRIO21
- 4'b 0001, // index[28] RV_PLIC_PRIO22
- 4'b 0001, // index[29] RV_PLIC_PRIO23
- 4'b 0001, // index[30] RV_PLIC_PRIO24
- 4'b 0001, // index[31] RV_PLIC_PRIO25
- 4'b 0001, // index[32] RV_PLIC_PRIO26
- 4'b 0001, // index[33] RV_PLIC_PRIO27
- 4'b 0001, // index[34] RV_PLIC_PRIO28
- 4'b 0001, // index[35] RV_PLIC_PRIO29
- 4'b 0001, // index[36] RV_PLIC_PRIO30
- 4'b 0001, // index[37] RV_PLIC_PRIO31
- 4'b 0001, // index[38] RV_PLIC_PRIO32
- 4'b 0001, // index[39] RV_PLIC_PRIO33
- 4'b 0001, // index[40] RV_PLIC_PRIO34
- 4'b 0001, // index[41] RV_PLIC_PRIO35
- 4'b 0001, // index[42] RV_PLIC_PRIO36
- 4'b 0001, // index[43] RV_PLIC_PRIO37
- 4'b 0001, // index[44] RV_PLIC_PRIO38
- 4'b 0001, // index[45] RV_PLIC_PRIO39
- 4'b 0001, // index[46] RV_PLIC_PRIO40
- 4'b 0001, // index[47] RV_PLIC_PRIO41
- 4'b 0001, // index[48] RV_PLIC_PRIO42
- 4'b 0001, // index[49] RV_PLIC_PRIO43
- 4'b 0001, // index[50] RV_PLIC_PRIO44
- 4'b 0001, // index[51] RV_PLIC_PRIO45
- 4'b 0001, // index[52] RV_PLIC_PRIO46
- 4'b 0001, // index[53] RV_PLIC_PRIO47
- 4'b 0001, // index[54] RV_PLIC_PRIO48
- 4'b 0001, // index[55] RV_PLIC_PRIO49
- 4'b 0001, // index[56] RV_PLIC_PRIO50
- 4'b 0001, // index[57] RV_PLIC_PRIO51
- 4'b 0001, // index[58] RV_PLIC_PRIO52
- 4'b 0001, // index[59] RV_PLIC_PRIO53
- 4'b 0001, // index[60] RV_PLIC_PRIO54
- 4'b 0001, // index[61] RV_PLIC_PRIO55
- 4'b 0001, // index[62] RV_PLIC_PRIO56
- 4'b 0001, // index[63] RV_PLIC_PRIO57
- 4'b 0001, // index[64] RV_PLIC_PRIO58
- 4'b 0001, // index[65] RV_PLIC_PRIO59
- 4'b 0001, // index[66] RV_PLIC_PRIO60
- 4'b 0001, // index[67] RV_PLIC_PRIO61
- 4'b 0001, // index[68] RV_PLIC_PRIO62
- 4'b 0001, // index[69] RV_PLIC_PRIO63
- 4'b 0001, // index[70] RV_PLIC_PRIO64
- 4'b 0001, // index[71] RV_PLIC_PRIO65
- 4'b 0001, // index[72] RV_PLIC_PRIO66
- 4'b 0001, // index[73] RV_PLIC_PRIO67
- 4'b 0001, // index[74] RV_PLIC_PRIO68
- 4'b 0001, // index[75] RV_PLIC_PRIO69
- 4'b 0001, // index[76] RV_PLIC_PRIO70
- 4'b 0001, // index[77] RV_PLIC_PRIO71
- 4'b 0001, // index[78] RV_PLIC_PRIO72
- 4'b 0001, // index[79] RV_PLIC_PRIO73
- 4'b 0001, // index[80] RV_PLIC_PRIO74
- 4'b 0001, // index[81] RV_PLIC_PRIO75
- 4'b 0001, // index[82] RV_PLIC_PRIO76
- 4'b 0001, // index[83] RV_PLIC_PRIO77
- 4'b 0001, // index[84] RV_PLIC_PRIO78
- 4'b 0001, // index[85] RV_PLIC_PRIO79
- 4'b 0001, // index[86] RV_PLIC_PRIO80
- 4'b 0001, // index[87] RV_PLIC_PRIO81
- 4'b 0001, // index[88] RV_PLIC_PRIO82
- 4'b 0001, // index[89] RV_PLIC_PRIO83
- 4'b 0001, // index[90] RV_PLIC_PRIO84
- 4'b 0001, // index[91] RV_PLIC_PRIO85
- 4'b 1111, // index[92] RV_PLIC_IE0_0
- 4'b 1111, // index[93] RV_PLIC_IE0_1
- 4'b 0111, // index[94] RV_PLIC_IE0_2
- 4'b 0001, // index[95] RV_PLIC_THRESHOLD0
- 4'b 0001, // index[96] RV_PLIC_CC0
- 4'b 0001 // index[97] RV_PLIC_MSIP0
+ parameter logic [3:0] RV_PLIC_PERMIT [114] = '{
+ 4'b 1111, // index[ 0] RV_PLIC_IP_0
+ 4'b 1111, // index[ 1] RV_PLIC_IP_1
+ 4'b 1111, // index[ 2] RV_PLIC_IP_2
+ 4'b 0001, // index[ 3] RV_PLIC_IP_3
+ 4'b 1111, // index[ 4] RV_PLIC_LE_0
+ 4'b 1111, // index[ 5] RV_PLIC_LE_1
+ 4'b 1111, // index[ 6] RV_PLIC_LE_2
+ 4'b 0001, // index[ 7] RV_PLIC_LE_3
+ 4'b 0001, // index[ 8] RV_PLIC_PRIO0
+ 4'b 0001, // index[ 9] RV_PLIC_PRIO1
+ 4'b 0001, // index[ 10] RV_PLIC_PRIO2
+ 4'b 0001, // index[ 11] RV_PLIC_PRIO3
+ 4'b 0001, // index[ 12] RV_PLIC_PRIO4
+ 4'b 0001, // index[ 13] RV_PLIC_PRIO5
+ 4'b 0001, // index[ 14] RV_PLIC_PRIO6
+ 4'b 0001, // index[ 15] RV_PLIC_PRIO7
+ 4'b 0001, // index[ 16] RV_PLIC_PRIO8
+ 4'b 0001, // index[ 17] RV_PLIC_PRIO9
+ 4'b 0001, // index[ 18] RV_PLIC_PRIO10
+ 4'b 0001, // index[ 19] RV_PLIC_PRIO11
+ 4'b 0001, // index[ 20] RV_PLIC_PRIO12
+ 4'b 0001, // index[ 21] RV_PLIC_PRIO13
+ 4'b 0001, // index[ 22] RV_PLIC_PRIO14
+ 4'b 0001, // index[ 23] RV_PLIC_PRIO15
+ 4'b 0001, // index[ 24] RV_PLIC_PRIO16
+ 4'b 0001, // index[ 25] RV_PLIC_PRIO17
+ 4'b 0001, // index[ 26] RV_PLIC_PRIO18
+ 4'b 0001, // index[ 27] RV_PLIC_PRIO19
+ 4'b 0001, // index[ 28] RV_PLIC_PRIO20
+ 4'b 0001, // index[ 29] RV_PLIC_PRIO21
+ 4'b 0001, // index[ 30] RV_PLIC_PRIO22
+ 4'b 0001, // index[ 31] RV_PLIC_PRIO23
+ 4'b 0001, // index[ 32] RV_PLIC_PRIO24
+ 4'b 0001, // index[ 33] RV_PLIC_PRIO25
+ 4'b 0001, // index[ 34] RV_PLIC_PRIO26
+ 4'b 0001, // index[ 35] RV_PLIC_PRIO27
+ 4'b 0001, // index[ 36] RV_PLIC_PRIO28
+ 4'b 0001, // index[ 37] RV_PLIC_PRIO29
+ 4'b 0001, // index[ 38] RV_PLIC_PRIO30
+ 4'b 0001, // index[ 39] RV_PLIC_PRIO31
+ 4'b 0001, // index[ 40] RV_PLIC_PRIO32
+ 4'b 0001, // index[ 41] RV_PLIC_PRIO33
+ 4'b 0001, // index[ 42] RV_PLIC_PRIO34
+ 4'b 0001, // index[ 43] RV_PLIC_PRIO35
+ 4'b 0001, // index[ 44] RV_PLIC_PRIO36
+ 4'b 0001, // index[ 45] RV_PLIC_PRIO37
+ 4'b 0001, // index[ 46] RV_PLIC_PRIO38
+ 4'b 0001, // index[ 47] RV_PLIC_PRIO39
+ 4'b 0001, // index[ 48] RV_PLIC_PRIO40
+ 4'b 0001, // index[ 49] RV_PLIC_PRIO41
+ 4'b 0001, // index[ 50] RV_PLIC_PRIO42
+ 4'b 0001, // index[ 51] RV_PLIC_PRIO43
+ 4'b 0001, // index[ 52] RV_PLIC_PRIO44
+ 4'b 0001, // index[ 53] RV_PLIC_PRIO45
+ 4'b 0001, // index[ 54] RV_PLIC_PRIO46
+ 4'b 0001, // index[ 55] RV_PLIC_PRIO47
+ 4'b 0001, // index[ 56] RV_PLIC_PRIO48
+ 4'b 0001, // index[ 57] RV_PLIC_PRIO49
+ 4'b 0001, // index[ 58] RV_PLIC_PRIO50
+ 4'b 0001, // index[ 59] RV_PLIC_PRIO51
+ 4'b 0001, // index[ 60] RV_PLIC_PRIO52
+ 4'b 0001, // index[ 61] RV_PLIC_PRIO53
+ 4'b 0001, // index[ 62] RV_PLIC_PRIO54
+ 4'b 0001, // index[ 63] RV_PLIC_PRIO55
+ 4'b 0001, // index[ 64] RV_PLIC_PRIO56
+ 4'b 0001, // index[ 65] RV_PLIC_PRIO57
+ 4'b 0001, // index[ 66] RV_PLIC_PRIO58
+ 4'b 0001, // index[ 67] RV_PLIC_PRIO59
+ 4'b 0001, // index[ 68] RV_PLIC_PRIO60
+ 4'b 0001, // index[ 69] RV_PLIC_PRIO61
+ 4'b 0001, // index[ 70] RV_PLIC_PRIO62
+ 4'b 0001, // index[ 71] RV_PLIC_PRIO63
+ 4'b 0001, // index[ 72] RV_PLIC_PRIO64
+ 4'b 0001, // index[ 73] RV_PLIC_PRIO65
+ 4'b 0001, // index[ 74] RV_PLIC_PRIO66
+ 4'b 0001, // index[ 75] RV_PLIC_PRIO67
+ 4'b 0001, // index[ 76] RV_PLIC_PRIO68
+ 4'b 0001, // index[ 77] RV_PLIC_PRIO69
+ 4'b 0001, // index[ 78] RV_PLIC_PRIO70
+ 4'b 0001, // index[ 79] RV_PLIC_PRIO71
+ 4'b 0001, // index[ 80] RV_PLIC_PRIO72
+ 4'b 0001, // index[ 81] RV_PLIC_PRIO73
+ 4'b 0001, // index[ 82] RV_PLIC_PRIO74
+ 4'b 0001, // index[ 83] RV_PLIC_PRIO75
+ 4'b 0001, // index[ 84] RV_PLIC_PRIO76
+ 4'b 0001, // index[ 85] RV_PLIC_PRIO77
+ 4'b 0001, // index[ 86] RV_PLIC_PRIO78
+ 4'b 0001, // index[ 87] RV_PLIC_PRIO79
+ 4'b 0001, // index[ 88] RV_PLIC_PRIO80
+ 4'b 0001, // index[ 89] RV_PLIC_PRIO81
+ 4'b 0001, // index[ 90] RV_PLIC_PRIO82
+ 4'b 0001, // index[ 91] RV_PLIC_PRIO83
+ 4'b 0001, // index[ 92] RV_PLIC_PRIO84
+ 4'b 0001, // index[ 93] RV_PLIC_PRIO85
+ 4'b 0001, // index[ 94] RV_PLIC_PRIO86
+ 4'b 0001, // index[ 95] RV_PLIC_PRIO87
+ 4'b 0001, // index[ 96] RV_PLIC_PRIO88
+ 4'b 0001, // index[ 97] RV_PLIC_PRIO89
+ 4'b 0001, // index[ 98] RV_PLIC_PRIO90
+ 4'b 0001, // index[ 99] RV_PLIC_PRIO91
+ 4'b 0001, // index[100] RV_PLIC_PRIO92
+ 4'b 0001, // index[101] RV_PLIC_PRIO93
+ 4'b 0001, // index[102] RV_PLIC_PRIO94
+ 4'b 0001, // index[103] RV_PLIC_PRIO95
+ 4'b 0001, // index[104] RV_PLIC_PRIO96
+ 4'b 0001, // index[105] RV_PLIC_PRIO97
+ 4'b 0001, // index[106] RV_PLIC_PRIO98
+ 4'b 1111, // index[107] RV_PLIC_IE0_0
+ 4'b 1111, // index[108] RV_PLIC_IE0_1
+ 4'b 1111, // index[109] RV_PLIC_IE0_2
+ 4'b 0001, // index[110] RV_PLIC_IE0_3
+ 4'b 0001, // index[111] RV_PLIC_THRESHOLD0
+ 4'b 0001, // index[112] RV_PLIC_CC0
+ 4'b 0001 // index[113] RV_PLIC_MSIP0
};
endpackage
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
index 9a832d7..7779c2a 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
@@ -157,6 +157,19 @@
logic ip_2_p_83_qs;
logic ip_2_p_84_qs;
logic ip_2_p_85_qs;
+ logic ip_2_p_86_qs;
+ logic ip_2_p_87_qs;
+ logic ip_2_p_88_qs;
+ logic ip_2_p_89_qs;
+ logic ip_2_p_90_qs;
+ logic ip_2_p_91_qs;
+ logic ip_2_p_92_qs;
+ logic ip_2_p_93_qs;
+ logic ip_2_p_94_qs;
+ logic ip_2_p_95_qs;
+ logic ip_3_p_96_qs;
+ logic ip_3_p_97_qs;
+ logic ip_3_p_98_qs;
logic le_0_le_0_qs;
logic le_0_le_0_wd;
logic le_0_le_0_we;
@@ -415,6 +428,45 @@
logic le_2_le_85_qs;
logic le_2_le_85_wd;
logic le_2_le_85_we;
+ logic le_2_le_86_qs;
+ logic le_2_le_86_wd;
+ logic le_2_le_86_we;
+ logic le_2_le_87_qs;
+ logic le_2_le_87_wd;
+ logic le_2_le_87_we;
+ logic le_2_le_88_qs;
+ logic le_2_le_88_wd;
+ logic le_2_le_88_we;
+ logic le_2_le_89_qs;
+ logic le_2_le_89_wd;
+ logic le_2_le_89_we;
+ logic le_2_le_90_qs;
+ logic le_2_le_90_wd;
+ logic le_2_le_90_we;
+ logic le_2_le_91_qs;
+ logic le_2_le_91_wd;
+ logic le_2_le_91_we;
+ logic le_2_le_92_qs;
+ logic le_2_le_92_wd;
+ logic le_2_le_92_we;
+ logic le_2_le_93_qs;
+ logic le_2_le_93_wd;
+ logic le_2_le_93_we;
+ logic le_2_le_94_qs;
+ logic le_2_le_94_wd;
+ logic le_2_le_94_we;
+ logic le_2_le_95_qs;
+ logic le_2_le_95_wd;
+ logic le_2_le_95_we;
+ logic le_3_le_96_qs;
+ logic le_3_le_96_wd;
+ logic le_3_le_96_we;
+ logic le_3_le_97_qs;
+ logic le_3_le_97_wd;
+ logic le_3_le_97_we;
+ logic le_3_le_98_qs;
+ logic le_3_le_98_wd;
+ logic le_3_le_98_we;
logic [1:0] prio0_qs;
logic [1:0] prio0_wd;
logic prio0_we;
@@ -673,6 +725,45 @@
logic [1:0] prio85_qs;
logic [1:0] prio85_wd;
logic prio85_we;
+ logic [1:0] prio86_qs;
+ logic [1:0] prio86_wd;
+ logic prio86_we;
+ logic [1:0] prio87_qs;
+ logic [1:0] prio87_wd;
+ logic prio87_we;
+ logic [1:0] prio88_qs;
+ logic [1:0] prio88_wd;
+ logic prio88_we;
+ logic [1:0] prio89_qs;
+ logic [1:0] prio89_wd;
+ logic prio89_we;
+ logic [1:0] prio90_qs;
+ logic [1:0] prio90_wd;
+ logic prio90_we;
+ logic [1:0] prio91_qs;
+ logic [1:0] prio91_wd;
+ logic prio91_we;
+ logic [1:0] prio92_qs;
+ logic [1:0] prio92_wd;
+ logic prio92_we;
+ logic [1:0] prio93_qs;
+ logic [1:0] prio93_wd;
+ logic prio93_we;
+ logic [1:0] prio94_qs;
+ logic [1:0] prio94_wd;
+ logic prio94_we;
+ logic [1:0] prio95_qs;
+ logic [1:0] prio95_wd;
+ logic prio95_we;
+ logic [1:0] prio96_qs;
+ logic [1:0] prio96_wd;
+ logic prio96_we;
+ logic [1:0] prio97_qs;
+ logic [1:0] prio97_wd;
+ logic prio97_we;
+ logic [1:0] prio98_qs;
+ logic [1:0] prio98_wd;
+ logic prio98_we;
logic ie0_0_e_0_qs;
logic ie0_0_e_0_wd;
logic ie0_0_e_0_we;
@@ -931,6 +1022,45 @@
logic ie0_2_e_85_qs;
logic ie0_2_e_85_wd;
logic ie0_2_e_85_we;
+ logic ie0_2_e_86_qs;
+ logic ie0_2_e_86_wd;
+ logic ie0_2_e_86_we;
+ logic ie0_2_e_87_qs;
+ logic ie0_2_e_87_wd;
+ logic ie0_2_e_87_we;
+ logic ie0_2_e_88_qs;
+ logic ie0_2_e_88_wd;
+ logic ie0_2_e_88_we;
+ logic ie0_2_e_89_qs;
+ logic ie0_2_e_89_wd;
+ logic ie0_2_e_89_we;
+ logic ie0_2_e_90_qs;
+ logic ie0_2_e_90_wd;
+ logic ie0_2_e_90_we;
+ logic ie0_2_e_91_qs;
+ logic ie0_2_e_91_wd;
+ logic ie0_2_e_91_we;
+ logic ie0_2_e_92_qs;
+ logic ie0_2_e_92_wd;
+ logic ie0_2_e_92_we;
+ logic ie0_2_e_93_qs;
+ logic ie0_2_e_93_wd;
+ logic ie0_2_e_93_we;
+ logic ie0_2_e_94_qs;
+ logic ie0_2_e_94_wd;
+ logic ie0_2_e_94_we;
+ logic ie0_2_e_95_qs;
+ logic ie0_2_e_95_wd;
+ logic ie0_2_e_95_we;
+ logic ie0_3_e_96_qs;
+ logic ie0_3_e_96_wd;
+ logic ie0_3_e_96_we;
+ logic ie0_3_e_97_qs;
+ logic ie0_3_e_97_wd;
+ logic ie0_3_e_97_we;
+ logic ie0_3_e_98_qs;
+ logic ie0_3_e_98_wd;
+ logic ie0_3_e_98_we;
logic [1:0] threshold0_qs;
logic [1:0] threshold0_wd;
logic threshold0_we;
@@ -3103,6 +3233,334 @@
);
+ // F[p_86]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_86 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[86].de),
+ .d (hw2reg.ip[86].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_2_p_86_qs)
+ );
+
+
+ // F[p_87]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_87 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[87].de),
+ .d (hw2reg.ip[87].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_2_p_87_qs)
+ );
+
+
+ // F[p_88]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_88 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[88].de),
+ .d (hw2reg.ip[88].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_2_p_88_qs)
+ );
+
+
+ // F[p_89]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_89 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[89].de),
+ .d (hw2reg.ip[89].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_2_p_89_qs)
+ );
+
+
+ // F[p_90]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_90 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[90].de),
+ .d (hw2reg.ip[90].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_2_p_90_qs)
+ );
+
+
+ // F[p_91]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_91 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[91].de),
+ .d (hw2reg.ip[91].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_2_p_91_qs)
+ );
+
+
+ // F[p_92]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_92 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[92].de),
+ .d (hw2reg.ip[92].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_2_p_92_qs)
+ );
+
+
+ // F[p_93]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_93 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[93].de),
+ .d (hw2reg.ip[93].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_2_p_93_qs)
+ );
+
+
+ // F[p_94]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_94 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[94].de),
+ .d (hw2reg.ip[94].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_2_p_94_qs)
+ );
+
+
+ // F[p_95]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_95 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[95].de),
+ .d (hw2reg.ip[95].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_2_p_95_qs)
+ );
+
+
+ // Subregister 96 of Multireg ip
+ // R[ip_3]: V(False)
+
+ // F[p_96]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_96 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[96].de),
+ .d (hw2reg.ip[96].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_96_qs)
+ );
+
+
+ // F[p_97]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_97 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[97].de),
+ .d (hw2reg.ip[97].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_97_qs)
+ );
+
+
+ // F[p_98]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_98 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[98].de),
+ .d (hw2reg.ip[98].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_3_p_98_qs)
+ );
+
+
// Subregister 0 of Multireg le
@@ -5350,6 +5808,347 @@
);
+ // F[le_86]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_2_le_86 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_2_le_86_we),
+ .wd (le_2_le_86_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[86].q ),
+
+ // to register interface (read)
+ .qs (le_2_le_86_qs)
+ );
+
+
+ // F[le_87]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_2_le_87 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_2_le_87_we),
+ .wd (le_2_le_87_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[87].q ),
+
+ // to register interface (read)
+ .qs (le_2_le_87_qs)
+ );
+
+
+ // F[le_88]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_2_le_88 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_2_le_88_we),
+ .wd (le_2_le_88_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[88].q ),
+
+ // to register interface (read)
+ .qs (le_2_le_88_qs)
+ );
+
+
+ // F[le_89]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_2_le_89 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_2_le_89_we),
+ .wd (le_2_le_89_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[89].q ),
+
+ // to register interface (read)
+ .qs (le_2_le_89_qs)
+ );
+
+
+ // F[le_90]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_2_le_90 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_2_le_90_we),
+ .wd (le_2_le_90_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[90].q ),
+
+ // to register interface (read)
+ .qs (le_2_le_90_qs)
+ );
+
+
+ // F[le_91]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_2_le_91 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_2_le_91_we),
+ .wd (le_2_le_91_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[91].q ),
+
+ // to register interface (read)
+ .qs (le_2_le_91_qs)
+ );
+
+
+ // F[le_92]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_2_le_92 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_2_le_92_we),
+ .wd (le_2_le_92_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[92].q ),
+
+ // to register interface (read)
+ .qs (le_2_le_92_qs)
+ );
+
+
+ // F[le_93]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_2_le_93 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_2_le_93_we),
+ .wd (le_2_le_93_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[93].q ),
+
+ // to register interface (read)
+ .qs (le_2_le_93_qs)
+ );
+
+
+ // F[le_94]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_2_le_94 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_2_le_94_we),
+ .wd (le_2_le_94_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[94].q ),
+
+ // to register interface (read)
+ .qs (le_2_le_94_qs)
+ );
+
+
+ // F[le_95]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_2_le_95 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_2_le_95_we),
+ .wd (le_2_le_95_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[95].q ),
+
+ // to register interface (read)
+ .qs (le_2_le_95_qs)
+ );
+
+
+ // Subregister 96 of Multireg le
+ // R[le_3]: V(False)
+
+ // F[le_96]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_96 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_96_we),
+ .wd (le_3_le_96_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[96].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_96_qs)
+ );
+
+
+ // F[le_97]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_97 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_97_we),
+ .wd (le_3_le_97_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[97].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_97_qs)
+ );
+
+
+ // F[le_98]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_3_le_98 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_3_le_98_we),
+ .wd (le_3_le_98_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[98].q ),
+
+ // to register interface (read)
+ .qs (le_3_le_98_qs)
+ );
+
+
// R[prio0]: V(False)
@@ -7673,6 +8472,357 @@
);
+ // R[prio86]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio86 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio86_we),
+ .wd (prio86_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio86.q ),
+
+ // to register interface (read)
+ .qs (prio86_qs)
+ );
+
+
+ // R[prio87]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio87 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio87_we),
+ .wd (prio87_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio87.q ),
+
+ // to register interface (read)
+ .qs (prio87_qs)
+ );
+
+
+ // R[prio88]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio88 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio88_we),
+ .wd (prio88_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio88.q ),
+
+ // to register interface (read)
+ .qs (prio88_qs)
+ );
+
+
+ // R[prio89]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio89 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio89_we),
+ .wd (prio89_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio89.q ),
+
+ // to register interface (read)
+ .qs (prio89_qs)
+ );
+
+
+ // R[prio90]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio90 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio90_we),
+ .wd (prio90_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio90.q ),
+
+ // to register interface (read)
+ .qs (prio90_qs)
+ );
+
+
+ // R[prio91]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio91 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio91_we),
+ .wd (prio91_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio91.q ),
+
+ // to register interface (read)
+ .qs (prio91_qs)
+ );
+
+
+ // R[prio92]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio92 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio92_we),
+ .wd (prio92_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio92.q ),
+
+ // to register interface (read)
+ .qs (prio92_qs)
+ );
+
+
+ // R[prio93]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio93 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio93_we),
+ .wd (prio93_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio93.q ),
+
+ // to register interface (read)
+ .qs (prio93_qs)
+ );
+
+
+ // R[prio94]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio94 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio94_we),
+ .wd (prio94_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio94.q ),
+
+ // to register interface (read)
+ .qs (prio94_qs)
+ );
+
+
+ // R[prio95]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio95 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio95_we),
+ .wd (prio95_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio95.q ),
+
+ // to register interface (read)
+ .qs (prio95_qs)
+ );
+
+
+ // R[prio96]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio96 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio96_we),
+ .wd (prio96_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio96.q ),
+
+ // to register interface (read)
+ .qs (prio96_qs)
+ );
+
+
+ // R[prio97]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio97 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio97_we),
+ .wd (prio97_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio97.q ),
+
+ // to register interface (read)
+ .qs (prio97_qs)
+ );
+
+
+ // R[prio98]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio98 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio98_we),
+ .wd (prio98_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio98.q ),
+
+ // to register interface (read)
+ .qs (prio98_qs)
+ );
+
+
// Subregister 0 of Multireg ie0
// R[ie0_0]: V(False)
@@ -9919,6 +11069,347 @@
);
+ // F[e_86]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_86 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_2_e_86_we),
+ .wd (ie0_2_e_86_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[86].q ),
+
+ // to register interface (read)
+ .qs (ie0_2_e_86_qs)
+ );
+
+
+ // F[e_87]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_87 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_2_e_87_we),
+ .wd (ie0_2_e_87_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[87].q ),
+
+ // to register interface (read)
+ .qs (ie0_2_e_87_qs)
+ );
+
+
+ // F[e_88]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_88 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_2_e_88_we),
+ .wd (ie0_2_e_88_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[88].q ),
+
+ // to register interface (read)
+ .qs (ie0_2_e_88_qs)
+ );
+
+
+ // F[e_89]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_89 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_2_e_89_we),
+ .wd (ie0_2_e_89_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[89].q ),
+
+ // to register interface (read)
+ .qs (ie0_2_e_89_qs)
+ );
+
+
+ // F[e_90]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_90 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_2_e_90_we),
+ .wd (ie0_2_e_90_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[90].q ),
+
+ // to register interface (read)
+ .qs (ie0_2_e_90_qs)
+ );
+
+
+ // F[e_91]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_91 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_2_e_91_we),
+ .wd (ie0_2_e_91_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[91].q ),
+
+ // to register interface (read)
+ .qs (ie0_2_e_91_qs)
+ );
+
+
+ // F[e_92]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_92 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_2_e_92_we),
+ .wd (ie0_2_e_92_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[92].q ),
+
+ // to register interface (read)
+ .qs (ie0_2_e_92_qs)
+ );
+
+
+ // F[e_93]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_93 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_2_e_93_we),
+ .wd (ie0_2_e_93_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[93].q ),
+
+ // to register interface (read)
+ .qs (ie0_2_e_93_qs)
+ );
+
+
+ // F[e_94]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_94 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_2_e_94_we),
+ .wd (ie0_2_e_94_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[94].q ),
+
+ // to register interface (read)
+ .qs (ie0_2_e_94_qs)
+ );
+
+
+ // F[e_95]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_95 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_2_e_95_we),
+ .wd (ie0_2_e_95_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[95].q ),
+
+ // to register interface (read)
+ .qs (ie0_2_e_95_qs)
+ );
+
+
+ // Subregister 96 of Multireg ie0
+ // R[ie0_3]: V(False)
+
+ // F[e_96]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_96 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_96_we),
+ .wd (ie0_3_e_96_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[96].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_96_qs)
+ );
+
+
+ // F[e_97]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_97 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_97_we),
+ .wd (ie0_3_e_97_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[97].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_97_qs)
+ );
+
+
+ // F[e_98]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_98 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_3_e_98_we),
+ .wd (ie0_3_e_98_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[98].q ),
+
+ // to register interface (read)
+ .qs (ie0_3_e_98_qs)
+ );
+
+
// R[threshold0]: V(False)
@@ -9992,107 +11483,123 @@
- logic [97:0] addr_hit;
+ logic [113:0] addr_hit;
always_comb begin
addr_hit = '0;
- addr_hit[ 0] = (reg_addr == RV_PLIC_IP_0_OFFSET);
- addr_hit[ 1] = (reg_addr == RV_PLIC_IP_1_OFFSET);
- addr_hit[ 2] = (reg_addr == RV_PLIC_IP_2_OFFSET);
- addr_hit[ 3] = (reg_addr == RV_PLIC_LE_0_OFFSET);
- addr_hit[ 4] = (reg_addr == RV_PLIC_LE_1_OFFSET);
- addr_hit[ 5] = (reg_addr == RV_PLIC_LE_2_OFFSET);
- addr_hit[ 6] = (reg_addr == RV_PLIC_PRIO0_OFFSET);
- addr_hit[ 7] = (reg_addr == RV_PLIC_PRIO1_OFFSET);
- addr_hit[ 8] = (reg_addr == RV_PLIC_PRIO2_OFFSET);
- addr_hit[ 9] = (reg_addr == RV_PLIC_PRIO3_OFFSET);
- addr_hit[10] = (reg_addr == RV_PLIC_PRIO4_OFFSET);
- addr_hit[11] = (reg_addr == RV_PLIC_PRIO5_OFFSET);
- addr_hit[12] = (reg_addr == RV_PLIC_PRIO6_OFFSET);
- addr_hit[13] = (reg_addr == RV_PLIC_PRIO7_OFFSET);
- addr_hit[14] = (reg_addr == RV_PLIC_PRIO8_OFFSET);
- addr_hit[15] = (reg_addr == RV_PLIC_PRIO9_OFFSET);
- addr_hit[16] = (reg_addr == RV_PLIC_PRIO10_OFFSET);
- addr_hit[17] = (reg_addr == RV_PLIC_PRIO11_OFFSET);
- addr_hit[18] = (reg_addr == RV_PLIC_PRIO12_OFFSET);
- addr_hit[19] = (reg_addr == RV_PLIC_PRIO13_OFFSET);
- addr_hit[20] = (reg_addr == RV_PLIC_PRIO14_OFFSET);
- addr_hit[21] = (reg_addr == RV_PLIC_PRIO15_OFFSET);
- addr_hit[22] = (reg_addr == RV_PLIC_PRIO16_OFFSET);
- addr_hit[23] = (reg_addr == RV_PLIC_PRIO17_OFFSET);
- addr_hit[24] = (reg_addr == RV_PLIC_PRIO18_OFFSET);
- addr_hit[25] = (reg_addr == RV_PLIC_PRIO19_OFFSET);
- addr_hit[26] = (reg_addr == RV_PLIC_PRIO20_OFFSET);
- addr_hit[27] = (reg_addr == RV_PLIC_PRIO21_OFFSET);
- addr_hit[28] = (reg_addr == RV_PLIC_PRIO22_OFFSET);
- addr_hit[29] = (reg_addr == RV_PLIC_PRIO23_OFFSET);
- addr_hit[30] = (reg_addr == RV_PLIC_PRIO24_OFFSET);
- addr_hit[31] = (reg_addr == RV_PLIC_PRIO25_OFFSET);
- addr_hit[32] = (reg_addr == RV_PLIC_PRIO26_OFFSET);
- addr_hit[33] = (reg_addr == RV_PLIC_PRIO27_OFFSET);
- addr_hit[34] = (reg_addr == RV_PLIC_PRIO28_OFFSET);
- addr_hit[35] = (reg_addr == RV_PLIC_PRIO29_OFFSET);
- addr_hit[36] = (reg_addr == RV_PLIC_PRIO30_OFFSET);
- addr_hit[37] = (reg_addr == RV_PLIC_PRIO31_OFFSET);
- addr_hit[38] = (reg_addr == RV_PLIC_PRIO32_OFFSET);
- addr_hit[39] = (reg_addr == RV_PLIC_PRIO33_OFFSET);
- addr_hit[40] = (reg_addr == RV_PLIC_PRIO34_OFFSET);
- addr_hit[41] = (reg_addr == RV_PLIC_PRIO35_OFFSET);
- addr_hit[42] = (reg_addr == RV_PLIC_PRIO36_OFFSET);
- addr_hit[43] = (reg_addr == RV_PLIC_PRIO37_OFFSET);
- addr_hit[44] = (reg_addr == RV_PLIC_PRIO38_OFFSET);
- addr_hit[45] = (reg_addr == RV_PLIC_PRIO39_OFFSET);
- addr_hit[46] = (reg_addr == RV_PLIC_PRIO40_OFFSET);
- addr_hit[47] = (reg_addr == RV_PLIC_PRIO41_OFFSET);
- addr_hit[48] = (reg_addr == RV_PLIC_PRIO42_OFFSET);
- addr_hit[49] = (reg_addr == RV_PLIC_PRIO43_OFFSET);
- addr_hit[50] = (reg_addr == RV_PLIC_PRIO44_OFFSET);
- addr_hit[51] = (reg_addr == RV_PLIC_PRIO45_OFFSET);
- addr_hit[52] = (reg_addr == RV_PLIC_PRIO46_OFFSET);
- addr_hit[53] = (reg_addr == RV_PLIC_PRIO47_OFFSET);
- addr_hit[54] = (reg_addr == RV_PLIC_PRIO48_OFFSET);
- addr_hit[55] = (reg_addr == RV_PLIC_PRIO49_OFFSET);
- addr_hit[56] = (reg_addr == RV_PLIC_PRIO50_OFFSET);
- addr_hit[57] = (reg_addr == RV_PLIC_PRIO51_OFFSET);
- addr_hit[58] = (reg_addr == RV_PLIC_PRIO52_OFFSET);
- addr_hit[59] = (reg_addr == RV_PLIC_PRIO53_OFFSET);
- addr_hit[60] = (reg_addr == RV_PLIC_PRIO54_OFFSET);
- addr_hit[61] = (reg_addr == RV_PLIC_PRIO55_OFFSET);
- addr_hit[62] = (reg_addr == RV_PLIC_PRIO56_OFFSET);
- addr_hit[63] = (reg_addr == RV_PLIC_PRIO57_OFFSET);
- addr_hit[64] = (reg_addr == RV_PLIC_PRIO58_OFFSET);
- addr_hit[65] = (reg_addr == RV_PLIC_PRIO59_OFFSET);
- addr_hit[66] = (reg_addr == RV_PLIC_PRIO60_OFFSET);
- addr_hit[67] = (reg_addr == RV_PLIC_PRIO61_OFFSET);
- addr_hit[68] = (reg_addr == RV_PLIC_PRIO62_OFFSET);
- addr_hit[69] = (reg_addr == RV_PLIC_PRIO63_OFFSET);
- addr_hit[70] = (reg_addr == RV_PLIC_PRIO64_OFFSET);
- addr_hit[71] = (reg_addr == RV_PLIC_PRIO65_OFFSET);
- addr_hit[72] = (reg_addr == RV_PLIC_PRIO66_OFFSET);
- addr_hit[73] = (reg_addr == RV_PLIC_PRIO67_OFFSET);
- addr_hit[74] = (reg_addr == RV_PLIC_PRIO68_OFFSET);
- addr_hit[75] = (reg_addr == RV_PLIC_PRIO69_OFFSET);
- addr_hit[76] = (reg_addr == RV_PLIC_PRIO70_OFFSET);
- addr_hit[77] = (reg_addr == RV_PLIC_PRIO71_OFFSET);
- addr_hit[78] = (reg_addr == RV_PLIC_PRIO72_OFFSET);
- addr_hit[79] = (reg_addr == RV_PLIC_PRIO73_OFFSET);
- addr_hit[80] = (reg_addr == RV_PLIC_PRIO74_OFFSET);
- addr_hit[81] = (reg_addr == RV_PLIC_PRIO75_OFFSET);
- addr_hit[82] = (reg_addr == RV_PLIC_PRIO76_OFFSET);
- addr_hit[83] = (reg_addr == RV_PLIC_PRIO77_OFFSET);
- addr_hit[84] = (reg_addr == RV_PLIC_PRIO78_OFFSET);
- addr_hit[85] = (reg_addr == RV_PLIC_PRIO79_OFFSET);
- addr_hit[86] = (reg_addr == RV_PLIC_PRIO80_OFFSET);
- addr_hit[87] = (reg_addr == RV_PLIC_PRIO81_OFFSET);
- addr_hit[88] = (reg_addr == RV_PLIC_PRIO82_OFFSET);
- addr_hit[89] = (reg_addr == RV_PLIC_PRIO83_OFFSET);
- addr_hit[90] = (reg_addr == RV_PLIC_PRIO84_OFFSET);
- addr_hit[91] = (reg_addr == RV_PLIC_PRIO85_OFFSET);
- addr_hit[92] = (reg_addr == RV_PLIC_IE0_0_OFFSET);
- addr_hit[93] = (reg_addr == RV_PLIC_IE0_1_OFFSET);
- addr_hit[94] = (reg_addr == RV_PLIC_IE0_2_OFFSET);
- addr_hit[95] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
- addr_hit[96] = (reg_addr == RV_PLIC_CC0_OFFSET);
- addr_hit[97] = (reg_addr == RV_PLIC_MSIP0_OFFSET);
+ addr_hit[ 0] = (reg_addr == RV_PLIC_IP_0_OFFSET);
+ addr_hit[ 1] = (reg_addr == RV_PLIC_IP_1_OFFSET);
+ addr_hit[ 2] = (reg_addr == RV_PLIC_IP_2_OFFSET);
+ addr_hit[ 3] = (reg_addr == RV_PLIC_IP_3_OFFSET);
+ addr_hit[ 4] = (reg_addr == RV_PLIC_LE_0_OFFSET);
+ addr_hit[ 5] = (reg_addr == RV_PLIC_LE_1_OFFSET);
+ addr_hit[ 6] = (reg_addr == RV_PLIC_LE_2_OFFSET);
+ addr_hit[ 7] = (reg_addr == RV_PLIC_LE_3_OFFSET);
+ addr_hit[ 8] = (reg_addr == RV_PLIC_PRIO0_OFFSET);
+ addr_hit[ 9] = (reg_addr == RV_PLIC_PRIO1_OFFSET);
+ addr_hit[ 10] = (reg_addr == RV_PLIC_PRIO2_OFFSET);
+ addr_hit[ 11] = (reg_addr == RV_PLIC_PRIO3_OFFSET);
+ addr_hit[ 12] = (reg_addr == RV_PLIC_PRIO4_OFFSET);
+ addr_hit[ 13] = (reg_addr == RV_PLIC_PRIO5_OFFSET);
+ addr_hit[ 14] = (reg_addr == RV_PLIC_PRIO6_OFFSET);
+ addr_hit[ 15] = (reg_addr == RV_PLIC_PRIO7_OFFSET);
+ addr_hit[ 16] = (reg_addr == RV_PLIC_PRIO8_OFFSET);
+ addr_hit[ 17] = (reg_addr == RV_PLIC_PRIO9_OFFSET);
+ addr_hit[ 18] = (reg_addr == RV_PLIC_PRIO10_OFFSET);
+ addr_hit[ 19] = (reg_addr == RV_PLIC_PRIO11_OFFSET);
+ addr_hit[ 20] = (reg_addr == RV_PLIC_PRIO12_OFFSET);
+ addr_hit[ 21] = (reg_addr == RV_PLIC_PRIO13_OFFSET);
+ addr_hit[ 22] = (reg_addr == RV_PLIC_PRIO14_OFFSET);
+ addr_hit[ 23] = (reg_addr == RV_PLIC_PRIO15_OFFSET);
+ addr_hit[ 24] = (reg_addr == RV_PLIC_PRIO16_OFFSET);
+ addr_hit[ 25] = (reg_addr == RV_PLIC_PRIO17_OFFSET);
+ addr_hit[ 26] = (reg_addr == RV_PLIC_PRIO18_OFFSET);
+ addr_hit[ 27] = (reg_addr == RV_PLIC_PRIO19_OFFSET);
+ addr_hit[ 28] = (reg_addr == RV_PLIC_PRIO20_OFFSET);
+ addr_hit[ 29] = (reg_addr == RV_PLIC_PRIO21_OFFSET);
+ addr_hit[ 30] = (reg_addr == RV_PLIC_PRIO22_OFFSET);
+ addr_hit[ 31] = (reg_addr == RV_PLIC_PRIO23_OFFSET);
+ addr_hit[ 32] = (reg_addr == RV_PLIC_PRIO24_OFFSET);
+ addr_hit[ 33] = (reg_addr == RV_PLIC_PRIO25_OFFSET);
+ addr_hit[ 34] = (reg_addr == RV_PLIC_PRIO26_OFFSET);
+ addr_hit[ 35] = (reg_addr == RV_PLIC_PRIO27_OFFSET);
+ addr_hit[ 36] = (reg_addr == RV_PLIC_PRIO28_OFFSET);
+ addr_hit[ 37] = (reg_addr == RV_PLIC_PRIO29_OFFSET);
+ addr_hit[ 38] = (reg_addr == RV_PLIC_PRIO30_OFFSET);
+ addr_hit[ 39] = (reg_addr == RV_PLIC_PRIO31_OFFSET);
+ addr_hit[ 40] = (reg_addr == RV_PLIC_PRIO32_OFFSET);
+ addr_hit[ 41] = (reg_addr == RV_PLIC_PRIO33_OFFSET);
+ addr_hit[ 42] = (reg_addr == RV_PLIC_PRIO34_OFFSET);
+ addr_hit[ 43] = (reg_addr == RV_PLIC_PRIO35_OFFSET);
+ addr_hit[ 44] = (reg_addr == RV_PLIC_PRIO36_OFFSET);
+ addr_hit[ 45] = (reg_addr == RV_PLIC_PRIO37_OFFSET);
+ addr_hit[ 46] = (reg_addr == RV_PLIC_PRIO38_OFFSET);
+ addr_hit[ 47] = (reg_addr == RV_PLIC_PRIO39_OFFSET);
+ addr_hit[ 48] = (reg_addr == RV_PLIC_PRIO40_OFFSET);
+ addr_hit[ 49] = (reg_addr == RV_PLIC_PRIO41_OFFSET);
+ addr_hit[ 50] = (reg_addr == RV_PLIC_PRIO42_OFFSET);
+ addr_hit[ 51] = (reg_addr == RV_PLIC_PRIO43_OFFSET);
+ addr_hit[ 52] = (reg_addr == RV_PLIC_PRIO44_OFFSET);
+ addr_hit[ 53] = (reg_addr == RV_PLIC_PRIO45_OFFSET);
+ addr_hit[ 54] = (reg_addr == RV_PLIC_PRIO46_OFFSET);
+ addr_hit[ 55] = (reg_addr == RV_PLIC_PRIO47_OFFSET);
+ addr_hit[ 56] = (reg_addr == RV_PLIC_PRIO48_OFFSET);
+ addr_hit[ 57] = (reg_addr == RV_PLIC_PRIO49_OFFSET);
+ addr_hit[ 58] = (reg_addr == RV_PLIC_PRIO50_OFFSET);
+ addr_hit[ 59] = (reg_addr == RV_PLIC_PRIO51_OFFSET);
+ addr_hit[ 60] = (reg_addr == RV_PLIC_PRIO52_OFFSET);
+ addr_hit[ 61] = (reg_addr == RV_PLIC_PRIO53_OFFSET);
+ addr_hit[ 62] = (reg_addr == RV_PLIC_PRIO54_OFFSET);
+ addr_hit[ 63] = (reg_addr == RV_PLIC_PRIO55_OFFSET);
+ addr_hit[ 64] = (reg_addr == RV_PLIC_PRIO56_OFFSET);
+ addr_hit[ 65] = (reg_addr == RV_PLIC_PRIO57_OFFSET);
+ addr_hit[ 66] = (reg_addr == RV_PLIC_PRIO58_OFFSET);
+ addr_hit[ 67] = (reg_addr == RV_PLIC_PRIO59_OFFSET);
+ addr_hit[ 68] = (reg_addr == RV_PLIC_PRIO60_OFFSET);
+ addr_hit[ 69] = (reg_addr == RV_PLIC_PRIO61_OFFSET);
+ addr_hit[ 70] = (reg_addr == RV_PLIC_PRIO62_OFFSET);
+ addr_hit[ 71] = (reg_addr == RV_PLIC_PRIO63_OFFSET);
+ addr_hit[ 72] = (reg_addr == RV_PLIC_PRIO64_OFFSET);
+ addr_hit[ 73] = (reg_addr == RV_PLIC_PRIO65_OFFSET);
+ addr_hit[ 74] = (reg_addr == RV_PLIC_PRIO66_OFFSET);
+ addr_hit[ 75] = (reg_addr == RV_PLIC_PRIO67_OFFSET);
+ addr_hit[ 76] = (reg_addr == RV_PLIC_PRIO68_OFFSET);
+ addr_hit[ 77] = (reg_addr == RV_PLIC_PRIO69_OFFSET);
+ addr_hit[ 78] = (reg_addr == RV_PLIC_PRIO70_OFFSET);
+ addr_hit[ 79] = (reg_addr == RV_PLIC_PRIO71_OFFSET);
+ addr_hit[ 80] = (reg_addr == RV_PLIC_PRIO72_OFFSET);
+ addr_hit[ 81] = (reg_addr == RV_PLIC_PRIO73_OFFSET);
+ addr_hit[ 82] = (reg_addr == RV_PLIC_PRIO74_OFFSET);
+ addr_hit[ 83] = (reg_addr == RV_PLIC_PRIO75_OFFSET);
+ addr_hit[ 84] = (reg_addr == RV_PLIC_PRIO76_OFFSET);
+ addr_hit[ 85] = (reg_addr == RV_PLIC_PRIO77_OFFSET);
+ addr_hit[ 86] = (reg_addr == RV_PLIC_PRIO78_OFFSET);
+ addr_hit[ 87] = (reg_addr == RV_PLIC_PRIO79_OFFSET);
+ addr_hit[ 88] = (reg_addr == RV_PLIC_PRIO80_OFFSET);
+ addr_hit[ 89] = (reg_addr == RV_PLIC_PRIO81_OFFSET);
+ addr_hit[ 90] = (reg_addr == RV_PLIC_PRIO82_OFFSET);
+ addr_hit[ 91] = (reg_addr == RV_PLIC_PRIO83_OFFSET);
+ addr_hit[ 92] = (reg_addr == RV_PLIC_PRIO84_OFFSET);
+ addr_hit[ 93] = (reg_addr == RV_PLIC_PRIO85_OFFSET);
+ addr_hit[ 94] = (reg_addr == RV_PLIC_PRIO86_OFFSET);
+ addr_hit[ 95] = (reg_addr == RV_PLIC_PRIO87_OFFSET);
+ addr_hit[ 96] = (reg_addr == RV_PLIC_PRIO88_OFFSET);
+ addr_hit[ 97] = (reg_addr == RV_PLIC_PRIO89_OFFSET);
+ addr_hit[ 98] = (reg_addr == RV_PLIC_PRIO90_OFFSET);
+ addr_hit[ 99] = (reg_addr == RV_PLIC_PRIO91_OFFSET);
+ addr_hit[100] = (reg_addr == RV_PLIC_PRIO92_OFFSET);
+ addr_hit[101] = (reg_addr == RV_PLIC_PRIO93_OFFSET);
+ addr_hit[102] = (reg_addr == RV_PLIC_PRIO94_OFFSET);
+ addr_hit[103] = (reg_addr == RV_PLIC_PRIO95_OFFSET);
+ addr_hit[104] = (reg_addr == RV_PLIC_PRIO96_OFFSET);
+ addr_hit[105] = (reg_addr == RV_PLIC_PRIO97_OFFSET);
+ addr_hit[106] = (reg_addr == RV_PLIC_PRIO98_OFFSET);
+ addr_hit[107] = (reg_addr == RV_PLIC_IE0_0_OFFSET);
+ addr_hit[108] = (reg_addr == RV_PLIC_IE0_1_OFFSET);
+ addr_hit[109] = (reg_addr == RV_PLIC_IE0_2_OFFSET);
+ addr_hit[110] = (reg_addr == RV_PLIC_IE0_3_OFFSET);
+ addr_hit[111] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
+ addr_hit[112] = (reg_addr == RV_PLIC_CC0_OFFSET);
+ addr_hit[113] = (reg_addr == RV_PLIC_MSIP0_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -10100,104 +11607,120 @@
// Check sub-word write is permitted
always_comb begin
wr_err = 1'b0;
- if (addr_hit[ 0] && reg_we && (RV_PLIC_PERMIT[ 0] != (RV_PLIC_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[ 1] && reg_we && (RV_PLIC_PERMIT[ 1] != (RV_PLIC_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[ 2] && reg_we && (RV_PLIC_PERMIT[ 2] != (RV_PLIC_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[ 3] && reg_we && (RV_PLIC_PERMIT[ 3] != (RV_PLIC_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[ 4] && reg_we && (RV_PLIC_PERMIT[ 4] != (RV_PLIC_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[ 5] && reg_we && (RV_PLIC_PERMIT[ 5] != (RV_PLIC_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[ 6] && reg_we && (RV_PLIC_PERMIT[ 6] != (RV_PLIC_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[ 7] && reg_we && (RV_PLIC_PERMIT[ 7] != (RV_PLIC_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[ 8] && reg_we && (RV_PLIC_PERMIT[ 8] != (RV_PLIC_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[ 9] && reg_we && (RV_PLIC_PERMIT[ 9] != (RV_PLIC_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[10] && reg_we && (RV_PLIC_PERMIT[10] != (RV_PLIC_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[11] && reg_we && (RV_PLIC_PERMIT[11] != (RV_PLIC_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[12] && reg_we && (RV_PLIC_PERMIT[12] != (RV_PLIC_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[13] && reg_we && (RV_PLIC_PERMIT[13] != (RV_PLIC_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[14] && reg_we && (RV_PLIC_PERMIT[14] != (RV_PLIC_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[15] && reg_we && (RV_PLIC_PERMIT[15] != (RV_PLIC_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[16] && reg_we && (RV_PLIC_PERMIT[16] != (RV_PLIC_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[17] && reg_we && (RV_PLIC_PERMIT[17] != (RV_PLIC_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[18] && reg_we && (RV_PLIC_PERMIT[18] != (RV_PLIC_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[19] && reg_we && (RV_PLIC_PERMIT[19] != (RV_PLIC_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[20] && reg_we && (RV_PLIC_PERMIT[20] != (RV_PLIC_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[21] && reg_we && (RV_PLIC_PERMIT[21] != (RV_PLIC_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[22] && reg_we && (RV_PLIC_PERMIT[22] != (RV_PLIC_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[23] && reg_we && (RV_PLIC_PERMIT[23] != (RV_PLIC_PERMIT[23] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[24] && reg_we && (RV_PLIC_PERMIT[24] != (RV_PLIC_PERMIT[24] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[25] && reg_we && (RV_PLIC_PERMIT[25] != (RV_PLIC_PERMIT[25] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[26] && reg_we && (RV_PLIC_PERMIT[26] != (RV_PLIC_PERMIT[26] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[27] && reg_we && (RV_PLIC_PERMIT[27] != (RV_PLIC_PERMIT[27] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[28] && reg_we && (RV_PLIC_PERMIT[28] != (RV_PLIC_PERMIT[28] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[29] && reg_we && (RV_PLIC_PERMIT[29] != (RV_PLIC_PERMIT[29] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[30] && reg_we && (RV_PLIC_PERMIT[30] != (RV_PLIC_PERMIT[30] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[31] && reg_we && (RV_PLIC_PERMIT[31] != (RV_PLIC_PERMIT[31] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[32] && reg_we && (RV_PLIC_PERMIT[32] != (RV_PLIC_PERMIT[32] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[33] && reg_we && (RV_PLIC_PERMIT[33] != (RV_PLIC_PERMIT[33] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[34] && reg_we && (RV_PLIC_PERMIT[34] != (RV_PLIC_PERMIT[34] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[35] && reg_we && (RV_PLIC_PERMIT[35] != (RV_PLIC_PERMIT[35] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[36] && reg_we && (RV_PLIC_PERMIT[36] != (RV_PLIC_PERMIT[36] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[37] && reg_we && (RV_PLIC_PERMIT[37] != (RV_PLIC_PERMIT[37] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[38] && reg_we && (RV_PLIC_PERMIT[38] != (RV_PLIC_PERMIT[38] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[39] && reg_we && (RV_PLIC_PERMIT[39] != (RV_PLIC_PERMIT[39] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[40] && reg_we && (RV_PLIC_PERMIT[40] != (RV_PLIC_PERMIT[40] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[41] && reg_we && (RV_PLIC_PERMIT[41] != (RV_PLIC_PERMIT[41] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[42] && reg_we && (RV_PLIC_PERMIT[42] != (RV_PLIC_PERMIT[42] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[43] && reg_we && (RV_PLIC_PERMIT[43] != (RV_PLIC_PERMIT[43] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[44] && reg_we && (RV_PLIC_PERMIT[44] != (RV_PLIC_PERMIT[44] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[45] && reg_we && (RV_PLIC_PERMIT[45] != (RV_PLIC_PERMIT[45] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[46] && reg_we && (RV_PLIC_PERMIT[46] != (RV_PLIC_PERMIT[46] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[47] && reg_we && (RV_PLIC_PERMIT[47] != (RV_PLIC_PERMIT[47] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[48] && reg_we && (RV_PLIC_PERMIT[48] != (RV_PLIC_PERMIT[48] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[49] && reg_we && (RV_PLIC_PERMIT[49] != (RV_PLIC_PERMIT[49] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[50] && reg_we && (RV_PLIC_PERMIT[50] != (RV_PLIC_PERMIT[50] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[51] && reg_we && (RV_PLIC_PERMIT[51] != (RV_PLIC_PERMIT[51] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[52] && reg_we && (RV_PLIC_PERMIT[52] != (RV_PLIC_PERMIT[52] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[53] && reg_we && (RV_PLIC_PERMIT[53] != (RV_PLIC_PERMIT[53] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[54] && reg_we && (RV_PLIC_PERMIT[54] != (RV_PLIC_PERMIT[54] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[55] && reg_we && (RV_PLIC_PERMIT[55] != (RV_PLIC_PERMIT[55] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[56] && reg_we && (RV_PLIC_PERMIT[56] != (RV_PLIC_PERMIT[56] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[57] && reg_we && (RV_PLIC_PERMIT[57] != (RV_PLIC_PERMIT[57] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[58] && reg_we && (RV_PLIC_PERMIT[58] != (RV_PLIC_PERMIT[58] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[59] && reg_we && (RV_PLIC_PERMIT[59] != (RV_PLIC_PERMIT[59] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[60] && reg_we && (RV_PLIC_PERMIT[60] != (RV_PLIC_PERMIT[60] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[61] && reg_we && (RV_PLIC_PERMIT[61] != (RV_PLIC_PERMIT[61] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[62] && reg_we && (RV_PLIC_PERMIT[62] != (RV_PLIC_PERMIT[62] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[63] && reg_we && (RV_PLIC_PERMIT[63] != (RV_PLIC_PERMIT[63] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[64] && reg_we && (RV_PLIC_PERMIT[64] != (RV_PLIC_PERMIT[64] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[65] && reg_we && (RV_PLIC_PERMIT[65] != (RV_PLIC_PERMIT[65] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[66] && reg_we && (RV_PLIC_PERMIT[66] != (RV_PLIC_PERMIT[66] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[67] && reg_we && (RV_PLIC_PERMIT[67] != (RV_PLIC_PERMIT[67] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[68] && reg_we && (RV_PLIC_PERMIT[68] != (RV_PLIC_PERMIT[68] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[69] && reg_we && (RV_PLIC_PERMIT[69] != (RV_PLIC_PERMIT[69] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[70] && reg_we && (RV_PLIC_PERMIT[70] != (RV_PLIC_PERMIT[70] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[71] && reg_we && (RV_PLIC_PERMIT[71] != (RV_PLIC_PERMIT[71] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[72] && reg_we && (RV_PLIC_PERMIT[72] != (RV_PLIC_PERMIT[72] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[73] && reg_we && (RV_PLIC_PERMIT[73] != (RV_PLIC_PERMIT[73] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[74] && reg_we && (RV_PLIC_PERMIT[74] != (RV_PLIC_PERMIT[74] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[75] && reg_we && (RV_PLIC_PERMIT[75] != (RV_PLIC_PERMIT[75] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[76] && reg_we && (RV_PLIC_PERMIT[76] != (RV_PLIC_PERMIT[76] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[77] && reg_we && (RV_PLIC_PERMIT[77] != (RV_PLIC_PERMIT[77] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[78] && reg_we && (RV_PLIC_PERMIT[78] != (RV_PLIC_PERMIT[78] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[79] && reg_we && (RV_PLIC_PERMIT[79] != (RV_PLIC_PERMIT[79] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[80] && reg_we && (RV_PLIC_PERMIT[80] != (RV_PLIC_PERMIT[80] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[81] && reg_we && (RV_PLIC_PERMIT[81] != (RV_PLIC_PERMIT[81] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[82] && reg_we && (RV_PLIC_PERMIT[82] != (RV_PLIC_PERMIT[82] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[83] && reg_we && (RV_PLIC_PERMIT[83] != (RV_PLIC_PERMIT[83] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[84] && reg_we && (RV_PLIC_PERMIT[84] != (RV_PLIC_PERMIT[84] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[85] && reg_we && (RV_PLIC_PERMIT[85] != (RV_PLIC_PERMIT[85] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[86] && reg_we && (RV_PLIC_PERMIT[86] != (RV_PLIC_PERMIT[86] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[87] && reg_we && (RV_PLIC_PERMIT[87] != (RV_PLIC_PERMIT[87] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[88] && reg_we && (RV_PLIC_PERMIT[88] != (RV_PLIC_PERMIT[88] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[89] && reg_we && (RV_PLIC_PERMIT[89] != (RV_PLIC_PERMIT[89] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[90] && reg_we && (RV_PLIC_PERMIT[90] != (RV_PLIC_PERMIT[90] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[91] && reg_we && (RV_PLIC_PERMIT[91] != (RV_PLIC_PERMIT[91] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[92] && reg_we && (RV_PLIC_PERMIT[92] != (RV_PLIC_PERMIT[92] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[93] && reg_we && (RV_PLIC_PERMIT[93] != (RV_PLIC_PERMIT[93] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[94] && reg_we && (RV_PLIC_PERMIT[94] != (RV_PLIC_PERMIT[94] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[95] && reg_we && (RV_PLIC_PERMIT[95] != (RV_PLIC_PERMIT[95] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[96] && reg_we && (RV_PLIC_PERMIT[96] != (RV_PLIC_PERMIT[96] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[97] && reg_we && (RV_PLIC_PERMIT[97] != (RV_PLIC_PERMIT[97] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 0] && reg_we && (RV_PLIC_PERMIT[ 0] != (RV_PLIC_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 1] && reg_we && (RV_PLIC_PERMIT[ 1] != (RV_PLIC_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 2] && reg_we && (RV_PLIC_PERMIT[ 2] != (RV_PLIC_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 3] && reg_we && (RV_PLIC_PERMIT[ 3] != (RV_PLIC_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 4] && reg_we && (RV_PLIC_PERMIT[ 4] != (RV_PLIC_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 5] && reg_we && (RV_PLIC_PERMIT[ 5] != (RV_PLIC_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 6] && reg_we && (RV_PLIC_PERMIT[ 6] != (RV_PLIC_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 7] && reg_we && (RV_PLIC_PERMIT[ 7] != (RV_PLIC_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 8] && reg_we && (RV_PLIC_PERMIT[ 8] != (RV_PLIC_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 9] && reg_we && (RV_PLIC_PERMIT[ 9] != (RV_PLIC_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 10] && reg_we && (RV_PLIC_PERMIT[ 10] != (RV_PLIC_PERMIT[ 10] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 11] && reg_we && (RV_PLIC_PERMIT[ 11] != (RV_PLIC_PERMIT[ 11] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 12] && reg_we && (RV_PLIC_PERMIT[ 12] != (RV_PLIC_PERMIT[ 12] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 13] && reg_we && (RV_PLIC_PERMIT[ 13] != (RV_PLIC_PERMIT[ 13] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 14] && reg_we && (RV_PLIC_PERMIT[ 14] != (RV_PLIC_PERMIT[ 14] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 15] && reg_we && (RV_PLIC_PERMIT[ 15] != (RV_PLIC_PERMIT[ 15] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 16] && reg_we && (RV_PLIC_PERMIT[ 16] != (RV_PLIC_PERMIT[ 16] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 17] && reg_we && (RV_PLIC_PERMIT[ 17] != (RV_PLIC_PERMIT[ 17] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 18] && reg_we && (RV_PLIC_PERMIT[ 18] != (RV_PLIC_PERMIT[ 18] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 19] && reg_we && (RV_PLIC_PERMIT[ 19] != (RV_PLIC_PERMIT[ 19] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 20] && reg_we && (RV_PLIC_PERMIT[ 20] != (RV_PLIC_PERMIT[ 20] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 21] && reg_we && (RV_PLIC_PERMIT[ 21] != (RV_PLIC_PERMIT[ 21] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 22] && reg_we && (RV_PLIC_PERMIT[ 22] != (RV_PLIC_PERMIT[ 22] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 23] && reg_we && (RV_PLIC_PERMIT[ 23] != (RV_PLIC_PERMIT[ 23] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 24] && reg_we && (RV_PLIC_PERMIT[ 24] != (RV_PLIC_PERMIT[ 24] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 25] && reg_we && (RV_PLIC_PERMIT[ 25] != (RV_PLIC_PERMIT[ 25] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 26] && reg_we && (RV_PLIC_PERMIT[ 26] != (RV_PLIC_PERMIT[ 26] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 27] && reg_we && (RV_PLIC_PERMIT[ 27] != (RV_PLIC_PERMIT[ 27] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 28] && reg_we && (RV_PLIC_PERMIT[ 28] != (RV_PLIC_PERMIT[ 28] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 29] && reg_we && (RV_PLIC_PERMIT[ 29] != (RV_PLIC_PERMIT[ 29] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 30] && reg_we && (RV_PLIC_PERMIT[ 30] != (RV_PLIC_PERMIT[ 30] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 31] && reg_we && (RV_PLIC_PERMIT[ 31] != (RV_PLIC_PERMIT[ 31] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 32] && reg_we && (RV_PLIC_PERMIT[ 32] != (RV_PLIC_PERMIT[ 32] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 33] && reg_we && (RV_PLIC_PERMIT[ 33] != (RV_PLIC_PERMIT[ 33] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 34] && reg_we && (RV_PLIC_PERMIT[ 34] != (RV_PLIC_PERMIT[ 34] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 35] && reg_we && (RV_PLIC_PERMIT[ 35] != (RV_PLIC_PERMIT[ 35] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 36] && reg_we && (RV_PLIC_PERMIT[ 36] != (RV_PLIC_PERMIT[ 36] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 37] && reg_we && (RV_PLIC_PERMIT[ 37] != (RV_PLIC_PERMIT[ 37] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 38] && reg_we && (RV_PLIC_PERMIT[ 38] != (RV_PLIC_PERMIT[ 38] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 39] && reg_we && (RV_PLIC_PERMIT[ 39] != (RV_PLIC_PERMIT[ 39] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 40] && reg_we && (RV_PLIC_PERMIT[ 40] != (RV_PLIC_PERMIT[ 40] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 41] && reg_we && (RV_PLIC_PERMIT[ 41] != (RV_PLIC_PERMIT[ 41] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 42] && reg_we && (RV_PLIC_PERMIT[ 42] != (RV_PLIC_PERMIT[ 42] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 43] && reg_we && (RV_PLIC_PERMIT[ 43] != (RV_PLIC_PERMIT[ 43] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 44] && reg_we && (RV_PLIC_PERMIT[ 44] != (RV_PLIC_PERMIT[ 44] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 45] && reg_we && (RV_PLIC_PERMIT[ 45] != (RV_PLIC_PERMIT[ 45] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 46] && reg_we && (RV_PLIC_PERMIT[ 46] != (RV_PLIC_PERMIT[ 46] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 47] && reg_we && (RV_PLIC_PERMIT[ 47] != (RV_PLIC_PERMIT[ 47] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 48] && reg_we && (RV_PLIC_PERMIT[ 48] != (RV_PLIC_PERMIT[ 48] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 49] && reg_we && (RV_PLIC_PERMIT[ 49] != (RV_PLIC_PERMIT[ 49] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 50] && reg_we && (RV_PLIC_PERMIT[ 50] != (RV_PLIC_PERMIT[ 50] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 51] && reg_we && (RV_PLIC_PERMIT[ 51] != (RV_PLIC_PERMIT[ 51] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 52] && reg_we && (RV_PLIC_PERMIT[ 52] != (RV_PLIC_PERMIT[ 52] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 53] && reg_we && (RV_PLIC_PERMIT[ 53] != (RV_PLIC_PERMIT[ 53] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 54] && reg_we && (RV_PLIC_PERMIT[ 54] != (RV_PLIC_PERMIT[ 54] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 55] && reg_we && (RV_PLIC_PERMIT[ 55] != (RV_PLIC_PERMIT[ 55] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 56] && reg_we && (RV_PLIC_PERMIT[ 56] != (RV_PLIC_PERMIT[ 56] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 57] && reg_we && (RV_PLIC_PERMIT[ 57] != (RV_PLIC_PERMIT[ 57] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 58] && reg_we && (RV_PLIC_PERMIT[ 58] != (RV_PLIC_PERMIT[ 58] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 59] && reg_we && (RV_PLIC_PERMIT[ 59] != (RV_PLIC_PERMIT[ 59] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 60] && reg_we && (RV_PLIC_PERMIT[ 60] != (RV_PLIC_PERMIT[ 60] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 61] && reg_we && (RV_PLIC_PERMIT[ 61] != (RV_PLIC_PERMIT[ 61] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 62] && reg_we && (RV_PLIC_PERMIT[ 62] != (RV_PLIC_PERMIT[ 62] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 63] && reg_we && (RV_PLIC_PERMIT[ 63] != (RV_PLIC_PERMIT[ 63] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 64] && reg_we && (RV_PLIC_PERMIT[ 64] != (RV_PLIC_PERMIT[ 64] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 65] && reg_we && (RV_PLIC_PERMIT[ 65] != (RV_PLIC_PERMIT[ 65] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 66] && reg_we && (RV_PLIC_PERMIT[ 66] != (RV_PLIC_PERMIT[ 66] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 67] && reg_we && (RV_PLIC_PERMIT[ 67] != (RV_PLIC_PERMIT[ 67] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 68] && reg_we && (RV_PLIC_PERMIT[ 68] != (RV_PLIC_PERMIT[ 68] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 69] && reg_we && (RV_PLIC_PERMIT[ 69] != (RV_PLIC_PERMIT[ 69] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 70] && reg_we && (RV_PLIC_PERMIT[ 70] != (RV_PLIC_PERMIT[ 70] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 71] && reg_we && (RV_PLIC_PERMIT[ 71] != (RV_PLIC_PERMIT[ 71] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 72] && reg_we && (RV_PLIC_PERMIT[ 72] != (RV_PLIC_PERMIT[ 72] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 73] && reg_we && (RV_PLIC_PERMIT[ 73] != (RV_PLIC_PERMIT[ 73] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 74] && reg_we && (RV_PLIC_PERMIT[ 74] != (RV_PLIC_PERMIT[ 74] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 75] && reg_we && (RV_PLIC_PERMIT[ 75] != (RV_PLIC_PERMIT[ 75] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 76] && reg_we && (RV_PLIC_PERMIT[ 76] != (RV_PLIC_PERMIT[ 76] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 77] && reg_we && (RV_PLIC_PERMIT[ 77] != (RV_PLIC_PERMIT[ 77] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 78] && reg_we && (RV_PLIC_PERMIT[ 78] != (RV_PLIC_PERMIT[ 78] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 79] && reg_we && (RV_PLIC_PERMIT[ 79] != (RV_PLIC_PERMIT[ 79] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 80] && reg_we && (RV_PLIC_PERMIT[ 80] != (RV_PLIC_PERMIT[ 80] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 81] && reg_we && (RV_PLIC_PERMIT[ 81] != (RV_PLIC_PERMIT[ 81] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 82] && reg_we && (RV_PLIC_PERMIT[ 82] != (RV_PLIC_PERMIT[ 82] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 83] && reg_we && (RV_PLIC_PERMIT[ 83] != (RV_PLIC_PERMIT[ 83] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 84] && reg_we && (RV_PLIC_PERMIT[ 84] != (RV_PLIC_PERMIT[ 84] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 85] && reg_we && (RV_PLIC_PERMIT[ 85] != (RV_PLIC_PERMIT[ 85] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 86] && reg_we && (RV_PLIC_PERMIT[ 86] != (RV_PLIC_PERMIT[ 86] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 87] && reg_we && (RV_PLIC_PERMIT[ 87] != (RV_PLIC_PERMIT[ 87] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 88] && reg_we && (RV_PLIC_PERMIT[ 88] != (RV_PLIC_PERMIT[ 88] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 89] && reg_we && (RV_PLIC_PERMIT[ 89] != (RV_PLIC_PERMIT[ 89] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 90] && reg_we && (RV_PLIC_PERMIT[ 90] != (RV_PLIC_PERMIT[ 90] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 91] && reg_we && (RV_PLIC_PERMIT[ 91] != (RV_PLIC_PERMIT[ 91] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 92] && reg_we && (RV_PLIC_PERMIT[ 92] != (RV_PLIC_PERMIT[ 92] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 93] && reg_we && (RV_PLIC_PERMIT[ 93] != (RV_PLIC_PERMIT[ 93] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 94] && reg_we && (RV_PLIC_PERMIT[ 94] != (RV_PLIC_PERMIT[ 94] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 95] && reg_we && (RV_PLIC_PERMIT[ 95] != (RV_PLIC_PERMIT[ 95] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 96] && reg_we && (RV_PLIC_PERMIT[ 96] != (RV_PLIC_PERMIT[ 96] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 97] && reg_we && (RV_PLIC_PERMIT[ 97] != (RV_PLIC_PERMIT[ 97] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 98] && reg_we && (RV_PLIC_PERMIT[ 98] != (RV_PLIC_PERMIT[ 98] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 99] && reg_we && (RV_PLIC_PERMIT[ 99] != (RV_PLIC_PERMIT[ 99] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[100] && reg_we && (RV_PLIC_PERMIT[100] != (RV_PLIC_PERMIT[100] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[101] && reg_we && (RV_PLIC_PERMIT[101] != (RV_PLIC_PERMIT[101] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[102] && reg_we && (RV_PLIC_PERMIT[102] != (RV_PLIC_PERMIT[102] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[103] && reg_we && (RV_PLIC_PERMIT[103] != (RV_PLIC_PERMIT[103] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[104] && reg_we && (RV_PLIC_PERMIT[104] != (RV_PLIC_PERMIT[104] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[105] && reg_we && (RV_PLIC_PERMIT[105] != (RV_PLIC_PERMIT[105] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[106] && reg_we && (RV_PLIC_PERMIT[106] != (RV_PLIC_PERMIT[106] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[107] && reg_we && (RV_PLIC_PERMIT[107] != (RV_PLIC_PERMIT[107] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[108] && reg_we && (RV_PLIC_PERMIT[108] != (RV_PLIC_PERMIT[108] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[109] && reg_we && (RV_PLIC_PERMIT[109] != (RV_PLIC_PERMIT[109] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[110] && reg_we && (RV_PLIC_PERMIT[110] != (RV_PLIC_PERMIT[110] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[111] && reg_we && (RV_PLIC_PERMIT[111] != (RV_PLIC_PERMIT[111] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[112] && reg_we && (RV_PLIC_PERMIT[112] != (RV_PLIC_PERMIT[112] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[113] && reg_we && (RV_PLIC_PERMIT[113] != (RV_PLIC_PERMIT[113] & reg_be))) wr_err = 1'b1 ;
end
@@ -10286,788 +11809,918 @@
- assign le_0_le_0_we = addr_hit[3] & reg_we & ~wr_err;
+
+
+
+
+
+
+
+
+
+
+
+
+
+ assign le_0_le_0_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_0_wd = reg_wdata[0];
- assign le_0_le_1_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_1_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_1_wd = reg_wdata[1];
- assign le_0_le_2_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_2_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_2_wd = reg_wdata[2];
- assign le_0_le_3_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_3_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_3_wd = reg_wdata[3];
- assign le_0_le_4_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_4_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_4_wd = reg_wdata[4];
- assign le_0_le_5_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_5_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_5_wd = reg_wdata[5];
- assign le_0_le_6_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_6_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_6_wd = reg_wdata[6];
- assign le_0_le_7_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_7_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_7_wd = reg_wdata[7];
- assign le_0_le_8_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_8_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_8_wd = reg_wdata[8];
- assign le_0_le_9_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_9_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_9_wd = reg_wdata[9];
- assign le_0_le_10_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_10_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_10_wd = reg_wdata[10];
- assign le_0_le_11_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_11_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_11_wd = reg_wdata[11];
- assign le_0_le_12_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_12_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_12_wd = reg_wdata[12];
- assign le_0_le_13_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_13_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_13_wd = reg_wdata[13];
- assign le_0_le_14_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_14_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_14_wd = reg_wdata[14];
- assign le_0_le_15_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_15_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_15_wd = reg_wdata[15];
- assign le_0_le_16_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_16_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_16_wd = reg_wdata[16];
- assign le_0_le_17_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_17_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_17_wd = reg_wdata[17];
- assign le_0_le_18_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_18_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_18_wd = reg_wdata[18];
- assign le_0_le_19_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_19_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_19_wd = reg_wdata[19];
- assign le_0_le_20_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_20_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_20_wd = reg_wdata[20];
- assign le_0_le_21_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_21_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_21_wd = reg_wdata[21];
- assign le_0_le_22_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_22_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_22_wd = reg_wdata[22];
- assign le_0_le_23_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_23_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_23_wd = reg_wdata[23];
- assign le_0_le_24_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_24_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_24_wd = reg_wdata[24];
- assign le_0_le_25_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_25_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_25_wd = reg_wdata[25];
- assign le_0_le_26_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_26_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_26_wd = reg_wdata[26];
- assign le_0_le_27_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_27_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_27_wd = reg_wdata[27];
- assign le_0_le_28_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_28_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_28_wd = reg_wdata[28];
- assign le_0_le_29_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_29_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_29_wd = reg_wdata[29];
- assign le_0_le_30_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_30_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_30_wd = reg_wdata[30];
- assign le_0_le_31_we = addr_hit[3] & reg_we & ~wr_err;
+ assign le_0_le_31_we = addr_hit[4] & reg_we & ~wr_err;
assign le_0_le_31_wd = reg_wdata[31];
- assign le_1_le_32_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_32_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_32_wd = reg_wdata[0];
- assign le_1_le_33_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_33_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_33_wd = reg_wdata[1];
- assign le_1_le_34_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_34_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_34_wd = reg_wdata[2];
- assign le_1_le_35_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_35_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_35_wd = reg_wdata[3];
- assign le_1_le_36_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_36_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_36_wd = reg_wdata[4];
- assign le_1_le_37_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_37_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_37_wd = reg_wdata[5];
- assign le_1_le_38_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_38_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_38_wd = reg_wdata[6];
- assign le_1_le_39_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_39_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_39_wd = reg_wdata[7];
- assign le_1_le_40_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_40_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_40_wd = reg_wdata[8];
- assign le_1_le_41_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_41_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_41_wd = reg_wdata[9];
- assign le_1_le_42_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_42_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_42_wd = reg_wdata[10];
- assign le_1_le_43_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_43_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_43_wd = reg_wdata[11];
- assign le_1_le_44_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_44_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_44_wd = reg_wdata[12];
- assign le_1_le_45_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_45_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_45_wd = reg_wdata[13];
- assign le_1_le_46_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_46_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_46_wd = reg_wdata[14];
- assign le_1_le_47_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_47_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_47_wd = reg_wdata[15];
- assign le_1_le_48_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_48_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_48_wd = reg_wdata[16];
- assign le_1_le_49_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_49_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_49_wd = reg_wdata[17];
- assign le_1_le_50_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_50_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_50_wd = reg_wdata[18];
- assign le_1_le_51_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_51_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_51_wd = reg_wdata[19];
- assign le_1_le_52_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_52_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_52_wd = reg_wdata[20];
- assign le_1_le_53_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_53_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_53_wd = reg_wdata[21];
- assign le_1_le_54_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_54_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_54_wd = reg_wdata[22];
- assign le_1_le_55_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_55_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_55_wd = reg_wdata[23];
- assign le_1_le_56_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_56_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_56_wd = reg_wdata[24];
- assign le_1_le_57_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_57_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_57_wd = reg_wdata[25];
- assign le_1_le_58_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_58_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_58_wd = reg_wdata[26];
- assign le_1_le_59_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_59_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_59_wd = reg_wdata[27];
- assign le_1_le_60_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_60_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_60_wd = reg_wdata[28];
- assign le_1_le_61_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_61_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_61_wd = reg_wdata[29];
- assign le_1_le_62_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_62_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_62_wd = reg_wdata[30];
- assign le_1_le_63_we = addr_hit[4] & reg_we & ~wr_err;
+ assign le_1_le_63_we = addr_hit[5] & reg_we & ~wr_err;
assign le_1_le_63_wd = reg_wdata[31];
- assign le_2_le_64_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_64_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_64_wd = reg_wdata[0];
- assign le_2_le_65_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_65_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_65_wd = reg_wdata[1];
- assign le_2_le_66_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_66_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_66_wd = reg_wdata[2];
- assign le_2_le_67_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_67_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_67_wd = reg_wdata[3];
- assign le_2_le_68_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_68_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_68_wd = reg_wdata[4];
- assign le_2_le_69_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_69_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_69_wd = reg_wdata[5];
- assign le_2_le_70_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_70_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_70_wd = reg_wdata[6];
- assign le_2_le_71_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_71_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_71_wd = reg_wdata[7];
- assign le_2_le_72_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_72_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_72_wd = reg_wdata[8];
- assign le_2_le_73_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_73_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_73_wd = reg_wdata[9];
- assign le_2_le_74_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_74_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_74_wd = reg_wdata[10];
- assign le_2_le_75_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_75_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_75_wd = reg_wdata[11];
- assign le_2_le_76_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_76_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_76_wd = reg_wdata[12];
- assign le_2_le_77_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_77_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_77_wd = reg_wdata[13];
- assign le_2_le_78_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_78_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_78_wd = reg_wdata[14];
- assign le_2_le_79_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_79_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_79_wd = reg_wdata[15];
- assign le_2_le_80_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_80_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_80_wd = reg_wdata[16];
- assign le_2_le_81_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_81_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_81_wd = reg_wdata[17];
- assign le_2_le_82_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_82_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_82_wd = reg_wdata[18];
- assign le_2_le_83_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_83_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_83_wd = reg_wdata[19];
- assign le_2_le_84_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_84_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_84_wd = reg_wdata[20];
- assign le_2_le_85_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_85_we = addr_hit[6] & reg_we & ~wr_err;
assign le_2_le_85_wd = reg_wdata[21];
- assign prio0_we = addr_hit[6] & reg_we & ~wr_err;
+ assign le_2_le_86_we = addr_hit[6] & reg_we & ~wr_err;
+ assign le_2_le_86_wd = reg_wdata[22];
+
+ assign le_2_le_87_we = addr_hit[6] & reg_we & ~wr_err;
+ assign le_2_le_87_wd = reg_wdata[23];
+
+ assign le_2_le_88_we = addr_hit[6] & reg_we & ~wr_err;
+ assign le_2_le_88_wd = reg_wdata[24];
+
+ assign le_2_le_89_we = addr_hit[6] & reg_we & ~wr_err;
+ assign le_2_le_89_wd = reg_wdata[25];
+
+ assign le_2_le_90_we = addr_hit[6] & reg_we & ~wr_err;
+ assign le_2_le_90_wd = reg_wdata[26];
+
+ assign le_2_le_91_we = addr_hit[6] & reg_we & ~wr_err;
+ assign le_2_le_91_wd = reg_wdata[27];
+
+ assign le_2_le_92_we = addr_hit[6] & reg_we & ~wr_err;
+ assign le_2_le_92_wd = reg_wdata[28];
+
+ assign le_2_le_93_we = addr_hit[6] & reg_we & ~wr_err;
+ assign le_2_le_93_wd = reg_wdata[29];
+
+ assign le_2_le_94_we = addr_hit[6] & reg_we & ~wr_err;
+ assign le_2_le_94_wd = reg_wdata[30];
+
+ assign le_2_le_95_we = addr_hit[6] & reg_we & ~wr_err;
+ assign le_2_le_95_wd = reg_wdata[31];
+
+ assign le_3_le_96_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_96_wd = reg_wdata[0];
+
+ assign le_3_le_97_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_97_wd = reg_wdata[1];
+
+ assign le_3_le_98_we = addr_hit[7] & reg_we & ~wr_err;
+ assign le_3_le_98_wd = reg_wdata[2];
+
+ assign prio0_we = addr_hit[8] & reg_we & ~wr_err;
assign prio0_wd = reg_wdata[1:0];
- assign prio1_we = addr_hit[7] & reg_we & ~wr_err;
+ assign prio1_we = addr_hit[9] & reg_we & ~wr_err;
assign prio1_wd = reg_wdata[1:0];
- assign prio2_we = addr_hit[8] & reg_we & ~wr_err;
+ assign prio2_we = addr_hit[10] & reg_we & ~wr_err;
assign prio2_wd = reg_wdata[1:0];
- assign prio3_we = addr_hit[9] & reg_we & ~wr_err;
+ assign prio3_we = addr_hit[11] & reg_we & ~wr_err;
assign prio3_wd = reg_wdata[1:0];
- assign prio4_we = addr_hit[10] & reg_we & ~wr_err;
+ assign prio4_we = addr_hit[12] & reg_we & ~wr_err;
assign prio4_wd = reg_wdata[1:0];
- assign prio5_we = addr_hit[11] & reg_we & ~wr_err;
+ assign prio5_we = addr_hit[13] & reg_we & ~wr_err;
assign prio5_wd = reg_wdata[1:0];
- assign prio6_we = addr_hit[12] & reg_we & ~wr_err;
+ assign prio6_we = addr_hit[14] & reg_we & ~wr_err;
assign prio6_wd = reg_wdata[1:0];
- assign prio7_we = addr_hit[13] & reg_we & ~wr_err;
+ assign prio7_we = addr_hit[15] & reg_we & ~wr_err;
assign prio7_wd = reg_wdata[1:0];
- assign prio8_we = addr_hit[14] & reg_we & ~wr_err;
+ assign prio8_we = addr_hit[16] & reg_we & ~wr_err;
assign prio8_wd = reg_wdata[1:0];
- assign prio9_we = addr_hit[15] & reg_we & ~wr_err;
+ assign prio9_we = addr_hit[17] & reg_we & ~wr_err;
assign prio9_wd = reg_wdata[1:0];
- assign prio10_we = addr_hit[16] & reg_we & ~wr_err;
+ assign prio10_we = addr_hit[18] & reg_we & ~wr_err;
assign prio10_wd = reg_wdata[1:0];
- assign prio11_we = addr_hit[17] & reg_we & ~wr_err;
+ assign prio11_we = addr_hit[19] & reg_we & ~wr_err;
assign prio11_wd = reg_wdata[1:0];
- assign prio12_we = addr_hit[18] & reg_we & ~wr_err;
+ assign prio12_we = addr_hit[20] & reg_we & ~wr_err;
assign prio12_wd = reg_wdata[1:0];
- assign prio13_we = addr_hit[19] & reg_we & ~wr_err;
+ assign prio13_we = addr_hit[21] & reg_we & ~wr_err;
assign prio13_wd = reg_wdata[1:0];
- assign prio14_we = addr_hit[20] & reg_we & ~wr_err;
+ assign prio14_we = addr_hit[22] & reg_we & ~wr_err;
assign prio14_wd = reg_wdata[1:0];
- assign prio15_we = addr_hit[21] & reg_we & ~wr_err;
+ assign prio15_we = addr_hit[23] & reg_we & ~wr_err;
assign prio15_wd = reg_wdata[1:0];
- assign prio16_we = addr_hit[22] & reg_we & ~wr_err;
+ assign prio16_we = addr_hit[24] & reg_we & ~wr_err;
assign prio16_wd = reg_wdata[1:0];
- assign prio17_we = addr_hit[23] & reg_we & ~wr_err;
+ assign prio17_we = addr_hit[25] & reg_we & ~wr_err;
assign prio17_wd = reg_wdata[1:0];
- assign prio18_we = addr_hit[24] & reg_we & ~wr_err;
+ assign prio18_we = addr_hit[26] & reg_we & ~wr_err;
assign prio18_wd = reg_wdata[1:0];
- assign prio19_we = addr_hit[25] & reg_we & ~wr_err;
+ assign prio19_we = addr_hit[27] & reg_we & ~wr_err;
assign prio19_wd = reg_wdata[1:0];
- assign prio20_we = addr_hit[26] & reg_we & ~wr_err;
+ assign prio20_we = addr_hit[28] & reg_we & ~wr_err;
assign prio20_wd = reg_wdata[1:0];
- assign prio21_we = addr_hit[27] & reg_we & ~wr_err;
+ assign prio21_we = addr_hit[29] & reg_we & ~wr_err;
assign prio21_wd = reg_wdata[1:0];
- assign prio22_we = addr_hit[28] & reg_we & ~wr_err;
+ assign prio22_we = addr_hit[30] & reg_we & ~wr_err;
assign prio22_wd = reg_wdata[1:0];
- assign prio23_we = addr_hit[29] & reg_we & ~wr_err;
+ assign prio23_we = addr_hit[31] & reg_we & ~wr_err;
assign prio23_wd = reg_wdata[1:0];
- assign prio24_we = addr_hit[30] & reg_we & ~wr_err;
+ assign prio24_we = addr_hit[32] & reg_we & ~wr_err;
assign prio24_wd = reg_wdata[1:0];
- assign prio25_we = addr_hit[31] & reg_we & ~wr_err;
+ assign prio25_we = addr_hit[33] & reg_we & ~wr_err;
assign prio25_wd = reg_wdata[1:0];
- assign prio26_we = addr_hit[32] & reg_we & ~wr_err;
+ assign prio26_we = addr_hit[34] & reg_we & ~wr_err;
assign prio26_wd = reg_wdata[1:0];
- assign prio27_we = addr_hit[33] & reg_we & ~wr_err;
+ assign prio27_we = addr_hit[35] & reg_we & ~wr_err;
assign prio27_wd = reg_wdata[1:0];
- assign prio28_we = addr_hit[34] & reg_we & ~wr_err;
+ assign prio28_we = addr_hit[36] & reg_we & ~wr_err;
assign prio28_wd = reg_wdata[1:0];
- assign prio29_we = addr_hit[35] & reg_we & ~wr_err;
+ assign prio29_we = addr_hit[37] & reg_we & ~wr_err;
assign prio29_wd = reg_wdata[1:0];
- assign prio30_we = addr_hit[36] & reg_we & ~wr_err;
+ assign prio30_we = addr_hit[38] & reg_we & ~wr_err;
assign prio30_wd = reg_wdata[1:0];
- assign prio31_we = addr_hit[37] & reg_we & ~wr_err;
+ assign prio31_we = addr_hit[39] & reg_we & ~wr_err;
assign prio31_wd = reg_wdata[1:0];
- assign prio32_we = addr_hit[38] & reg_we & ~wr_err;
+ assign prio32_we = addr_hit[40] & reg_we & ~wr_err;
assign prio32_wd = reg_wdata[1:0];
- assign prio33_we = addr_hit[39] & reg_we & ~wr_err;
+ assign prio33_we = addr_hit[41] & reg_we & ~wr_err;
assign prio33_wd = reg_wdata[1:0];
- assign prio34_we = addr_hit[40] & reg_we & ~wr_err;
+ assign prio34_we = addr_hit[42] & reg_we & ~wr_err;
assign prio34_wd = reg_wdata[1:0];
- assign prio35_we = addr_hit[41] & reg_we & ~wr_err;
+ assign prio35_we = addr_hit[43] & reg_we & ~wr_err;
assign prio35_wd = reg_wdata[1:0];
- assign prio36_we = addr_hit[42] & reg_we & ~wr_err;
+ assign prio36_we = addr_hit[44] & reg_we & ~wr_err;
assign prio36_wd = reg_wdata[1:0];
- assign prio37_we = addr_hit[43] & reg_we & ~wr_err;
+ assign prio37_we = addr_hit[45] & reg_we & ~wr_err;
assign prio37_wd = reg_wdata[1:0];
- assign prio38_we = addr_hit[44] & reg_we & ~wr_err;
+ assign prio38_we = addr_hit[46] & reg_we & ~wr_err;
assign prio38_wd = reg_wdata[1:0];
- assign prio39_we = addr_hit[45] & reg_we & ~wr_err;
+ assign prio39_we = addr_hit[47] & reg_we & ~wr_err;
assign prio39_wd = reg_wdata[1:0];
- assign prio40_we = addr_hit[46] & reg_we & ~wr_err;
+ assign prio40_we = addr_hit[48] & reg_we & ~wr_err;
assign prio40_wd = reg_wdata[1:0];
- assign prio41_we = addr_hit[47] & reg_we & ~wr_err;
+ assign prio41_we = addr_hit[49] & reg_we & ~wr_err;
assign prio41_wd = reg_wdata[1:0];
- assign prio42_we = addr_hit[48] & reg_we & ~wr_err;
+ assign prio42_we = addr_hit[50] & reg_we & ~wr_err;
assign prio42_wd = reg_wdata[1:0];
- assign prio43_we = addr_hit[49] & reg_we & ~wr_err;
+ assign prio43_we = addr_hit[51] & reg_we & ~wr_err;
assign prio43_wd = reg_wdata[1:0];
- assign prio44_we = addr_hit[50] & reg_we & ~wr_err;
+ assign prio44_we = addr_hit[52] & reg_we & ~wr_err;
assign prio44_wd = reg_wdata[1:0];
- assign prio45_we = addr_hit[51] & reg_we & ~wr_err;
+ assign prio45_we = addr_hit[53] & reg_we & ~wr_err;
assign prio45_wd = reg_wdata[1:0];
- assign prio46_we = addr_hit[52] & reg_we & ~wr_err;
+ assign prio46_we = addr_hit[54] & reg_we & ~wr_err;
assign prio46_wd = reg_wdata[1:0];
- assign prio47_we = addr_hit[53] & reg_we & ~wr_err;
+ assign prio47_we = addr_hit[55] & reg_we & ~wr_err;
assign prio47_wd = reg_wdata[1:0];
- assign prio48_we = addr_hit[54] & reg_we & ~wr_err;
+ assign prio48_we = addr_hit[56] & reg_we & ~wr_err;
assign prio48_wd = reg_wdata[1:0];
- assign prio49_we = addr_hit[55] & reg_we & ~wr_err;
+ assign prio49_we = addr_hit[57] & reg_we & ~wr_err;
assign prio49_wd = reg_wdata[1:0];
- assign prio50_we = addr_hit[56] & reg_we & ~wr_err;
+ assign prio50_we = addr_hit[58] & reg_we & ~wr_err;
assign prio50_wd = reg_wdata[1:0];
- assign prio51_we = addr_hit[57] & reg_we & ~wr_err;
+ assign prio51_we = addr_hit[59] & reg_we & ~wr_err;
assign prio51_wd = reg_wdata[1:0];
- assign prio52_we = addr_hit[58] & reg_we & ~wr_err;
+ assign prio52_we = addr_hit[60] & reg_we & ~wr_err;
assign prio52_wd = reg_wdata[1:0];
- assign prio53_we = addr_hit[59] & reg_we & ~wr_err;
+ assign prio53_we = addr_hit[61] & reg_we & ~wr_err;
assign prio53_wd = reg_wdata[1:0];
- assign prio54_we = addr_hit[60] & reg_we & ~wr_err;
+ assign prio54_we = addr_hit[62] & reg_we & ~wr_err;
assign prio54_wd = reg_wdata[1:0];
- assign prio55_we = addr_hit[61] & reg_we & ~wr_err;
+ assign prio55_we = addr_hit[63] & reg_we & ~wr_err;
assign prio55_wd = reg_wdata[1:0];
- assign prio56_we = addr_hit[62] & reg_we & ~wr_err;
+ assign prio56_we = addr_hit[64] & reg_we & ~wr_err;
assign prio56_wd = reg_wdata[1:0];
- assign prio57_we = addr_hit[63] & reg_we & ~wr_err;
+ assign prio57_we = addr_hit[65] & reg_we & ~wr_err;
assign prio57_wd = reg_wdata[1:0];
- assign prio58_we = addr_hit[64] & reg_we & ~wr_err;
+ assign prio58_we = addr_hit[66] & reg_we & ~wr_err;
assign prio58_wd = reg_wdata[1:0];
- assign prio59_we = addr_hit[65] & reg_we & ~wr_err;
+ assign prio59_we = addr_hit[67] & reg_we & ~wr_err;
assign prio59_wd = reg_wdata[1:0];
- assign prio60_we = addr_hit[66] & reg_we & ~wr_err;
+ assign prio60_we = addr_hit[68] & reg_we & ~wr_err;
assign prio60_wd = reg_wdata[1:0];
- assign prio61_we = addr_hit[67] & reg_we & ~wr_err;
+ assign prio61_we = addr_hit[69] & reg_we & ~wr_err;
assign prio61_wd = reg_wdata[1:0];
- assign prio62_we = addr_hit[68] & reg_we & ~wr_err;
+ assign prio62_we = addr_hit[70] & reg_we & ~wr_err;
assign prio62_wd = reg_wdata[1:0];
- assign prio63_we = addr_hit[69] & reg_we & ~wr_err;
+ assign prio63_we = addr_hit[71] & reg_we & ~wr_err;
assign prio63_wd = reg_wdata[1:0];
- assign prio64_we = addr_hit[70] & reg_we & ~wr_err;
+ assign prio64_we = addr_hit[72] & reg_we & ~wr_err;
assign prio64_wd = reg_wdata[1:0];
- assign prio65_we = addr_hit[71] & reg_we & ~wr_err;
+ assign prio65_we = addr_hit[73] & reg_we & ~wr_err;
assign prio65_wd = reg_wdata[1:0];
- assign prio66_we = addr_hit[72] & reg_we & ~wr_err;
+ assign prio66_we = addr_hit[74] & reg_we & ~wr_err;
assign prio66_wd = reg_wdata[1:0];
- assign prio67_we = addr_hit[73] & reg_we & ~wr_err;
+ assign prio67_we = addr_hit[75] & reg_we & ~wr_err;
assign prio67_wd = reg_wdata[1:0];
- assign prio68_we = addr_hit[74] & reg_we & ~wr_err;
+ assign prio68_we = addr_hit[76] & reg_we & ~wr_err;
assign prio68_wd = reg_wdata[1:0];
- assign prio69_we = addr_hit[75] & reg_we & ~wr_err;
+ assign prio69_we = addr_hit[77] & reg_we & ~wr_err;
assign prio69_wd = reg_wdata[1:0];
- assign prio70_we = addr_hit[76] & reg_we & ~wr_err;
+ assign prio70_we = addr_hit[78] & reg_we & ~wr_err;
assign prio70_wd = reg_wdata[1:0];
- assign prio71_we = addr_hit[77] & reg_we & ~wr_err;
+ assign prio71_we = addr_hit[79] & reg_we & ~wr_err;
assign prio71_wd = reg_wdata[1:0];
- assign prio72_we = addr_hit[78] & reg_we & ~wr_err;
+ assign prio72_we = addr_hit[80] & reg_we & ~wr_err;
assign prio72_wd = reg_wdata[1:0];
- assign prio73_we = addr_hit[79] & reg_we & ~wr_err;
+ assign prio73_we = addr_hit[81] & reg_we & ~wr_err;
assign prio73_wd = reg_wdata[1:0];
- assign prio74_we = addr_hit[80] & reg_we & ~wr_err;
+ assign prio74_we = addr_hit[82] & reg_we & ~wr_err;
assign prio74_wd = reg_wdata[1:0];
- assign prio75_we = addr_hit[81] & reg_we & ~wr_err;
+ assign prio75_we = addr_hit[83] & reg_we & ~wr_err;
assign prio75_wd = reg_wdata[1:0];
- assign prio76_we = addr_hit[82] & reg_we & ~wr_err;
+ assign prio76_we = addr_hit[84] & reg_we & ~wr_err;
assign prio76_wd = reg_wdata[1:0];
- assign prio77_we = addr_hit[83] & reg_we & ~wr_err;
+ assign prio77_we = addr_hit[85] & reg_we & ~wr_err;
assign prio77_wd = reg_wdata[1:0];
- assign prio78_we = addr_hit[84] & reg_we & ~wr_err;
+ assign prio78_we = addr_hit[86] & reg_we & ~wr_err;
assign prio78_wd = reg_wdata[1:0];
- assign prio79_we = addr_hit[85] & reg_we & ~wr_err;
+ assign prio79_we = addr_hit[87] & reg_we & ~wr_err;
assign prio79_wd = reg_wdata[1:0];
- assign prio80_we = addr_hit[86] & reg_we & ~wr_err;
+ assign prio80_we = addr_hit[88] & reg_we & ~wr_err;
assign prio80_wd = reg_wdata[1:0];
- assign prio81_we = addr_hit[87] & reg_we & ~wr_err;
+ assign prio81_we = addr_hit[89] & reg_we & ~wr_err;
assign prio81_wd = reg_wdata[1:0];
- assign prio82_we = addr_hit[88] & reg_we & ~wr_err;
+ assign prio82_we = addr_hit[90] & reg_we & ~wr_err;
assign prio82_wd = reg_wdata[1:0];
- assign prio83_we = addr_hit[89] & reg_we & ~wr_err;
+ assign prio83_we = addr_hit[91] & reg_we & ~wr_err;
assign prio83_wd = reg_wdata[1:0];
- assign prio84_we = addr_hit[90] & reg_we & ~wr_err;
+ assign prio84_we = addr_hit[92] & reg_we & ~wr_err;
assign prio84_wd = reg_wdata[1:0];
- assign prio85_we = addr_hit[91] & reg_we & ~wr_err;
+ assign prio85_we = addr_hit[93] & reg_we & ~wr_err;
assign prio85_wd = reg_wdata[1:0];
- assign ie0_0_e_0_we = addr_hit[92] & reg_we & ~wr_err;
+ assign prio86_we = addr_hit[94] & reg_we & ~wr_err;
+ assign prio86_wd = reg_wdata[1:0];
+
+ assign prio87_we = addr_hit[95] & reg_we & ~wr_err;
+ assign prio87_wd = reg_wdata[1:0];
+
+ assign prio88_we = addr_hit[96] & reg_we & ~wr_err;
+ assign prio88_wd = reg_wdata[1:0];
+
+ assign prio89_we = addr_hit[97] & reg_we & ~wr_err;
+ assign prio89_wd = reg_wdata[1:0];
+
+ assign prio90_we = addr_hit[98] & reg_we & ~wr_err;
+ assign prio90_wd = reg_wdata[1:0];
+
+ assign prio91_we = addr_hit[99] & reg_we & ~wr_err;
+ assign prio91_wd = reg_wdata[1:0];
+
+ assign prio92_we = addr_hit[100] & reg_we & ~wr_err;
+ assign prio92_wd = reg_wdata[1:0];
+
+ assign prio93_we = addr_hit[101] & reg_we & ~wr_err;
+ assign prio93_wd = reg_wdata[1:0];
+
+ assign prio94_we = addr_hit[102] & reg_we & ~wr_err;
+ assign prio94_wd = reg_wdata[1:0];
+
+ assign prio95_we = addr_hit[103] & reg_we & ~wr_err;
+ assign prio95_wd = reg_wdata[1:0];
+
+ assign prio96_we = addr_hit[104] & reg_we & ~wr_err;
+ assign prio96_wd = reg_wdata[1:0];
+
+ assign prio97_we = addr_hit[105] & reg_we & ~wr_err;
+ assign prio97_wd = reg_wdata[1:0];
+
+ assign prio98_we = addr_hit[106] & reg_we & ~wr_err;
+ assign prio98_wd = reg_wdata[1:0];
+
+ assign ie0_0_e_0_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_0_wd = reg_wdata[0];
- assign ie0_0_e_1_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_1_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_1_wd = reg_wdata[1];
- assign ie0_0_e_2_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_2_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_2_wd = reg_wdata[2];
- assign ie0_0_e_3_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_3_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_3_wd = reg_wdata[3];
- assign ie0_0_e_4_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_4_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_4_wd = reg_wdata[4];
- assign ie0_0_e_5_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_5_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_5_wd = reg_wdata[5];
- assign ie0_0_e_6_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_6_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_6_wd = reg_wdata[6];
- assign ie0_0_e_7_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_7_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_7_wd = reg_wdata[7];
- assign ie0_0_e_8_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_8_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_8_wd = reg_wdata[8];
- assign ie0_0_e_9_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_9_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_9_wd = reg_wdata[9];
- assign ie0_0_e_10_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_10_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_10_wd = reg_wdata[10];
- assign ie0_0_e_11_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_11_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_11_wd = reg_wdata[11];
- assign ie0_0_e_12_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_12_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_12_wd = reg_wdata[12];
- assign ie0_0_e_13_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_13_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_13_wd = reg_wdata[13];
- assign ie0_0_e_14_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_14_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_14_wd = reg_wdata[14];
- assign ie0_0_e_15_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_15_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_15_wd = reg_wdata[15];
- assign ie0_0_e_16_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_16_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_16_wd = reg_wdata[16];
- assign ie0_0_e_17_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_17_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_17_wd = reg_wdata[17];
- assign ie0_0_e_18_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_18_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_18_wd = reg_wdata[18];
- assign ie0_0_e_19_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_19_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_19_wd = reg_wdata[19];
- assign ie0_0_e_20_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_20_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_20_wd = reg_wdata[20];
- assign ie0_0_e_21_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_21_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_21_wd = reg_wdata[21];
- assign ie0_0_e_22_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_22_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_22_wd = reg_wdata[22];
- assign ie0_0_e_23_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_23_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_23_wd = reg_wdata[23];
- assign ie0_0_e_24_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_24_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_24_wd = reg_wdata[24];
- assign ie0_0_e_25_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_25_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_25_wd = reg_wdata[25];
- assign ie0_0_e_26_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_26_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_26_wd = reg_wdata[26];
- assign ie0_0_e_27_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_27_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_27_wd = reg_wdata[27];
- assign ie0_0_e_28_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_28_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_28_wd = reg_wdata[28];
- assign ie0_0_e_29_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_29_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_29_wd = reg_wdata[29];
- assign ie0_0_e_30_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_30_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_30_wd = reg_wdata[30];
- assign ie0_0_e_31_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_0_e_31_we = addr_hit[107] & reg_we & ~wr_err;
assign ie0_0_e_31_wd = reg_wdata[31];
- assign ie0_1_e_32_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_32_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_32_wd = reg_wdata[0];
- assign ie0_1_e_33_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_33_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_33_wd = reg_wdata[1];
- assign ie0_1_e_34_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_34_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_34_wd = reg_wdata[2];
- assign ie0_1_e_35_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_35_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_35_wd = reg_wdata[3];
- assign ie0_1_e_36_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_36_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_36_wd = reg_wdata[4];
- assign ie0_1_e_37_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_37_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_37_wd = reg_wdata[5];
- assign ie0_1_e_38_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_38_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_38_wd = reg_wdata[6];
- assign ie0_1_e_39_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_39_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_39_wd = reg_wdata[7];
- assign ie0_1_e_40_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_40_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_40_wd = reg_wdata[8];
- assign ie0_1_e_41_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_41_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_41_wd = reg_wdata[9];
- assign ie0_1_e_42_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_42_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_42_wd = reg_wdata[10];
- assign ie0_1_e_43_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_43_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_43_wd = reg_wdata[11];
- assign ie0_1_e_44_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_44_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_44_wd = reg_wdata[12];
- assign ie0_1_e_45_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_45_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_45_wd = reg_wdata[13];
- assign ie0_1_e_46_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_46_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_46_wd = reg_wdata[14];
- assign ie0_1_e_47_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_47_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_47_wd = reg_wdata[15];
- assign ie0_1_e_48_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_48_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_48_wd = reg_wdata[16];
- assign ie0_1_e_49_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_49_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_49_wd = reg_wdata[17];
- assign ie0_1_e_50_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_50_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_50_wd = reg_wdata[18];
- assign ie0_1_e_51_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_51_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_51_wd = reg_wdata[19];
- assign ie0_1_e_52_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_52_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_52_wd = reg_wdata[20];
- assign ie0_1_e_53_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_53_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_53_wd = reg_wdata[21];
- assign ie0_1_e_54_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_54_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_54_wd = reg_wdata[22];
- assign ie0_1_e_55_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_55_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_55_wd = reg_wdata[23];
- assign ie0_1_e_56_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_56_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_56_wd = reg_wdata[24];
- assign ie0_1_e_57_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_57_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_57_wd = reg_wdata[25];
- assign ie0_1_e_58_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_58_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_58_wd = reg_wdata[26];
- assign ie0_1_e_59_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_59_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_59_wd = reg_wdata[27];
- assign ie0_1_e_60_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_60_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_60_wd = reg_wdata[28];
- assign ie0_1_e_61_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_61_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_61_wd = reg_wdata[29];
- assign ie0_1_e_62_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_62_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_62_wd = reg_wdata[30];
- assign ie0_1_e_63_we = addr_hit[93] & reg_we & ~wr_err;
+ assign ie0_1_e_63_we = addr_hit[108] & reg_we & ~wr_err;
assign ie0_1_e_63_wd = reg_wdata[31];
- assign ie0_2_e_64_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_64_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_64_wd = reg_wdata[0];
- assign ie0_2_e_65_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_65_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_65_wd = reg_wdata[1];
- assign ie0_2_e_66_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_66_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_66_wd = reg_wdata[2];
- assign ie0_2_e_67_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_67_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_67_wd = reg_wdata[3];
- assign ie0_2_e_68_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_68_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_68_wd = reg_wdata[4];
- assign ie0_2_e_69_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_69_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_69_wd = reg_wdata[5];
- assign ie0_2_e_70_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_70_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_70_wd = reg_wdata[6];
- assign ie0_2_e_71_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_71_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_71_wd = reg_wdata[7];
- assign ie0_2_e_72_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_72_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_72_wd = reg_wdata[8];
- assign ie0_2_e_73_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_73_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_73_wd = reg_wdata[9];
- assign ie0_2_e_74_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_74_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_74_wd = reg_wdata[10];
- assign ie0_2_e_75_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_75_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_75_wd = reg_wdata[11];
- assign ie0_2_e_76_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_76_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_76_wd = reg_wdata[12];
- assign ie0_2_e_77_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_77_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_77_wd = reg_wdata[13];
- assign ie0_2_e_78_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_78_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_78_wd = reg_wdata[14];
- assign ie0_2_e_79_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_79_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_79_wd = reg_wdata[15];
- assign ie0_2_e_80_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_80_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_80_wd = reg_wdata[16];
- assign ie0_2_e_81_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_81_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_81_wd = reg_wdata[17];
- assign ie0_2_e_82_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_82_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_82_wd = reg_wdata[18];
- assign ie0_2_e_83_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_83_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_83_wd = reg_wdata[19];
- assign ie0_2_e_84_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_84_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_84_wd = reg_wdata[20];
- assign ie0_2_e_85_we = addr_hit[94] & reg_we & ~wr_err;
+ assign ie0_2_e_85_we = addr_hit[109] & reg_we & ~wr_err;
assign ie0_2_e_85_wd = reg_wdata[21];
- assign threshold0_we = addr_hit[95] & reg_we & ~wr_err;
+ assign ie0_2_e_86_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_86_wd = reg_wdata[22];
+
+ assign ie0_2_e_87_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_87_wd = reg_wdata[23];
+
+ assign ie0_2_e_88_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_88_wd = reg_wdata[24];
+
+ assign ie0_2_e_89_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_89_wd = reg_wdata[25];
+
+ assign ie0_2_e_90_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_90_wd = reg_wdata[26];
+
+ assign ie0_2_e_91_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_91_wd = reg_wdata[27];
+
+ assign ie0_2_e_92_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_92_wd = reg_wdata[28];
+
+ assign ie0_2_e_93_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_93_wd = reg_wdata[29];
+
+ assign ie0_2_e_94_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_94_wd = reg_wdata[30];
+
+ assign ie0_2_e_95_we = addr_hit[109] & reg_we & ~wr_err;
+ assign ie0_2_e_95_wd = reg_wdata[31];
+
+ assign ie0_3_e_96_we = addr_hit[110] & reg_we & ~wr_err;
+ assign ie0_3_e_96_wd = reg_wdata[0];
+
+ assign ie0_3_e_97_we = addr_hit[110] & reg_we & ~wr_err;
+ assign ie0_3_e_97_wd = reg_wdata[1];
+
+ assign ie0_3_e_98_we = addr_hit[110] & reg_we & ~wr_err;
+ assign ie0_3_e_98_wd = reg_wdata[2];
+
+ assign threshold0_we = addr_hit[111] & reg_we & ~wr_err;
assign threshold0_wd = reg_wdata[1:0];
- assign cc0_we = addr_hit[96] & reg_we & ~wr_err;
+ assign cc0_we = addr_hit[112] & reg_we & ~wr_err;
assign cc0_wd = reg_wdata[6:0];
- assign cc0_re = addr_hit[96] && reg_re;
+ assign cc0_re = addr_hit[112] && reg_re;
- assign msip0_we = addr_hit[97] & reg_we & ~wr_err;
+ assign msip0_we = addr_hit[113] & reg_we & ~wr_err;
assign msip0_wd = reg_wdata[0];
// Read data return
@@ -11167,9 +12820,25 @@
reg_rdata_next[19] = ip_2_p_83_qs;
reg_rdata_next[20] = ip_2_p_84_qs;
reg_rdata_next[21] = ip_2_p_85_qs;
+ reg_rdata_next[22] = ip_2_p_86_qs;
+ reg_rdata_next[23] = ip_2_p_87_qs;
+ reg_rdata_next[24] = ip_2_p_88_qs;
+ reg_rdata_next[25] = ip_2_p_89_qs;
+ reg_rdata_next[26] = ip_2_p_90_qs;
+ reg_rdata_next[27] = ip_2_p_91_qs;
+ reg_rdata_next[28] = ip_2_p_92_qs;
+ reg_rdata_next[29] = ip_2_p_93_qs;
+ reg_rdata_next[30] = ip_2_p_94_qs;
+ reg_rdata_next[31] = ip_2_p_95_qs;
end
addr_hit[3]: begin
+ reg_rdata_next[0] = ip_3_p_96_qs;
+ reg_rdata_next[1] = ip_3_p_97_qs;
+ reg_rdata_next[2] = ip_3_p_98_qs;
+ end
+
+ addr_hit[4]: begin
reg_rdata_next[0] = le_0_le_0_qs;
reg_rdata_next[1] = le_0_le_1_qs;
reg_rdata_next[2] = le_0_le_2_qs;
@@ -11204,7 +12873,7 @@
reg_rdata_next[31] = le_0_le_31_qs;
end
- addr_hit[4]: begin
+ addr_hit[5]: begin
reg_rdata_next[0] = le_1_le_32_qs;
reg_rdata_next[1] = le_1_le_33_qs;
reg_rdata_next[2] = le_1_le_34_qs;
@@ -11239,7 +12908,7 @@
reg_rdata_next[31] = le_1_le_63_qs;
end
- addr_hit[5]: begin
+ addr_hit[6]: begin
reg_rdata_next[0] = le_2_le_64_qs;
reg_rdata_next[1] = le_2_le_65_qs;
reg_rdata_next[2] = le_2_le_66_qs;
@@ -11262,353 +12931,421 @@
reg_rdata_next[19] = le_2_le_83_qs;
reg_rdata_next[20] = le_2_le_84_qs;
reg_rdata_next[21] = le_2_le_85_qs;
- end
-
- addr_hit[6]: begin
- reg_rdata_next[1:0] = prio0_qs;
+ reg_rdata_next[22] = le_2_le_86_qs;
+ reg_rdata_next[23] = le_2_le_87_qs;
+ reg_rdata_next[24] = le_2_le_88_qs;
+ reg_rdata_next[25] = le_2_le_89_qs;
+ reg_rdata_next[26] = le_2_le_90_qs;
+ reg_rdata_next[27] = le_2_le_91_qs;
+ reg_rdata_next[28] = le_2_le_92_qs;
+ reg_rdata_next[29] = le_2_le_93_qs;
+ reg_rdata_next[30] = le_2_le_94_qs;
+ reg_rdata_next[31] = le_2_le_95_qs;
end
addr_hit[7]: begin
- reg_rdata_next[1:0] = prio1_qs;
+ reg_rdata_next[0] = le_3_le_96_qs;
+ reg_rdata_next[1] = le_3_le_97_qs;
+ reg_rdata_next[2] = le_3_le_98_qs;
end
addr_hit[8]: begin
- reg_rdata_next[1:0] = prio2_qs;
+ reg_rdata_next[1:0] = prio0_qs;
end
addr_hit[9]: begin
- reg_rdata_next[1:0] = prio3_qs;
+ reg_rdata_next[1:0] = prio1_qs;
end
addr_hit[10]: begin
- reg_rdata_next[1:0] = prio4_qs;
+ reg_rdata_next[1:0] = prio2_qs;
end
addr_hit[11]: begin
- reg_rdata_next[1:0] = prio5_qs;
+ reg_rdata_next[1:0] = prio3_qs;
end
addr_hit[12]: begin
- reg_rdata_next[1:0] = prio6_qs;
+ reg_rdata_next[1:0] = prio4_qs;
end
addr_hit[13]: begin
- reg_rdata_next[1:0] = prio7_qs;
+ reg_rdata_next[1:0] = prio5_qs;
end
addr_hit[14]: begin
- reg_rdata_next[1:0] = prio8_qs;
+ reg_rdata_next[1:0] = prio6_qs;
end
addr_hit[15]: begin
- reg_rdata_next[1:0] = prio9_qs;
+ reg_rdata_next[1:0] = prio7_qs;
end
addr_hit[16]: begin
- reg_rdata_next[1:0] = prio10_qs;
+ reg_rdata_next[1:0] = prio8_qs;
end
addr_hit[17]: begin
- reg_rdata_next[1:0] = prio11_qs;
+ reg_rdata_next[1:0] = prio9_qs;
end
addr_hit[18]: begin
- reg_rdata_next[1:0] = prio12_qs;
+ reg_rdata_next[1:0] = prio10_qs;
end
addr_hit[19]: begin
- reg_rdata_next[1:0] = prio13_qs;
+ reg_rdata_next[1:0] = prio11_qs;
end
addr_hit[20]: begin
- reg_rdata_next[1:0] = prio14_qs;
+ reg_rdata_next[1:0] = prio12_qs;
end
addr_hit[21]: begin
- reg_rdata_next[1:0] = prio15_qs;
+ reg_rdata_next[1:0] = prio13_qs;
end
addr_hit[22]: begin
- reg_rdata_next[1:0] = prio16_qs;
+ reg_rdata_next[1:0] = prio14_qs;
end
addr_hit[23]: begin
- reg_rdata_next[1:0] = prio17_qs;
+ reg_rdata_next[1:0] = prio15_qs;
end
addr_hit[24]: begin
- reg_rdata_next[1:0] = prio18_qs;
+ reg_rdata_next[1:0] = prio16_qs;
end
addr_hit[25]: begin
- reg_rdata_next[1:0] = prio19_qs;
+ reg_rdata_next[1:0] = prio17_qs;
end
addr_hit[26]: begin
- reg_rdata_next[1:0] = prio20_qs;
+ reg_rdata_next[1:0] = prio18_qs;
end
addr_hit[27]: begin
- reg_rdata_next[1:0] = prio21_qs;
+ reg_rdata_next[1:0] = prio19_qs;
end
addr_hit[28]: begin
- reg_rdata_next[1:0] = prio22_qs;
+ reg_rdata_next[1:0] = prio20_qs;
end
addr_hit[29]: begin
- reg_rdata_next[1:0] = prio23_qs;
+ reg_rdata_next[1:0] = prio21_qs;
end
addr_hit[30]: begin
- reg_rdata_next[1:0] = prio24_qs;
+ reg_rdata_next[1:0] = prio22_qs;
end
addr_hit[31]: begin
- reg_rdata_next[1:0] = prio25_qs;
+ reg_rdata_next[1:0] = prio23_qs;
end
addr_hit[32]: begin
- reg_rdata_next[1:0] = prio26_qs;
+ reg_rdata_next[1:0] = prio24_qs;
end
addr_hit[33]: begin
- reg_rdata_next[1:0] = prio27_qs;
+ reg_rdata_next[1:0] = prio25_qs;
end
addr_hit[34]: begin
- reg_rdata_next[1:0] = prio28_qs;
+ reg_rdata_next[1:0] = prio26_qs;
end
addr_hit[35]: begin
- reg_rdata_next[1:0] = prio29_qs;
+ reg_rdata_next[1:0] = prio27_qs;
end
addr_hit[36]: begin
- reg_rdata_next[1:0] = prio30_qs;
+ reg_rdata_next[1:0] = prio28_qs;
end
addr_hit[37]: begin
- reg_rdata_next[1:0] = prio31_qs;
+ reg_rdata_next[1:0] = prio29_qs;
end
addr_hit[38]: begin
- reg_rdata_next[1:0] = prio32_qs;
+ reg_rdata_next[1:0] = prio30_qs;
end
addr_hit[39]: begin
- reg_rdata_next[1:0] = prio33_qs;
+ reg_rdata_next[1:0] = prio31_qs;
end
addr_hit[40]: begin
- reg_rdata_next[1:0] = prio34_qs;
+ reg_rdata_next[1:0] = prio32_qs;
end
addr_hit[41]: begin
- reg_rdata_next[1:0] = prio35_qs;
+ reg_rdata_next[1:0] = prio33_qs;
end
addr_hit[42]: begin
- reg_rdata_next[1:0] = prio36_qs;
+ reg_rdata_next[1:0] = prio34_qs;
end
addr_hit[43]: begin
- reg_rdata_next[1:0] = prio37_qs;
+ reg_rdata_next[1:0] = prio35_qs;
end
addr_hit[44]: begin
- reg_rdata_next[1:0] = prio38_qs;
+ reg_rdata_next[1:0] = prio36_qs;
end
addr_hit[45]: begin
- reg_rdata_next[1:0] = prio39_qs;
+ reg_rdata_next[1:0] = prio37_qs;
end
addr_hit[46]: begin
- reg_rdata_next[1:0] = prio40_qs;
+ reg_rdata_next[1:0] = prio38_qs;
end
addr_hit[47]: begin
- reg_rdata_next[1:0] = prio41_qs;
+ reg_rdata_next[1:0] = prio39_qs;
end
addr_hit[48]: begin
- reg_rdata_next[1:0] = prio42_qs;
+ reg_rdata_next[1:0] = prio40_qs;
end
addr_hit[49]: begin
- reg_rdata_next[1:0] = prio43_qs;
+ reg_rdata_next[1:0] = prio41_qs;
end
addr_hit[50]: begin
- reg_rdata_next[1:0] = prio44_qs;
+ reg_rdata_next[1:0] = prio42_qs;
end
addr_hit[51]: begin
- reg_rdata_next[1:0] = prio45_qs;
+ reg_rdata_next[1:0] = prio43_qs;
end
addr_hit[52]: begin
- reg_rdata_next[1:0] = prio46_qs;
+ reg_rdata_next[1:0] = prio44_qs;
end
addr_hit[53]: begin
- reg_rdata_next[1:0] = prio47_qs;
+ reg_rdata_next[1:0] = prio45_qs;
end
addr_hit[54]: begin
- reg_rdata_next[1:0] = prio48_qs;
+ reg_rdata_next[1:0] = prio46_qs;
end
addr_hit[55]: begin
- reg_rdata_next[1:0] = prio49_qs;
+ reg_rdata_next[1:0] = prio47_qs;
end
addr_hit[56]: begin
- reg_rdata_next[1:0] = prio50_qs;
+ reg_rdata_next[1:0] = prio48_qs;
end
addr_hit[57]: begin
- reg_rdata_next[1:0] = prio51_qs;
+ reg_rdata_next[1:0] = prio49_qs;
end
addr_hit[58]: begin
- reg_rdata_next[1:0] = prio52_qs;
+ reg_rdata_next[1:0] = prio50_qs;
end
addr_hit[59]: begin
- reg_rdata_next[1:0] = prio53_qs;
+ reg_rdata_next[1:0] = prio51_qs;
end
addr_hit[60]: begin
- reg_rdata_next[1:0] = prio54_qs;
+ reg_rdata_next[1:0] = prio52_qs;
end
addr_hit[61]: begin
- reg_rdata_next[1:0] = prio55_qs;
+ reg_rdata_next[1:0] = prio53_qs;
end
addr_hit[62]: begin
- reg_rdata_next[1:0] = prio56_qs;
+ reg_rdata_next[1:0] = prio54_qs;
end
addr_hit[63]: begin
- reg_rdata_next[1:0] = prio57_qs;
+ reg_rdata_next[1:0] = prio55_qs;
end
addr_hit[64]: begin
- reg_rdata_next[1:0] = prio58_qs;
+ reg_rdata_next[1:0] = prio56_qs;
end
addr_hit[65]: begin
- reg_rdata_next[1:0] = prio59_qs;
+ reg_rdata_next[1:0] = prio57_qs;
end
addr_hit[66]: begin
- reg_rdata_next[1:0] = prio60_qs;
+ reg_rdata_next[1:0] = prio58_qs;
end
addr_hit[67]: begin
- reg_rdata_next[1:0] = prio61_qs;
+ reg_rdata_next[1:0] = prio59_qs;
end
addr_hit[68]: begin
- reg_rdata_next[1:0] = prio62_qs;
+ reg_rdata_next[1:0] = prio60_qs;
end
addr_hit[69]: begin
- reg_rdata_next[1:0] = prio63_qs;
+ reg_rdata_next[1:0] = prio61_qs;
end
addr_hit[70]: begin
- reg_rdata_next[1:0] = prio64_qs;
+ reg_rdata_next[1:0] = prio62_qs;
end
addr_hit[71]: begin
- reg_rdata_next[1:0] = prio65_qs;
+ reg_rdata_next[1:0] = prio63_qs;
end
addr_hit[72]: begin
- reg_rdata_next[1:0] = prio66_qs;
+ reg_rdata_next[1:0] = prio64_qs;
end
addr_hit[73]: begin
- reg_rdata_next[1:0] = prio67_qs;
+ reg_rdata_next[1:0] = prio65_qs;
end
addr_hit[74]: begin
- reg_rdata_next[1:0] = prio68_qs;
+ reg_rdata_next[1:0] = prio66_qs;
end
addr_hit[75]: begin
- reg_rdata_next[1:0] = prio69_qs;
+ reg_rdata_next[1:0] = prio67_qs;
end
addr_hit[76]: begin
- reg_rdata_next[1:0] = prio70_qs;
+ reg_rdata_next[1:0] = prio68_qs;
end
addr_hit[77]: begin
- reg_rdata_next[1:0] = prio71_qs;
+ reg_rdata_next[1:0] = prio69_qs;
end
addr_hit[78]: begin
- reg_rdata_next[1:0] = prio72_qs;
+ reg_rdata_next[1:0] = prio70_qs;
end
addr_hit[79]: begin
- reg_rdata_next[1:0] = prio73_qs;
+ reg_rdata_next[1:0] = prio71_qs;
end
addr_hit[80]: begin
- reg_rdata_next[1:0] = prio74_qs;
+ reg_rdata_next[1:0] = prio72_qs;
end
addr_hit[81]: begin
- reg_rdata_next[1:0] = prio75_qs;
+ reg_rdata_next[1:0] = prio73_qs;
end
addr_hit[82]: begin
- reg_rdata_next[1:0] = prio76_qs;
+ reg_rdata_next[1:0] = prio74_qs;
end
addr_hit[83]: begin
- reg_rdata_next[1:0] = prio77_qs;
+ reg_rdata_next[1:0] = prio75_qs;
end
addr_hit[84]: begin
- reg_rdata_next[1:0] = prio78_qs;
+ reg_rdata_next[1:0] = prio76_qs;
end
addr_hit[85]: begin
- reg_rdata_next[1:0] = prio79_qs;
+ reg_rdata_next[1:0] = prio77_qs;
end
addr_hit[86]: begin
- reg_rdata_next[1:0] = prio80_qs;
+ reg_rdata_next[1:0] = prio78_qs;
end
addr_hit[87]: begin
- reg_rdata_next[1:0] = prio81_qs;
+ reg_rdata_next[1:0] = prio79_qs;
end
addr_hit[88]: begin
- reg_rdata_next[1:0] = prio82_qs;
+ reg_rdata_next[1:0] = prio80_qs;
end
addr_hit[89]: begin
- reg_rdata_next[1:0] = prio83_qs;
+ reg_rdata_next[1:0] = prio81_qs;
end
addr_hit[90]: begin
- reg_rdata_next[1:0] = prio84_qs;
+ reg_rdata_next[1:0] = prio82_qs;
end
addr_hit[91]: begin
- reg_rdata_next[1:0] = prio85_qs;
+ reg_rdata_next[1:0] = prio83_qs;
end
addr_hit[92]: begin
+ reg_rdata_next[1:0] = prio84_qs;
+ end
+
+ addr_hit[93]: begin
+ reg_rdata_next[1:0] = prio85_qs;
+ end
+
+ addr_hit[94]: begin
+ reg_rdata_next[1:0] = prio86_qs;
+ end
+
+ addr_hit[95]: begin
+ reg_rdata_next[1:0] = prio87_qs;
+ end
+
+ addr_hit[96]: begin
+ reg_rdata_next[1:0] = prio88_qs;
+ end
+
+ addr_hit[97]: begin
+ reg_rdata_next[1:0] = prio89_qs;
+ end
+
+ addr_hit[98]: begin
+ reg_rdata_next[1:0] = prio90_qs;
+ end
+
+ addr_hit[99]: begin
+ reg_rdata_next[1:0] = prio91_qs;
+ end
+
+ addr_hit[100]: begin
+ reg_rdata_next[1:0] = prio92_qs;
+ end
+
+ addr_hit[101]: begin
+ reg_rdata_next[1:0] = prio93_qs;
+ end
+
+ addr_hit[102]: begin
+ reg_rdata_next[1:0] = prio94_qs;
+ end
+
+ addr_hit[103]: begin
+ reg_rdata_next[1:0] = prio95_qs;
+ end
+
+ addr_hit[104]: begin
+ reg_rdata_next[1:0] = prio96_qs;
+ end
+
+ addr_hit[105]: begin
+ reg_rdata_next[1:0] = prio97_qs;
+ end
+
+ addr_hit[106]: begin
+ reg_rdata_next[1:0] = prio98_qs;
+ end
+
+ addr_hit[107]: begin
reg_rdata_next[0] = ie0_0_e_0_qs;
reg_rdata_next[1] = ie0_0_e_1_qs;
reg_rdata_next[2] = ie0_0_e_2_qs;
@@ -11643,7 +13380,7 @@
reg_rdata_next[31] = ie0_0_e_31_qs;
end
- addr_hit[93]: begin
+ addr_hit[108]: begin
reg_rdata_next[0] = ie0_1_e_32_qs;
reg_rdata_next[1] = ie0_1_e_33_qs;
reg_rdata_next[2] = ie0_1_e_34_qs;
@@ -11678,7 +13415,7 @@
reg_rdata_next[31] = ie0_1_e_63_qs;
end
- addr_hit[94]: begin
+ addr_hit[109]: begin
reg_rdata_next[0] = ie0_2_e_64_qs;
reg_rdata_next[1] = ie0_2_e_65_qs;
reg_rdata_next[2] = ie0_2_e_66_qs;
@@ -11701,17 +13438,33 @@
reg_rdata_next[19] = ie0_2_e_83_qs;
reg_rdata_next[20] = ie0_2_e_84_qs;
reg_rdata_next[21] = ie0_2_e_85_qs;
+ reg_rdata_next[22] = ie0_2_e_86_qs;
+ reg_rdata_next[23] = ie0_2_e_87_qs;
+ reg_rdata_next[24] = ie0_2_e_88_qs;
+ reg_rdata_next[25] = ie0_2_e_89_qs;
+ reg_rdata_next[26] = ie0_2_e_90_qs;
+ reg_rdata_next[27] = ie0_2_e_91_qs;
+ reg_rdata_next[28] = ie0_2_e_92_qs;
+ reg_rdata_next[29] = ie0_2_e_93_qs;
+ reg_rdata_next[30] = ie0_2_e_94_qs;
+ reg_rdata_next[31] = ie0_2_e_95_qs;
end
- addr_hit[95]: begin
+ addr_hit[110]: begin
+ reg_rdata_next[0] = ie0_3_e_96_qs;
+ reg_rdata_next[1] = ie0_3_e_97_qs;
+ reg_rdata_next[2] = ie0_3_e_98_qs;
+ end
+
+ addr_hit[111]: begin
reg_rdata_next[1:0] = threshold0_qs;
end
- addr_hit[96]: begin
+ addr_hit[112]: begin
reg_rdata_next[6:0] = cc0_qs;
end
- addr_hit[97]: begin
+ addr_hit[113]: begin
reg_rdata_next[0] = msip0_qs;
end
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 71ca674..85dfb1a 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -164,7 +164,7 @@
// otbn
- logic [85:0] intr_vector;
+ logic [98:0] intr_vector;
// Interrupt source list
logic intr_uart_tx_watermark;
logic intr_uart_rx_watermark;
@@ -1403,6 +1403,19 @@
// interrupt assignments
assign intr_vector = {
+ intr_entropy_src_es_fifo_err,
+ intr_entropy_src_es_health_test_failed,
+ intr_entropy_src_es_entropy_valid,
+ intr_edn1_edn_fifo_err,
+ intr_edn1_edn_cmd_req_done,
+ intr_edn0_edn_fifo_err,
+ intr_edn0_edn_cmd_req_done,
+ intr_csrng_cs_fifo_err,
+ intr_csrng_cs_hw_inst_exc,
+ intr_csrng_cs_entropy_req,
+ intr_csrng_cs_cmd_req_done,
+ intr_otp_ctrl_otp_error,
+ intr_otp_ctrl_otp_operation_done,
intr_kmac_kmac_err,
intr_kmac_fifo_empty,
intr_kmac_kmac_done,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
index e221e51..1ebb08f 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -11,7 +11,7 @@
* `top_earlgrey_plic_peripheral_t`.
*/
const top_earlgrey_plic_peripheral_t
- top_earlgrey_plic_interrupt_for_peripheral[86] = {
+ top_earlgrey_plic_interrupt_for_peripheral[99] = {
[kTopEarlgreyPlicIrqIdNone] = kTopEarlgreyPlicPeripheralUnknown,
[kTopEarlgreyPlicIrqIdGpioGpio0] = kTopEarlgreyPlicPeripheralGpio,
[kTopEarlgreyPlicIrqIdGpioGpio1] = kTopEarlgreyPlicPeripheralGpio,
@@ -98,6 +98,19 @@
[kTopEarlgreyPlicIrqIdKmacKmacDone] = kTopEarlgreyPlicPeripheralKmac,
[kTopEarlgreyPlicIrqIdKmacFifoEmpty] = kTopEarlgreyPlicPeripheralKmac,
[kTopEarlgreyPlicIrqIdKmacKmacErr] = kTopEarlgreyPlicPeripheralKmac,
+ [kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone] = kTopEarlgreyPlicPeripheralOtpCtrl,
+ [kTopEarlgreyPlicIrqIdOtpCtrlOtpError] = kTopEarlgreyPlicPeripheralOtpCtrl,
+ [kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone] = kTopEarlgreyPlicPeripheralCsrng,
+ [kTopEarlgreyPlicIrqIdCsrngCsEntropyReq] = kTopEarlgreyPlicPeripheralCsrng,
+ [kTopEarlgreyPlicIrqIdCsrngCsHwInstExc] = kTopEarlgreyPlicPeripheralCsrng,
+ [kTopEarlgreyPlicIrqIdCsrngCsFifoErr] = kTopEarlgreyPlicPeripheralCsrng,
+ [kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone] = kTopEarlgreyPlicPeripheralEdn0,
+ [kTopEarlgreyPlicIrqIdEdn0EdnFifoErr] = kTopEarlgreyPlicPeripheralEdn0,
+ [kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone] = kTopEarlgreyPlicPeripheralEdn1,
+ [kTopEarlgreyPlicIrqIdEdn1EdnFifoErr] = kTopEarlgreyPlicPeripheralEdn1,
+ [kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid] = kTopEarlgreyPlicPeripheralEntropySrc,
+ [kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed] = kTopEarlgreyPlicPeripheralEntropySrc,
+ [kTopEarlgreyPlicIrqIdEntropySrcEsFifoErr] = kTopEarlgreyPlicPeripheralEntropySrc,
};
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index 9ad555d..c71dea9 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -555,7 +555,12 @@
kTopEarlgreyPlicPeripheralOtbn = 10, /**< otbn */
kTopEarlgreyPlicPeripheralKeymgr = 11, /**< keymgr */
kTopEarlgreyPlicPeripheralKmac = 12, /**< kmac */
- kTopEarlgreyPlicPeripheralLast = 12, /**< \internal Final PLIC peripheral */
+ kTopEarlgreyPlicPeripheralOtpCtrl = 13, /**< otp_ctrl */
+ kTopEarlgreyPlicPeripheralCsrng = 14, /**< csrng */
+ kTopEarlgreyPlicPeripheralEdn0 = 15, /**< edn0 */
+ kTopEarlgreyPlicPeripheralEdn1 = 16, /**< edn1 */
+ kTopEarlgreyPlicPeripheralEntropySrc = 17, /**< entropy_src */
+ kTopEarlgreyPlicPeripheralLast = 17, /**< \internal Final PLIC peripheral */
} top_earlgrey_plic_peripheral_t;
/**
@@ -651,7 +656,20 @@
kTopEarlgreyPlicIrqIdKmacKmacDone = 83, /**< kmac_kmac_done */
kTopEarlgreyPlicIrqIdKmacFifoEmpty = 84, /**< kmac_fifo_empty */
kTopEarlgreyPlicIrqIdKmacKmacErr = 85, /**< kmac_kmac_err */
- kTopEarlgreyPlicIrqIdLast = 85, /**< \internal The Last Valid Interrupt ID. */
+ kTopEarlgreyPlicIrqIdOtpCtrlOtpOperationDone = 86, /**< otp_ctrl_otp_operation_done */
+ kTopEarlgreyPlicIrqIdOtpCtrlOtpError = 87, /**< otp_ctrl_otp_error */
+ kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone = 88, /**< csrng_cs_cmd_req_done */
+ kTopEarlgreyPlicIrqIdCsrngCsEntropyReq = 89, /**< csrng_cs_entropy_req */
+ kTopEarlgreyPlicIrqIdCsrngCsHwInstExc = 90, /**< csrng_cs_hw_inst_exc */
+ kTopEarlgreyPlicIrqIdCsrngCsFifoErr = 91, /**< csrng_cs_fifo_err */
+ kTopEarlgreyPlicIrqIdEdn0EdnCmdReqDone = 92, /**< edn0_edn_cmd_req_done */
+ kTopEarlgreyPlicIrqIdEdn0EdnFifoErr = 93, /**< edn0_edn_fifo_err */
+ kTopEarlgreyPlicIrqIdEdn1EdnCmdReqDone = 94, /**< edn1_edn_cmd_req_done */
+ kTopEarlgreyPlicIrqIdEdn1EdnFifoErr = 95, /**< edn1_edn_fifo_err */
+ kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 96, /**< entropy_src_es_entropy_valid */
+ kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 97, /**< entropy_src_es_health_test_failed */
+ kTopEarlgreyPlicIrqIdEntropySrcEsFifoErr = 98, /**< entropy_src_es_fifo_err */
+ kTopEarlgreyPlicIrqIdLast = 98, /**< \internal The Last Valid Interrupt ID. */
} top_earlgrey_plic_irq_id_t;
/**
@@ -661,7 +679,7 @@
* `top_earlgrey_plic_peripheral_t`.
*/
extern const top_earlgrey_plic_peripheral_t
- top_earlgrey_plic_interrupt_for_peripheral[86];
+ top_earlgrey_plic_interrupt_for_peripheral[99];
/**
* PLIC Interrupt Target.
