commit | f21a889a74aec84b3615ca983ccdb3f1e99f45da | [log] [tgz] |
---|---|---|
author | Andreas Kurth <adk@lowrisc.org> | Fri Aug 26 11:55:33 2022 +0000 |
committer | Greg Chadwick <mail@gregchadwick.co.uk> | Tue Aug 30 14:00:31 2022 +0100 |
tree | 1d43ead97a0cc914f5c24909063d8b6c84259e4e | |
parent | 751fbf5b7ccd54abe54dd387b4f7c2e220d2e43c [diff] |
[otbn] Fix DMEM/IMEM rdata bus enabled assertions These assertions tried to capture all conditions when a core would not access DMEM or IMEM to assert that DMEM or IMEM would then be accessible via the bus. However, the conditions were not sufficiently specific, and when DMEM or IMEM were not accessible while the conditions held, the assertion would fail. One option would be to make the conditions more specific, but that would approach the definition of the enable signal, which is not the point of an assertion. Instead, an assertion should check if an implementation behaves as specified. OTBN's specification states that DMEM/IMEM can be read via the bus when OTBN is *Idle*. This commit changes those assertions to match the specification, thereby closing #14602. Signed-off-by: Andreas Kurth <adk@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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