| commit | ee060bd6728a7d5cef26b67bba70dcf662c1971c | [log] [tgz] |
|---|---|---|
| author | Greg Chadwick <gac@lowrisc.org> | Sat May 15 17:33:22 2021 +0100 |
| committer | Greg Chadwick <gac@lowrisc.org> | Tue May 18 15:51:20 2021 +0100 |
| tree | c18d7952b555ac3ace8cd83289ced74384cb8629 | |
| parent | faa63d2e0cc274667adde09f9700139521bf5875 [diff] |
[otbn] Add integrity to DMem and IMem Memories were already expanded to included integrity bits. This commit puts them to use. Integrity bits are carried through from memory to and from the register file for reads and writes. Integrity is checked at the memory boundary for all reads. This includes integrity generation in the `otbn` module for all data arriving via the TL interconnect. This is a temporary feature until full end to end integrity has been enabled across the TL interconnect. Fixes #6421 Fixes #6422 Signed-off-by: Greg Chadwick <gac@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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