[dv/keymgr] Enable testing for sw_binding_*
Also fix a corner case in cfgen_vseq: when done is asserted, skiping
writting cfgen gated csr
Signed-off-by: Weicai Yang <weicai@google.com>
diff --git a/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv b/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv
index 21d3119..6bfb7a3 100644
--- a/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv
+++ b/hw/ip/keymgr/dv/env/keymgr_scoreboard.sv
@@ -91,7 +91,7 @@
forever begin
wait(!cfg.under_reset);
wait(cfg.keymgr_vif.keymgr_en != lc_ctrl_pkg::On);
- wipe_hw_keys();
+ if (current_state != keymgr_pkg::StReset) wipe_hw_keys();
wait(cfg.keymgr_vif.keymgr_en == lc_ctrl_pkg::On);
end
join_none
@@ -200,6 +200,9 @@
if (current_state == keymgr_pkg::StOwnerKey) update_result = NotUpdate;
else update_result = UpdateInternalKey;
current_state = get_next_state(current_state);
+
+ // set sw_binding_en after advance OP
+ void'(ral.sw_binding_en.predict(.value(1)));
end
keymgr_pkg::OpDisable: begin
update_result = UpdateInternalKey;
@@ -263,12 +266,14 @@
// if OP WIP or keymgr_en=0, will clear cfgen and below csr can't be written
if ((current_op_status == keymgr_pkg::OpWip || cfg.keymgr_vif.keymgr_en != lc_ctrl_pkg::On) &&
csr.get_name() inside {"control", "key_version",
- // TODO enable these after #4564 is solved
- //"sw_binding_0", "sw_binding_1", "sw_binding_2", "sw_binding_3",
+ "sw_binding_0", "sw_binding_1", "sw_binding_2", "sw_binding_3",
"salt_0", "salt_1", "salt_2", "salt_3"}) begin
`uvm_info(`gfn, $sformatf("Reg write to %0s is ignored due to cfgen=0", csr.get_name()),
UVM_MEDIUM)
return;
+ end else if (`gmv(ral.sw_binding_en) == 0 && csr.get_name() inside {"sw_binding_0",
+ "sw_binding_1", "sw_binding_2", "sw_binding_3"}) begin
+ return;
end else begin
void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask)));
end
@@ -622,7 +627,8 @@
// TODO, need designer to update for #4680
virtual function void wipe_hw_keys();
- if (current_state != keymgr_pkg::StReset) current_state = keymgr_pkg::StInvalid;
+ `uvm_info(`gfn, "Keymgr_en is Off, wipe secret and move state to Invalid", UVM_LOW)
+ current_state = keymgr_pkg::StInvalid;
endfunction
virtual function void reset(string kind = "HARD");
diff --git a/hw/ip/keymgr/dv/env/seq_lib/keymgr_cfgen_vseq.sv b/hw/ip/keymgr/dv/env/seq_lib/keymgr_cfgen_vseq.sv
index 81c5736..6a1b76e 100644
--- a/hw/ip/keymgr/dv/env/seq_lib/keymgr_cfgen_vseq.sv
+++ b/hw/ip/keymgr/dv/env/seq_lib/keymgr_cfgen_vseq.sv
@@ -50,9 +50,12 @@
// writing during cfgen is timing sensitive
// 1. make sure no other thread is accessing register
// 2. use backdoor check op_status again in case it's not OpWip after front-door read
+ // 3. make sure done isn't high, because if done is high, next cycle status won't be WIP
wait_no_outstanding_access();
csr_rd(ral.op_status, op_status_val, .backdoor(1));
- if (op_status_val == keymgr_pkg::OpWip) write_cfgen_gated_reg();
+ if (op_status_val == keymgr_pkg::OpWip && cfg.keymgr_vif.kmac_data_rsp.done) begin
+ write_cfgen_gated_reg();
+ end
end
endtask
@@ -64,11 +67,10 @@
randcase
1: csr_wr(ral.control, val);
1: csr_wr(ral.key_version, val);
- // TODO enable these after #4564 is solved
- //1: csr_wr(ral.sw_binding_0, val);
- //1: csr_wr(ral.sw_binding_1, val);
- //1: csr_wr(ral.sw_binding_2, val);
- //1: csr_wr(ral.sw_binding_3, val);
+ 1: csr_wr(ral.sw_binding_0, val);
+ 1: csr_wr(ral.sw_binding_1, val);
+ 1: csr_wr(ral.sw_binding_2, val);
+ 1: csr_wr(ral.sw_binding_3, val);
1: csr_wr(ral.salt_0, val);
1: csr_wr(ral.salt_1, val);
1: csr_wr(ral.salt_2, val);
diff --git a/hw/ip/keymgr/dv/env/seq_lib/keymgr_random_vseq.sv b/hw/ip/keymgr/dv/env/seq_lib/keymgr_random_vseq.sv
index fb5b7c1..b661ca8 100644
--- a/hw/ip/keymgr/dv/env/seq_lib/keymgr_random_vseq.sv
+++ b/hw/ip/keymgr/dv/env/seq_lib/keymgr_random_vseq.sv
@@ -10,6 +10,7 @@
task write_random_sw_content();
uvm_reg csr_update_q[$];
+ csr_random_n_add_to_q(ral.sw_binding_en, csr_update_q);
csr_random_n_add_to_q(ral.sw_binding_0, csr_update_q);
csr_random_n_add_to_q(ral.sw_binding_1, csr_update_q);
csr_random_n_add_to_q(ral.sw_binding_2, csr_update_q);
